FPGA可编程逻辑器件芯片XC2VP4-5FGG256I中文规格书

Chapter5 Configuration Details
Configuration Pins
Certain pins are dedicated to configuration (Table5-1), while others are dual-purpose
(Table5-3). Dual-purpose pins serve both as configuration pins and as user I/Os after
configuration. Dedicated configuration pins retain their function after configuration.
Configuration constraints can be selected when generating the Spartan®-6 device
bitstream. Certain configuration operations can be affected by these constraints. For a
description of the available constraints, see the software constraints guide.
Table 5-1:Spartan-6 FPGA Dedicated Configuration Pins
Pin Name Type(1)Description
DONE Bidirectional,
Open-Drain,
or Active Active High signal with programmable pull-up indicating configuration is complete.
0 = FPGA not configured
1 = FPGA configured
Refer to the BitGen section of UG628, Command Line Tools User Guide, for software settings.
PROGRAM_B(2, 3)Input Activ e Low signal with programmable pull-up, asynchronous full-chip reset.
TDI Input Test Data In. This pin is the serial input to all JTAG instruction and data registers.
The state of the TAP controller and the current instruction determine the register that
is fed by the TDI pin for a specific operation. TDI has an internal resistive pull-up to
provide a logic High to the system if the pin is not driven. TDI is applied into the
JTAG registers on the rising edge of TCK.
TDO Output Test Data Out. This pin is the serial output for all JTAG instruction and data registers.
The state of the TAP controller and the current instruction determine the register
(instruction or data) that feeds TDO for a specific operation. TDO changes state on
the falling edge of TCK and is only active during the shifting of instructions or data
through the device. TDO is an active driver output.
TMS Input Test Mode Select. This pin determines the sequence of states through the JTAG TAP
controller on the rising edge of TCK. TMS has an internal resistive pull-up to provide
a logic High if the pin is not driven.
TCK Input Test Clock. This pin is the JTAG Test Clock. TCK sequences the TAP controller and
the JTAG registers.
SUSPEND(3)Input Suspend Mode. Used to put the FPGA into suspend mode.
The SUSPEND pin should be Low during power up and configuration. If the
Suspend feature is not used, the SUSPEND pin must be connected to ground.
V FS Input Voltage source for eFUSE programming.(4)
V BATT Input Battery supply voltage for AES encryption key storage in SRAM.(4)
Configuration Packets
CRC Register
The Cyclic Redundancy Check register utilizes a standard 32-bit CRC checksum algorithm to verify bitstream integrity during configuration. If the value written matches the current calculated CRC, the CRC_ERROR flag is cleared and startup is allowed.
FAR_MAJ Register
Frame Address Register sets the starting block and column address for the next configuration data input. See Table 5-31.FAR_MIN Register
There are three types of write to FAR: •Write one word to FAR_MAJ: only updates the FAR_MAJ.•Write one word to FAR_MIN: only updates the FAR_MIN.
•
Write two words to FAR_MAJ: updates both FAR_MAJ and FAR_MIN; the data for FAR_MAJ will come first.
FDRI Register
Configuration data is written to the device by loading the command register with the WCFG command and then loading the Frame Data Input Register.
SEU_OPT R/W 6'h1d SEU frequency, enable and status.EXP_SIGN R/W 6'h1e Expected readback signature for SEU detection.
RDBK_SIGN W 6'h1f Readback signature for readback command and SEU.
BOOTSTS R 6'h20Boot History Register.
EYE_MASK R/W 6'h21Mask pins for Multi-Pin Wake-Up.CBC_REG
W
6'h22
Initial CBC Value Register.
Table 5-30:Configuration Registers (Cont’d)
Register Name R/W Address Description
Table 5-31:
Frame Address Register (MAJOR)
BLK
ROW MAJOR Bits
[15:12][11:8][7:0]0xxx
xxxx
xxxxxxxx
Table 5-32:Frame Address Register (MINOR)
Block RAM
(Reserved)MINOR Bits [15:14][13:10][9:0]xx
0000
xxxxxxxxxx
Table 6-7 lists the readback files.The design.rba and design.rbb files combine readback commands with expected readback data and the RBD file contains only expected readback data. Systems that use an RBD file for readback must store readback commands elsewhere. The actual readback data must be masked against an MSK or MSD mask file, as certain bits in the expected readback stream in the RBA , RBB , and RBD files should be ignored.
The readback command set files do not indicate when users must change the SelectMAP or JTAG interface from write to read control; the user must handle this based on the Readback Command Sequences described above.
Table 6-7:Readback Files File Extension File Type
BitGen Setting
Description
RBA
ASCII
-b and -g Readback An ASCII file that contains readback commands, rather than
configuration commands, and expected readback data where the configuration data normally is. This file must be used with
the MSK file RBB Binary
-g Readback Binary version of the RBA file. This file must be used with the
MSK file.
RBD ASCII
-g
Readback
An ASCII file that contains only expected readback data, including the initial pad frame. No commands are included.
This file must be used with the MSD file.
MSK Binary -m
A binary file that contains the same configuration commands as a BIT file, but replaces the contents of the FDRI write packet with mask data that indicate whether the corresponding bits in the BIT file should be compared. If a mask bit is 0, the corresponding bits in the readback data stream should be compared. If a mask bit is 1, the corresponding bit in the readback data stream should be ignored.
MSD ASCII
-g
readback
An ASCII file that contains only mask bits. The first bit in the MSD file corresponds to the first bit in the RBD file. Pad data in the actual readback stream are accounted for in the MSD and RBD files. If a mask bit is 0, that bit should be verified against the bitstream data. If a mask bit is 1, that bit should not be verified.
LL ASCII -l
An ASCII file that contains information on each of the nodes in the design that can be captured for readback. The file contains the absolute bit position in the readback stream, frame address, frame offset, logic resource used, and name of the component in the design.
Chapter 8:Readback CRC。