Altera Recent Advances in Die Stacking and 3D FPGA

*: Other Alternative solutions include glass or organic interposer, wafer-level fan-out, etc.
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Design and Architectural Consideration System-level Partitioning and Feasibility
IC2
Chip-to-chip bonding Thorough silicon via (10-100 um pitch ) Thin wafer handling & processing (25-100um thick) C4 Interconnect (100-250 um pitch)
IC1 IC2
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Agenda

Background Technology Trends 3D FPGA and Application Space Exploration Die Stacking Initiatives at Altera Summary
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What’s Driving the Need for 3D? Enhanced Capabilities Bandwidth expansion
Technology*
Die Size Number of Interconnects Int. Power Aggregate BW/W Tech. Availability
Wire Bonding
Small A few 100’s 1X 1X In volume production
2.5D (Silicon Interposer)
− High-bandwidth chip-to-chip interface (wide IO interface) − Opticanal processing capabilities
− Memory enhancement
Product feature set expansion
300-500X
IC2
100-1KX
Chip-to-chip bonding Thorough silicon via (10-100 um pitch ) Thin wafer handling & processing (25-100um thick) C4 Interconnect (100-250 um pitch)
Back End Centric Front End Centric
3D Integration (HMC, HBM, etc.) Silicon Interposer (FPGA, mixed signal, - Face-to-Face Stacking SoC, Proc + Memory) (Sony PSP) - Wire bond stacking Glass interposer - Organic Interposer - Fine-Pitch Substrate - Wafer level FO - Multi-Chip Package Cost Driven Performance Driven

Application requirements and product realization
− − − −
Partitioning of functions in different die Chip-to-chip interface Manufacturing aspects (KGD, test) Thermal and thermo-mechanical co-design Relative dimensions of on-chip and chip-chip features, design rules and impact to floorplan Keep out zone for TSVs Design trade-off High-frequency signaling through TSV and u-bump Signal isolation between stacked components
FPGAs FPGAs Cost/Power Balance Mid-range FPGAs SoC & Transceivers SoC & Transceivers
FPGAs Optimized for High Bandwidth
PowerSoCs High-efficiency Power Management
Today’s Remote Radio Units
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Energy Efficiency Normalized Energy Operation
Write 64b DFF 64b Integer Add Read 64b Register (64 x 32 bank) 8192-point FFT (per transform) Read 64b from DRAM
− Major semi companies across the supply chain have programs in place − High-volume application driver is needed for broader adoption

Next generation high-end FPGA applications require 2.5D/3D integrated memory
Recent Advances in Die Stacking and 3D FPGA
Arif Rahman, Program Director & Architect December 9th 2013
Summary

Early adoption of die stacking technology is underway in logic and logic-memory applications
− Derivative products
Energy efficiency Integration
− Fewer components
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Enhanced Memory Capability
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Integration and Form Factor Reduction
Yesterday’s Cell Towers

Implementation strategy
− − −

Other considerations
− −
Traditional system and board level design considerations are now part of 2.5D/3D integration
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Design Consideration Manufacturing Aspects
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Altera’s 3D Silicon Vision

Customer & application driven heterogeneous system integration in package
− Mix and match silicon IP − Integrated design flow − Integrated system test methodology

Testability and KGD
Design and technology interaction has to be considered much earlier in product planning process
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Altera’s Product Portfolio
CPLDs Lowest Cost, Lowest Power
FPGA
HardCopy ASIC ASSP
+
Memory ASIC CPU SoC FPGA

Maximum system performance Minimum system power Smallest form factor Reduced system cost
Package Substrate
Solder Balls (0.5-1 mm pitch)
Enabling Technologies for 3D Integration
Relative Scale 1-10X
IC1
On-chip interconnect (<0.1- 0.8 um pitch) Micro-bump (30-55 um pitch)

Scalability of 2.5D/3D interconnect vs. traditional interconnects Thermal budget and heat removal
− Thermally aware design
Component reliability
− Effects on die size, structural attributes, and material properties − FPGA specific requirements
IC1 IC2
1K-2.5KX
Package Substrate
Solder Balls (0.5-1 mm pitch)
5K-10KX
Comparison of 3D Integration Schemes
Courtesy: Chipworks
Intel: 4Mb Stacked SRAM in 65nm
− Driven by application requirements − Addresses pin bandwidth limitations