Introduction to AMBA Bus System
India-introduction-印度最全英文介绍
Indian Chai
咖喱角,印度三角饼
ART&LANGUAGE
LANGUAGE&LITERATURE
• ENGLISH AND HINDI (北印度 语 )LANGUAGE
DANCE
Belly Dance
• Northern Indian dance Manny pooley dance Cuttack dance • Southern Indian dance Bharatanatyam Getakeli dance
Etiquettes and taboos
Just Can't Say No
• Indians do not like to express 'no,' An Indian would be considered terribly rude if you said “no”.
•
•
Molden Temple Assault (1984)
• 4. Missile Launches and Green Revolution (20th century)
Hindu Baby Naming CeremonyNamkaran
• Mostly on the 11th or 12th day after delivery • Female relatives gather around the cradle and sing traditional folk songs • Bless the child and the mother together giving some gift items • A feast for all the family members
常用集成电路名词缩写汇总（第二版）
常⽤集成电路名词缩写汇总（第⼆版）重要说明整个集成电路的设计和⽣产链路很长,相关专有名称很多;本⽂对常见的集成电路相关的名词缩写进⾏了汇总,特别聚焦与集成电路设计领域,意在整理常⽤的数字电路/DC/PT/ICC/DFV/DFT/RTL/ATE相关⽅⾯的知识点,⽅便⼤家快速学习和掌握相关知识,⽅便⼤家查询;同时希望对学⽣将来的培训/⾯试等活动给予最⼤的帮助;⽂章按照字母排序的⽅式进⾏编排,⽅便⼤家查询;本次⽂章内容为第⼆次发布,我们将定期更新,逐步完善;欢迎⼤家提供相关信息⾄xgcl_wei微信号,帮助我们逐步完善内容,⽅便更多的⼈查询和使⽤,感谢您的参与,谢谢!英⽂全称中⽂说明ABV Assertion based verification基于断⾔的验证AES Advanced Encryption Standard⾼级加密标准,是美国政府采⽤的⼀种区块加密标准ADC Analog-to-Digital Converter指模/数转换器或者模数转换器AHB Advanced High Performance Bus⾼级⾼性能总线ALF Advanced Library Format先进（时序）库格式ALU Arithmetic and logic unit算数逻辑单元AMBA Advanced Microcontroller Bus Architecture⾼级微控制器总线体系ANT antenna天线效应AOP Aspect Oriented Programming⾯向⽅⾯编程APB Advanced Peripheral Bus⾼级外部设备总线API Application Programming Interface应⽤程序编程接⼝APR Auto place and route⾃动布局布线ARM Advanced RISC Machines 英国Acorn公司(ARM公司的前⾝)设计的低功耗成本的第⼀款RISC微处理器。
阿斯顿大学电子工程和计算机科学本科
阿斯顿大学电子工程和计算机科学- Electronic Engineering & Computer Science阿斯顿大学Aston University综合排名：37学校类型：公立- 综合性大学所在地：英国英格兰伯明翰录取率：15.00%每年学费：13万(人民币)是否有奖学金：是在校生人数：10351开学时间：秋季学校网址：院校介绍院校简介阿斯顿大学创立于1895年，是英国最具活力、最有创新精神的大学之一。
大学为学生提供组合式的本科和研究生学习、研究课程，与企业界保持密切的联系，根据社会、市场需求制定课程规划，因此，其毕业生就业率很高，十分受各大公司欢迎。
阿斯顿大学目前共有10351名学生，本科生7906人，研究生2066人，其中有来自世界100多个国家的2361名国际学生。
院系介绍阿斯顿大学共有4个大的教学学院，分别是商学院、工程和应用科学学院、生命和健康科学学院、语言和社会科学学院，四个学院下设20多个系，涵盖经济、金融、会计、管理、工程、计算机、电子电气、医药、语言、社科等专业领域。
另外，还有两个培训和职业发展学院。
学校最受欢迎的专业是商科和工程专业。
学术实力阿斯顿大学经过百年的发展，已成为英国最优秀的大学之一，并形成了自己的特色。
学校16个专业学科中，12个都排在英国前15位，尤其是商科、工程、医学等专业尤为出色。
阿斯顿大学的MBA课程在英国排名前10位，是AMBA成员之一。
工程、医学等专业也在英国大学排名中位列前茅。
校园环境阿斯顿大学位于伯明翰市中心区，各种学习、生活设施十分完备，拥有一流的校园网络系统和住宿条件。
伯明翰是英国的第二大城市，位于英格兰中心，是一座充满活力的多文化背景的城市，也是英国的商业、工业、休闲娱乐中心和交通枢纽，高速公路和铁路四通八达，伯明翰国际机场到市中心只需20分钟，乘火车去伦敦只需90分钟，开车需2小时。
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微小米 Cortex-M1 启用 ProASIC3L 开发套件中 Core8051s 微控制器系统的
Application Note AC427July 20141© 2014 Microsemi Corporation Loading and Debugging Core8051s Application From External Flash MemoryTable of ContentsPurposeThis application note describes how to load and debug application code from external flash memory available on the Microsemi ® Cortex-M1-enabled ProASIC3L Development Kit.IntroductionA Core8051s based microcontroller system is implemented on the Microsemi M1 enabled ProASIC3L field programmable gate array (FPGA). The external flash memory is interfaced to the Core8051s microcontroller system to load and debug the application code.ReferencesThe following references are used in this document:•Core8051s Based Hardware Tutorial •Core8051s Based Software User GuidePurpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Running the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Appendix A – Design and Programming Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Loading and Debugging Core8051s Application From External Flash Memory2Design RequirementsDesign OverviewA Core8051s IP based microcontroller system is developed with peripheral IPs such as CoreGPIO,CoreUARTapb, CoreWatchdog, CoreTimer, and CoreAPB3 that are implemented on the Microsemi Cortex-M1-enabled ProASIC3L Development Kit . An external Micron JS28F640J3D-75 flash memory is interfaced to the Core8051s microcontroller system. A simple application is loaded into the external Micron JS28F640J3D-75 flash memory to blink the on-board LEDs. Figure 1 shows the Core8051s microcontroller system.Table 1 • Design RequirementsDesign RequirementsDescriptionHardware RequirementsCortex-M1-enabled ProASIC3L Development Kit-Host PC or LaptopAny 64-bit Windows Operating System Software RequirementsLibero ® System-on-Chip (SoC)v11.3SoftConsolev3.4One of the following serial terminal emulation programs:• HyperTerminal• TeraTerm• PuTTY -Figure 1 • Core8051s Microcontroller SystemDesign Description3Design DescriptionThis design example has the following IPs that are available in Libero SoC catalog:•Core8051s : an 8-bit microcontroller IP core •CoreGPIO : provides up to 32-bit inputs and 32-bit outputs for general purpose •CoreUARTapb : a serial communication interface •CoreWatchdog : provides a means of recovering from software crashes •CoreTimer : for interrupt-generation and programmable counter •CoreAPB3: a bus component that provides advanced microcontroller bus architecture (AMBA3)advanced peripheral bus (APB3) fabric supporting up to 16 APB slavesThe following sections provide a brief description of each IP and its configuration:•Core8051s Description•Difference Between Core8051s and Core8051•CoreAPB3 Description•External Flash Memory Description•CoreTimer Description•CoreWatchdog Description•CoreUARTapb Description•CoreGPIO Description•Description of Core8051s based Microcontroller System•Memory Map•Software Development Description Core8051s DescriptionThe Core8051s is a high-performance, 8-bit microcontroller IP core. It is an 8-bit embedded controller that executes all ASM51 instructions and has the same instruction set as 80C31. It provides software and hardware interrupts. It eliminates redundant bus states and implements parallel execution of fetch and execution phases. The Core8051s uses one clock per cycle, and most of the one byte instructions are performed in a single clock cycle. Figure 2 shows the Core8051s architecture.Difference Between Core8051s and Core8051The Core8051s is smaller and more flexible than the Core8051.The microcontroller-specific features such as SFR-mapped peripherals, power management circuitry, serial channel, I/O ports and timers of the original 8051 are not present in Core8051s. The Core8051s contains the main 8051 core logic, but it does not have peripheral logic. The Core8051s has an advanced peripheral bus interface that can be used like the SFR (special function register) bus to easily expand the functionality of the core by connecting it to the existing advanced peripheral bus IPs. The Core8051s allows to configure the coreFigure 2 • Core8051s ArchitectureLoading and Debugging Core8051s Application From External Flash Memory4with the peripheral functions (timers, UARTs, I/O ports, etc.) that are required for the application.Configure the Core8051s Configurator GUI as shown in Figure 3.Refer to the Core8051s Handbook for more details.CoreAPB3 DescriptionThe CoreAPB3 is a bus component that provides advanced microcontroller bus architecture (AMBA3)advanced peripheral bus (APB3) fabric supporting up to 16 APB slaves, and a single APB master. The CoreAPB3 can be used with an APB3 master that does not have a built-in APB address decoding, such as Core8051s. A single APB3 master is connected to CoreAPB3. The master’s PSEL and PADDR signals are used within the CoreAPB3 to decode the appropriate PSELS slave select signals, and only one signal can be active at a time. This address decoding depends on the RANGESIZE hardware parameter/generic. Refer to the CoreAPB3 Handbook for more information.Figure 3 • Core8051s Configurator GUIDesign Description5Configure the CoreAPB3 Configurator GUI as shown in Figure 4.External Flash Memory DescriptionPart Number:•Micron JS28F640J3D-75Architecture: •64 Mbit (64 blocks)Performance: •75 ns Initial Access Speed, 25 ns 8-word and 4-word Asynchronous page-mode reads •32-Byte Write buffer (4 μs per Byte Effective programming time)System voltage: •VCC = 2.7 V to 3.6 V and VCCQ = 2.7 V to 3.6 V Enhanced security options for code protection:•128-bit Protection Register (64-bits unique device identifier bits, 64-bits user-programmable OTP (one time programmable) bits)•Absolute protection with VPEN = GND •Individual block locking •Block erase/program lockout during power transitions Figure 4 • CoreAPB3 Configurator GUILoading and Debugging Core8051s Application From External Flash Memory6Software:•Program and erase suspend support•Flash data integrator (FDI)•Common flash interface (CFI) compatibleThe external flash memory device can be accessed as 8- or 16-bit words. A command user interface (CUI) serves as the interface between the system processor and the internal operation of the device. A valid command sequence written to the CUI that initiates the device automation. An internal write state machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations.Flash operations are command-based, where command codes are first issued to the flash memory, then the flash memory performs the required operation. Refer to the flash memory Micron JS28F640J3D-75 datasheet for a list of command codes and flowcharts. Flash memory has a read-only 8-bit status register that indicates the flash memory status and operational errors. Four types of data can be read from the flash memory: array data, device information, CFI data, and device status.The flash memory is set to Read Array mode by default after power-up or reset. Executing the Read Array command sets the flash memory to Read Array mode and reads the output array data. The flash memory remains in Read Array mode until a different read command is executed. To change the flash memory to Read Array mode while it is programming or erasing, first issue the suspend command. After suspending the operation, run the Read Array command to set to Read Array mode. When the program or erase operation is subsequently resumed, the flash memory automatically sets to Read Status mode. Issuing the Read Device Information command places the flash memory in Read Device Information mode and reads the output of the device information. The flash memory remains in Read Device Information mode until a different read command is issued. Also, performing a program, erase, or block-lock operation changes the flash memory to Read Status Register mode.Array programming is performed by first issuing the single-word/byte program command. This is followed by writing the desired data at the desired array address. The read mode of the device is automatically changed to Read Status Register mode, which remains in effect until another read-mode command is issued.Erasing a block changes zeros to ones. To change ones to zeros, a program operation must be performed. Erasing is performed on a block basis - an entire block is erased each time when an erase command sequence is issued. Once a block is fully erased, all addressable locations within that block read as logical ones (FFFFh). Only one block-erase operation can occur at a time, and it is not allowed during a program suspend. To perform a block-erase operation, issue the block erase command sequence at the required block address. An erase or programming operation can be suspended to perform other operations, and then subsequently resumed. To suspend an on-going erase or a program operation, issue the suspend command to any address.All blocks are unlocked at the factory. Blocks can be locked individually by issuing the set block lock bit command sequence to any address within a block. Once locked, blocks remain locked when power cable is unplugged or when the device is reset. All locked blocks are unlocked simultaneously by issuing the clear block lock bits command sequence to any device address. The locked blocks cannot be erased or programmed.The sequence of the commands that must be given to the flash memory are written in an XML file. The XML files are provided with the SoftConsole software for the JS28F640J3D-75 flash memory located at: C:\Program Files (x86)\Microsemi\SoftConsole v3.4\Sourcery-G++\share\sprite\flash.Design Description7CoreTimer DescriptionThe CoreTimer is an APB slave that provides a functionality for the interrupt generations, and a programmable decrementing counter. It is configurable and programmable, and can be used in either continuous or one-shot modes. It is an essential element in many designs because it supports accurate generation of timing for precise application control. Refer to the CoreTimer Handbook for more information. Configure the CoreTimer Configurator GUI as shown in Figure 5.CoreWatchdog DescriptionThe CoreWatchdog is an APB slave that provides a means of recovering from software crashes. When the CoreWatchdog is enabled, the core generates a soft reset if the microprocessor fails to refresh it on a regular basis. The CoreWatchdog can be configured based on a decrementing counter, which asserts a reset signal if it is allowed to time out. The width of the decrementing counter can be configured as either 16 or 32-bits. The processor-accessible registers in CoreWatchdog provide a means to control and monitor the operation of the core. Refer to the CoreWatchdog Handbook for more information.Configure the CoreWatchdog Configurator GUI as shown in Figure 6.Figure 5 • CoreTimer Configurator GUIFigure 6 • CoreWatchdog Configurator GUILoading and Debugging Core8051s Application From External Flash Memory8CoreUARTapb DescriptionThe CoreUARTapb is a serial communications interface that is primarily used in the embedded systems.The controller can operate in either an asynchronous (UART) or a synchronous mode. In asynchronous mode, the CoreUARTapb can be used to interface directly to industry standard UARTs. The CoreUARTapb has an APB-wrapper that adds an APB interface allowing the core to be connected to the APB bus and controlled by an APB bus master. Unlike a standard 8051 UART, the CoreUARTapb includes a baud rate generator and so does not need a separate timer for the baud rate. Refer to the CoreUARTapb Handbook for more information.Configure the CoreUARTapb Configurator GUI as shown in Figure 7.Figure 7 • CoreUARTapb Configurator GUIDesign Description9CoreGPIO DescriptionThe CoreGPIO is an APB bus peripheral that provides up to 32-bit inputs and 32-bit outputs for general purpose. Refer to the CoreGPIO Handbook for more information.Configure the CoreGPIO Configurator GUI as shown in Figure 8.Figure 8 • CoreGPIO Configurator GUILoading and Debugging Core8051s Application From External Flash Memory10Description of Core8051s based Microcontroller System All the peripherals are interfaced to the Core8051s as shown in Figure 9.Refer to the Core8051s Based Hardware Tutorial for more information.Figure 9 • SmartDesign Top-Level Block DiagramDesign Description Instantiate a two port RAM on the SmartDesign top-level and configure it as shown in Figure10.Figure 10 • SRAM ConfigurationExternal memory buffer and multiplexer are configured as shown in Figure11 and Figure12.Figure 11 • External Memory Buffer ConfigurationLoading and Debugging Core8051s Application From External Flash MemoryMemory MapRight-click the Modify Memory Map to see the memory map as shown in Figure 13.Software Development DescriptionThe drivers are generated from firmware catalog for CoreTimer, CoreGPIO, CoreWatchdog, CoreTimer,and hardware abstraction layer (HAL). The HAL is used by drivers to access the hardware and also allows the control of interrupts.Refer to the Core8051s Based Software User Guide for more information.The Core8051s hardware design provides access to the external flash memory and internal SRAM. The Core8051s flash programming flow for Core8051s program memory is similar to the existing programming flow for Cortex-M1 flash program memory. The principal difference is, instead of specifying the location, size and the type of the program memory in a linker script, the program memory details are given in a text file (a memory-region-file) which uses the same syntax as the memory command section of a GCC linker script. The SoftConsole project configuration must be modified to specify the memory-region-file as an argument to the actel-map.exe helper program. Application code is written in main.c of the SoftConsole project to blink the on-board LED's.Figure 12 • Multiplexer ConfigurationFigure 13 • Memory MapRunning the Design ExampleRunning the Design ExampleTo run the design example,1.Download the design example at,/download/rsc/?f=Core8051s_ExtFlashIntSRAM_DF2.Double-click the Program Device under Program Design to program the Cortex-M1-enabledProASIC3L Development Kit in the Design Flow window, as shown in Figure14.Figure 14 • Program DeviceLoading and Debugging Core8051s Application From External Flash Memory3.Open the SoftConsole project after successfully programming the device, as shown in Figure15.Figure 15 • SoftConsole Project WindowRunning the Design Example4.Right-click the Core8051s_ExtFlashIntSRAM on the left pane and click Properties, as shown inFigure16. The Properties window is displayed as shown in Figure16.Figure 16 • Project Properties5.Double-click Settings under C/C++ Build on the left pane of Properties window.Loading and Debugging Core8051s Application From External Flash Memory6.Click Tools Settings tab on the right pane and select the Memory map generator, as shown inFigure 17.7.Enter actel-map -M../intel-28f640-1x8-code-memory.txt text in the Command field.Note:The “intel-28f640-1x8” XML file, which is at C:\Program Files (x86)\Microsemi\SoftConsolev3.4\Sourcery-G++\share\sprite\flash is used for loading and debugging the JS28F640J3D-75 flash memory.Figure 17 • Memory Map GeneratorRunning the Design Example8.Right-click Core8051s_ExtFlashIntSRAM on the left pane and click Debug As > DebugConfigurations…, as shown in Figure18. The Debug Configurations window is displayed.Figure 18 • Debug ConfigurationsLoading and Debugging Core8051s Application From External Flash Memory9.Right-click Microsemi Core8051s Target and click New to create a new debug configuration, asshown in Figure19.Figure 19 • New Debug Configuration10.Click Debug.Figure 20 • Debug ConfigurationsRunning the Design Example After launching the debug session, the flash programming operation starts. The erase and writeoperations are shown in Figure21.Figure 21 • Flash ProgrammingLoading and Debugging Core8051s Application From External Flash Memory11.Start PuTTY (with settings 57600 baud rate, 8 data bits, and No parity), and choose Resumefrom the Run menu. The LEDs are scanned on the Cortex-M1-enabled ProASIC3L Development Kit in the forward and reverse direction. The messages are displayed as shown in Figure 22.12.Terminate and relaunch the debug session.13.Set break points at 60, 115 and 149 lines of main.c.14.Choose Resume from the Run menu.15.Choose Step Over from the Run menu until it reaches the 115 line of main.c. The “RunningCore8051s Application from External Flash Memory” message is displayed as shown in Figure 23.Figure 22 • Application Running From External Flash MemoryFigure 23 • Debug CodeRunning the Design Example2116.Choose Step Over from the Run menu. While stepping over the code, the LEDs blinks on theMicrosemi Cortex-M1-enabled ProASIC3L Development Kit . The message is displayed as shown in Figure 24.Figure 24 • Step OverLoading and Debugging Core8051s Application From External Flash Memory2217.Right-click Core8051s_ExtFlashIntSRAM Debug [Microsemi Core8051 Target] and clickTerminate and Remove the debug session as shown in Figure 25.18.Choose Exit from the File menu to close the SoftConsole project.19.Unplug the USB cables and power supply cable and plug-in the power supply cable. The sameLED scanning application runs from the non-volatile external flash memory.ConclusionThis application note describes how to load and debug the Core8051s application from the external flash memory using SoftConsole. The example design serves as a starting point to other Core8051s designs.It includes a Core8051s based system, firmware drivers, and a sample LED scanning application that runs from the external flash memory.Appendix A – Design and Programming FilesYou can download the design files from the Microsemi SoC Products Group website:/download/rsc/?f=Core8051s_ExtFlashIntSRAM_DFThe design file consists of Libero project and programming file. Refer to the Readme.txt file included in the design file for directory structure and description.Figure 25 • Terminate and Remove Debug SessionList of Changes 23List of ChangesThe following table lists the critical changes that were made in the current version of the application note.DateChanges Page Revision 1(July 2014)Initial Release.NA51900295-1/7.14© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996E-mail:***************************Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense and security, aerospace, and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs, and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has approximately 3,400 employees globally. Learn more at .。
AMBA2_subsystem_design
The AMBA 2.0 Specification
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AMBA interfaces are the de-facto standard in the industry First released in 1995 Specification downloaded over 15,000 times Free license to download and implement
Question for the Audience Is this data still accurate for 2005?
49% 48%
Embedded Processor Used
Base = Use an Embedded Processor
9%
2004 2003
ARM Dominates!
SNUG San Jose 2005 (8)
Memory Controller and DMA
• 8 Channels, scatter gather • FIFO per channel, arbitration
AMBA High speed Bus - AHB
DMA Controller
M S
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Access to all IP blocks that are required? Wall clock Weeks to Months
SNUG San Jose 2005 (17)
IP Reuse is Required for Productivity
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IP Blocks are becoming a larger percentage of the overall design IP block choice becomes critical to the overall success of your design
CoreDDR_LiteAXI v2.0 50200853 手册说明书
HB0853Handbook CoreDDR_LiteAXI v2.0Microsemi Corporate Headquarters One Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996E-mail: *************************** © 2019 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.About MicrosemiMicrosemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees globally.Learn more at .Contents1Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.1Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2Core Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3Supported Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.4Device Utilization and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.5References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 4Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44.1Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.2Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 6Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76.1License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.2RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.3SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.4Configuring CoreDDR_LiteAXI in SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.5Simulation Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.6Synthesis in Libero SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86.7Place-and-Route in Libero SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7Register Map and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 8System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10FiguresFigure 1High Level Block Diagram of CoreDDR_LiteAXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2SmartDesign CoreDDR_LiteAXI Instance View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3SmartDesign CoreDDR_LiteAXI Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4CoreDDR_LiteAXI System Integration Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10TablesTable 1CoreDDR_LiteAXI Utilization and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table 2CoreDDR_LiteAXI I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 3CoreDDR_LiteAXI Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Revision History1Revision HistoryThe revision history describes the changes that were implemented in the document. The changes arelisted by revision, starting with the most current publication.1.1Revision 1.0Revision 1.0 is the first publication of this document. Created for CoreDDR_LiteAXI v2.0.Introduction2IntroductionCoreDDR_LiteAXI IP converts AXI4 transactions to PolarFire DDR Native interface transactions that access DDR memory through AXI4 interface. This IP is a lighter version of AXI to DDR Native interface,which supports only the AXI INCR transactions.2.1FeaturesCoreDDR_LiteAXI supports the following features:•AXI4 protocol•1:1 synchronous clock•Interface data widths: 128, 256, and 512-bits •32 to 40-bit AXI address bus •Single or burst transfers•Only AXI4 increment transfers •Maximum of 16-bit ID width2.2Core VersionThis handbook is for CoreDDR_LiteAXI version 2.0.2.3Supported Families•PolarFire ®2.4Device Utilization and PerformanceUtilization and performance data is as shown in Table 1, for PolarFire (MPF300T) device family. The data provided in these tables are indicative only. The overall device utilization and performance of the core is system dependent.Note:The data in this table was achieved using default synthesis and layout settings. Frequency (in MHz) wasset to 200 and speed grade set to -1.2.5ReferencesAMBA AXI protocol specification:UG0676: PolarFire FPGA Memory Controller User GuideTU0775: PolarFire FPGA: Building a RISC-V Processor Subsystem TutorialTable 1 • CoreDDR_LiteAXI Utilization and PerformanceData Bus Width (bits)Logic Elements Memory Blocks Performance in MHz Combinational %Sequential %uSRAM LSRAM 12829490.9825540.85392432564624 1.544331 1.4541622351279372.6578342.62429232Functional Description3Functional DescriptionCoreDDR_LiteAXI consists of an AXI4 slave interface, read and write data FIFOs, read ID FIFO, readand write response generators, and Native Interface transaction generator. The following figure showsthe high level block diagram of CoreDDR_LiteAXI.The state machine analyzes the AXI4 transactions and efficiently sends those transactions to DDRNative Interface. This IP handles the AXI handshaking, and monitors the FIFO levels to make sure theydo not overflow.The read and write FIFOs are used to allow posting of transactions and to hold data that may be neededfor read and write transactions.The Native Interface transaction generator initiates the transactions on the DDR native interfacedepending on the AXI transaction size. In case of write, the number of bytes are calculated based on thesum of the bytes in each beat (as per the number of ones in WSTRB). CoreDDR_LiteAXI uses the DDRNative interface data mask signal (l_dm_in) according to the WSTRB signal (that is, the DDR subsystemmust be configured to use the data mask signal).AXI read transaction generator block provides data to AXI read channel when read FIFO is not empty.The CoreDDR_Lite AXI IP handles the simultaneous read and write transactions to the same address byholding the read transaction until the completion of write transaction.Limitations:1.FIXED and WRAP type bursts are not supported.2.AXI transactions with data before address are not supported.4Interface4.1PortsThe following table describes the CoreDDR_LiteAXI I/O signals.Table 2 • CoreDDR_LiteAXI I/O SignalsPort Name Type DescriptionClocks and ResetACLK Input Clock for user logic generated by the DDR subsystem(SYS_CLK). All native interface signals are synchronous tothis clock.ARESET_N Input Active-low asynchronous reset.AXI interface signalsAWID[AXI_ID_WIDTH - 1:0]Input Write address ID.AWADDR[AXI_ADDR_WIDTH - 1:0]Input Write address.AWLEN[7:0]Input Burst length.AWSIZE[2:0]Input Burst size.AWBURST[1:0]Input Burst type. Only INCR burst type is supported. AWVALID Input Write address valid.AWREADY Output Write address ready.WDATA[AXI_DATA_WIDTH – 1:0]Input Write data.WSTRB[AXI_DATA_WIDTH/8 -1:0]Input Write strobes.WLAST Input Write last.WVALID Input Write valid.WREADY Output Write ready.BID[AXI_ID_WIDTH – 1:0]Output Response ID tag.BRESP[1:0]Output Write response.BVALID Output Write response valid.BREADY Input Response ready.ARID[AXI_ID_WIDTH – 1:0]Input Read address ID.ARADDR[AXI_ADDR_WIDTH – 1:0]Input Read address.ARLEN[7:0]Input Burst length.ARSIZE[2:0]Input Burst size.ARBURST[1:0]Input Burst type.ARVALID Input Read address valid.ARREADY Output Read address ready.RID[AXI_ID_WIDTH – 1:0]Output Read ID tag.RDATA[AXI_DATA_WIDTH – 1:0]Output Read data.RRESP[1:0]Output Read response.RLAST Output Read last.4.2Configuration ParametersThe following table describes the configurable parameters for CoreDDR_LiteAXI. If a setting other than the default is required, use the configuration dialog box in SmartDesign to select appropriate values for the configurable options.RVALID Output Read valid.RREADYInput Read ready.Native Interface SignalsL_ADDR[LOCAL_BUS_ASIZE – 1:0]Input Native interface address sizes: DDR4 = 39 bits, DDR3 = 36 bits, and LPDDR3 = 36 bits.L_B_SIZE[BURST_SIZE_WIDTH – 1:0]Input Native interface burst length in terms of bytes. It must be in multiples of the native interface bus width.L_R_REQ Input Native interface read request.L_W_REQ Input Native interface write request.L_BUSYOutputSpecifies that the subsystem is busy and is not accepting new requests. A command is accepted on any clock cycle where L_R_REQ or L_W_REQ is set, and L_BUSY is low. If L_BUSY is high when L_R_REQ or L_W_REQ is set, the request may be kept asserted (along with the desired L_ADDR, L_B_SIZE and L_AUTO_PCH values) until L_BUSY goes low.L_D_REQ OutputRequests data on the native interface write data bus(L_DATAIN) during a write transaction. Asserts one clock cycle prior to when data is required.L_R_VALIDOutput Data-valid indication for data on the native interface read data bus (L_DATAOUT).L_DATAIN[AXI_DATA_WIDTH – 1:0]InputInput data bus. This data bus is eight times the width of the SDRAM device data bus.Memory width (bits): 16, 32, 64Input data bus (bits): 128, 256, 512L_DATAOUT[AXI_DATA_WIDTH – 1:0]Output Output data bus. This data bus width is same as L_DATAIN width.L_DM_IN[AXI_DATA_WIDTH/8 – 1:0]InputIndividual byte masks during data write.Note:All signals are Active High (logic’1’) unless noted.Table 3 • CoreDDR_LiteAXI Configuration OptionsParameter Name Valid Range Default DescriptionAXI_ID_WIDTH 4-164AXI4 slave IF ID width.AXI_ADDR_WIDTH 32-4032AXI4 address width. Must be less or equal to LOCAL_BUS_ASIZE.AXI_DATA_WIDTH 128, 256, 512128AXI4 data width. It should be same as Native IF data bus width of DDR subsystem.LOCAL_BUS_ASIZE32-4036Native IF address width.Table 2 • CoreDDR_LiteAXI I/O SignalsTiming Diagrams5Timing DiagramsCoreDDR_LiteAXI IP complies with the AMBA® AXI4 protocol specifications timings.6Tool Flow6.1LicenseCoreDDR_LiteAXI does not require a license.6.2RTLThe complete RTL source code is provided for the core and testbenches.6.3SmartDesignCoreDDR_LiteAXI is pre-installed in the SmartDesign IP Deployment design environment. An exampleinstantiated view is as shown in Figure2. The core can be configured using the configuration GUI withinSmartDesign, as shown in Figure3.For information on using SmartDesign to instantiate and generate cores, refer to the Using DirectCore inLibero® SoC user guide.Figure 2 • SmartDesign CoreDDR_LiteAXI Instance View6.4Configuring CoreDDR_LiteAXI in SmartDesignThe following figure shows the CoreDDR_LiteAXI Configurator in SmartDesign.Figure 3 • SmartDesign CoreDDR_LiteAXI Configurator6.5Simulation FlowsThe User Testbench for CoreDDR_LiteAXI is not included.6.6Synthesis in Libero SoCClick the Synthesis icon in Libero SoC. The Synthesis window appears, displaying the Synplicity®project. Set synplicity to use the Verilog 2001 standard, if Verilog is being used. To run synthesis, selectthe Run icon.6.7Place-and-Route in Libero SoCClick the Layout icon in the Libero SoC to invoke Designer. CoreDDR_LiteAXI requires no special place-and-route settings.Register Map and Descriptions7Register Map and Descriptions CoreDDR_LiteAXI does not contain any registers.System Integration8System IntegrationThe following is an example of the system integration diagram for CoreDDR_LiteAXI.This design example contains the CoreAXI_LiteAXI (axi2ni_0) which is interfaced with Mi-V softprocessor and DDR3 subsystem. The soft processor can perform read/writes or execute code fromDDR3 memory. This design example is similar to the TU0775: PolarFire FPGA: Building a RISC-VProcessor Subsystem Tutorial design and uses the DDR3 Native interface along with theCoreDDR_LiteAXI IP.Figure 4 • CoreDDR_LiteAXI System Integration Diagram。
外文文献原稿和译文--公交车自动报站系统
The bus stops system automatically1、The bus is automatically stops the background and significanceThe people of car out for provides convenient service, while the bus stops directly affect the quality of the service. Traditional stops by the crew artificially, and in this way because of its poor and working intensity effect is too great, in many big cities have been eliminated. In recent years, with the development of science and technology progress and microcomputer technology in many fields has been widely used. In the acoustic field, with various pronunciation chip microcomputer technology, can complete combined speech synthesis technology, makes the car stops controller is realized for citizens becomes possible, and thus provide a more personalized service. In view of the traditional bus stops system deficiency, combined with the use of public transport vehicle characteristics and practical operating environment, the design of a single-chip microcomputer control bus stops system automatically. The bus stops the design of automatic device is mainly to compensate for changing the traditional voice stops device must have driver control can work backward way, pitted, automatic station broadcasts six-foot-tall service term for the public and provide more humanized more perfect service.2. The system design of each componentThis system is designed hardware circuit design part: use AT89C51 as controller, through ISD4004 pronunciation chip establish speech, forming a variety of information and use the voice messages broadcast speech information and tips amplifier, and using speech, LED digital display for standing count. When the bus arrived at one site, use the keyboard control the system work, through the yukon voice circuits output speech information and tips, stood in several information LED digital tube display. The whole system hardware design including keyboard circuit and reset circuit, display driver circuit, display circuit, memory expansion circuit module. In order to realize the bus stops, namely in speech automatic six-foot-tall; and when voice prompt information and automatic reporting service term, while utilizing of LED dot matrix circuit Chinese displaying. This design is required to exploit the AT89C51 as the master control circuit design of chips, auxiliary circuit requirements including voice circuits, Chinese dot matrix display circuit, the power supply circuit, etc. The CPU control and control signals, pronunciation chip, output indicator light component. The bus station is automatically stops the car wheel design, to count the pulse Angle, will count value compared with preset value, can determine moments, attain the precise automatically stops the purpose. USES AT89C51 as main control chip, combining to foreign pulse count ISD4004 output voice pronunciation chip. System consists of pulse detection, pulse count, CPU control and control signals, pronunciation chip, output indicator light component.About AT89C51 chip: A T89C51 it mainly consists of for the following parts: 1 eight central processing unit (CPU), piece you in memory, the pieces (Flash RAM, 4 of 8 bits two-way addressable I/O port, 1 full-duplex UART (general asynchronous receiver transmitter) serial interface, 2 16 timer/counters, multiple priority nested interrupt structure, and a piece inside oscillator and clock circuit. In AT89C51 structure, the most striking characteristics of internal contains Flash memory is, while in other aspects of the structure of the Intel corporation, the and the structure of the 8051 no much difference.Main performance:1. With MCS - 51 compatible2. 4K bytes programmable flashing memory Life expectancy: 1000 times to write/wipe cycle Data retention time: 10 years3. All the static job: 0Hz - 24Hz4. Tertiary program memory lock5. 128 * 8 bits inside6. 32 programmable I/O lines7. Two 16 timers, counter8. Five interrupt source9. Programmable serial channels10. Slice clock circuit oscillator and withinThe design of pulse detection circuit:The design of the key is that the rotor turn lap count, considering the vehicles will be running in a complex environment, and the hall componets are resistant to vibrate, afraid of dust, grease, water vapor and salt fog the advantages of the pollution or corrosion, so adopt reliable hall element DN6848 as signal acquisition device, again by photoelectric couplers 4N25 input to microcontroller. Photoelectric coupler current transmission 10% ~ 25%, than for less than 10us response time.About speech output circuit designThis series of chip required by the microprocessor or micro controller series through serial peripheral interfaces and serial interface addressing and control. The recording data is stored method of multistage storage is through ISD patent technology implementation, with sound and audio signals directly in the natural form of solid state memory, thus providing high quality replay the fidelity of speech.ISD4004 voice recording devices for 6.4 kHZ sampling frequency, time and recording a single chip 8 points, 10 points, 12 points, 16 points several, and its use of built-in FLASH memory cost nonvolatile CaXie memory, this fast data, and it is not lost power save data department needs power consumption. The typical stored information can save time up to 100 years, the same storage unit can be repeated be recorded 10 million times.IAD4004 chip audio output pin can drive a five thousand uefa load, when device after power up, change the power output pins for 1.2 v. to this design of chosen amplifier is LM386 is for low voltage application design audio amplifier, the working voltage of 6V, maximum distortion degree of 0.2, power frequency response to 20 ~ 100 KHZAbout LED display output design:This circuit USES 16 * 256 destem to display 16 16 * 16 Chinese characters, using the video memory U14 to deposit the characters bitmap information. Screen points page 32, each page 16 line 8 column LED by constitute the light emitting diode, destem with a four - 16 decoder 74LS154 decode, will address A0 - A3 decode formed by two do signal, 4-16 decoder 74LS154 form a 5-32 decoder, carries on the page decode, will address A4 - A8 decode form page, choose communication, respectively, to choose a 74LS244 general 74LS244 data through this system to a page in a line of eight leds into display information.3. The characteristics of the system and advantageThis system greatly improve the accuracy of bus stops, and reliability. Improving the service quality of the bus system. Promote the city economic development and harmonious development of traffic changes. Made up for changing the traditional voice stops device must have drivercontrol can work means, in the bus stops behind when the station broadcasts, automatic six-foot-tall service term for the public and provide more humanized more perfect service.公交车自动报站系统1.公交车自动报站器的背景及意义共汽车为外出的人们提供了方便快捷的服务，而公共汽车的报站直接影响服务的质量。
XMC1300 Boot Kit用户手册说明书
XMC1300 Boot KitPart Number: KIT_XMC13_BOOT_001Features∙XMC1300 Microcontroller with 200KB Flash∙Detachable SEGGER J-Link∙Motor control timer∙MATH co-processor∙Motor position interface∙Digital power conversionPLEASE SEE THE FOLLOWING PAGES FOR USERS MANUALXMC1300 CPU Card For XMC1000 FamilyCPU-13A-V1XMC1300 CPU CardBoard User's Manual Revision 2.0, 2013-12-18Edition 2013-12-18Published byInfineon Technologies AG81726 Munich, Germany© 2013 Infineon Technologies AGAll Rights Reserved.Legal DisclaimerThe information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.InformationFor further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office ().WarningsDue to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or otherTrademarks of Infineon Technologies AGAURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™,EconoPACK™,EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™,my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.Other TrademarksAdvance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of D ECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektr onix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.Last Trademarks Update 2011-11-11Table of Contents1Overview (7)1.1Key Features (7)1.2Block Diagram (7)2Hardware Description (8)2.1Power Supply (8)2.2Reset (9)2.3Clock Generation (9)2.4Boot Option (9)2.5Debug Interface and virtual com port (9)2.6LED (9)2.7Potentiometer (10)2.8Application Card connector (10)3Production Data (12)3.1Schematics (12)3.2Layout and Geometry (15)3.3Bill of Material (15)List of FiguresFigure 1Block Diagram of XMC1300 CPU Card (7)Figure 2XMC1300 CPU Card (8)Figure 3Power Supply circuit (8)Figure 4LEDs circuit (10)Figure 5Potentiometer Circuit (10)Figure 6Pinout of the 2x30 pin edge connector (11)Figure 7Schematic 1 of 2 XMC1300 CPU Card (13)Figure 8Schematic 2 of 2 XMC1300 CPU Card (14)Figure 9XMC1300 CPU Card layout and geometry (15)List of TablesTable 1Debug connector X201 (9)Table 2LEDs Pinout (10)Table 3XMC1300 CPU Card (15)IntroductionThis document describes the features and hardware details of the XMC1300 CPU Card. This board is mounted with ARM® Cortex TM-M0 based XMC1300 Microcontroller from Infineon Technologies AG. This board is part of Infineon’s XMC1000 Application Kits1 OverviewThe XMC1300 CPU board (CPU-13A-V1) houses the XMC1300 Microcontroller and a 2x30 pin edge for application expansion. The board along with application cards (e.g. Colour LED Card, White LED Card) demonstrates the capabilities of XMC1300. The main use case for this board is to demonstrate the generic features of XMC1300 device including tool chain. The focus is safe operation under evaluation conditions. The board is neither cost nor size optimized and does not serve as a reference design.1.1 Key FeaturesThe XMC1300 CPU Card is equipped with the following features∙XMC1300 (ARM®Cortex TM-M0 based) Microcontroller, TSSOP38∙Connection to XMC1300 application cards via card edge connector∙Detachable J-Link debugger and UART virtual COM port, with micro USB connector∙Six user LEDs∙Potentiometer, connected to analog input P2.5∙Power supply via Micro-USB connector1.2 Block DiagramFigure 1 shows the functional block diagram of the XMC1300 CPU Card.Features include:−On board Debugger, for downloading and debugging of application code−Virtual com port for uart communication with terminal program e.g. Hyperterminal.−2x30 card edge connector, for extension to application card e.g. Colour LED Card and White LED Card.− 6 User LEDs connected to GPIO P0.0, P0.1, P0.6, P0.7, P0.8 and P0.9−Variable resistor R110 connected to Analog input P2.5−All the pins of XMC1300 are accessible via the connector JP101, JP102, JP103 and JP104Figure 1 Block Diagram of XMC1300 CPU Card2 Hardware DescriptionThe following sections give a detailed description of the hardware and how it can be used.Figure 2 XMC1300 CPU Card2.1 Power SupplyXMC1300 CPU Card is powered from the micro USB connector (5V); however, there is a current limit that can be drawn from the host PC through USB. If the CPU-13A-V1 board is used to drive other application board (e.g. Colour LED Card, White LED Card) and the total current required exceeds 500mA, then the board needs to be powered by external power supply connected to VDD and GND connection on board.The XMC1300 device can operate by power supply of 1.8V till 5.5Vdc. On this board, 5Vdc is used to power the XMC1300 device. However, if user wants to power the XMC1300 device with 3.3Vdc, then, set Jumper at JP201 to 3.3V side.Figure 3 Power Supply circuit2.2 ResetXMC1300 does not have a reset pin, hence, user can unplug and replug the USB cable to achieve power-on master reset.2.3 Clock GenerationNo external clock source is required. XMC1300 has two internal oscillators DCO1 and DCO2. DCO1 has a clock output of 64MHz. DCO2 is used to generate the standby clock running at 32.768KHz which used for Real Time Clock too. The main clock, MCLK and fast peripherial clock, PCLK, are generated from DCO1’s output.2.4 Boot OptionAfter power-on reset with master reset, XMC1300 device will enter different boot mode depend on the BMI (Boot Mode Index) value stored in XMC1300’s f lash configuration sector 0 (CS0). The BMI value pre-programmed on the XMC1300 device on CPU Card is User mode with debug enabled, hence, the XMC1300 device will start to run the application code in its embedded Flash after power on reset.2.5 Debug Interface and virtual com portXMC1300 CPU Card has on-board debugger which supports Serial Wire Debug (SWD) and Single Pin Debug (SPD) as debug interface. SPD is a proprietary debugging protocol from Infineon Technologies and it requires only 1 pin for debug communication. The debugger also provides a virtual COM port which support UART communication via P1.3 (rx-in) and P1.2 (tx-out) of XMC1300. There is a 2x5 pins Header Debug connector X201.Table 1 Debug connector X2012.6 LEDThe port pins P0.0, P0.1, P0.6, P0.7, P0.8 and P0.9 are connected to LED101, LED102, LED103, LED104, LED105 and LED106 respectively. The LED is turn on by output ‘L ow’ at the port pin.Figure 4 LEDs circuit2.7 PotentiometerXMC1300 CPU Card provides a potentiometer R110 for ease of use and testing of the on-chip analog to digital converter. The potentiometer is connected to the analog input P2.5. The analog output of the potentiometer is the same the VDDP voltage supplied to the XMC1300 device.Figure 5 Potentiometer Circuit2.8 Application Card connectorXMC1300 CPU Card has a 2x30 pins card edge connector. The mating connector is SAMTEC HSEC8-130-01-L-RA-XX.Figure 6 Pinout of the 2x30 pin edge connector3 Production Data3.1 SchematicsThis chapter contains the schematics for the XMC1300 CPU Card:∙Figure 7: CPU, Pin Headers, Potentiometer and LED and 60pin Edge connector ∙Figure 8: On-board Debugger, Power Supply3.2 Layout and GeometryFigure 9 XMC1300 CPU Card layout and geometry 3.3 Bill of Materialw w w.i n f i n e o n.c o m。
amba协议手册
AMBA协议手册一、AMBA概况AMBA（Advanced Microcontroller Bus Architecture）协议，又被称为AMBA 2.0，是一种针对高性能、高吞吐量嵌入式系统设计的总线协议。
它定义了在一个或多个嵌入式处理器和多个外设之间的高效通信方式，广泛应用于各类芯片和集成电路中。
AMBA为微控制器、数字信号处理器（DSP）以及通信和消费电子等多种应用提供了优秀的性能表现。
二、AMBA版本历史AMBA的发展经历了几个重要的版本，每个版本都增加了新的特性和功能。
1.AMBA 1.0：这个版本主要定义了简单的主从设备间的通信方式，包括数据传输和地址协议。
2.AMBA 2.0：在AMBA 2.0中，引入了更复杂的特性，如猝发传输和更高级的地址和数据传输控制。
3.AMBA 3.0：这个版本引入了新的特性，如外部总线的对齐和分区、扩展的地址空间和数据字节宽度的动态调整。
4.AMBA 4.0：随着芯片设计的不断发展和系统性能的持续提高，AMBA 4.0为高带宽总线传输和高频率时钟提供了支持。
三、AMBA组成部分AMBA协议主要包括以下组成部分：1.AXI（Advanced eXtensible Interface）：AXI是一种高性能、高吞吐量的总线接口，用于连接主设备和从设备。
它支持多个通道的数据传输，每个通道都有数据写和数据读两个通道。
2.ACE（Advanced Coherency Enhanced）：ACE是AMBA的一种扩展，提供了更高级的内存一致性保证，确保在多处理器系统中数据的一致性。
3.APB（Advanced Peripheral Bus）：APB是一种简单、低速的总线接口，主要用于连接低速外设。
它基于传统的Peripheral Bus，但提供了更高的性能和更小的芯片面积。
4.AHB（Advanced High-performance Bus）：AHB是一种高性能的总线接口，主要用于连接高性能的处理器和高速存储器。
智能融合2 FPGA 微控制器子系统 BFM 仿真指南说明书
SmartFusion2 FPGA Microcontroller Subsystem BFM Simulation GuideSmartFusion2 FPGA Microcontroller Subsystem BFM Simulation Guide Table of ContentsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Cortex-M3 BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 MSS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Fabric Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53BFM Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Writing and Verifying Fabric GPIO Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 BFM Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9A Product Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11IntroductionThe SmartFusion2 FPGA's Microcontroller Subsystem (MSS) can be simulated using ModelSim or othersupported third-party simulators. MSS Simulation is performed using a Bus Functional Model (BFM)strategy. Simulation can be useful in the following situations:•Verifying the connectivity and addressing of MSS peripherals.•Verifying the DDR Memory configuration and addressing with your vendor's memory (subject to availability of appropriate HDL memory models).•Verifying addressing of peripherals in the Fabric that are connected to the MSS using the 32-bit or 64-bit Fabric Interface Controllers (FICs).This document describes how to simulate your SmartFusion2 FPGA design that includes the MSS.Note:Only one MSS component is allowed in your design.1 – Simulation ModelsCortex-M3 BFMThe SmartFusion2 MSS' Cortex-M3 processor is modeled with Microsemi's AMBA Bus Functional Model(BFM). Refer to Microsemi's DirectCore AMBA BFM User's Guide for details on the supportedinstructions and syntax of the BFM commands.MSS PeripheralsTo minimize simulation time, certain peripherals in the SmartFusion2 MSS do not have full behavioralmodels. Instead they are replaced with memory models that will output a message indicating when thememory locations inside the peripheral have been accessed. This means that the peripheral outputsignals do not toggle based on any writes to registers, or react to any signal inputs on the protocol pins.The peripherals without full behavioral models are:•CAN•Ethernet•MMUART•I2C•PDMA•RTC•SPI•USB•WatchDogThe peripherals that have full behavioral models are:•AHB Bus Matrix•eNVM•Fabric Interface Controllers•GPIO•MDDR•MSS Clock Conditioning CircuitFabric PeripheralsRTL level simulation models are available to simulate Fabric peripherals.2 – Simulation FlowFigure 2-1 illustrates the hierarchy of a SmartFusion2 design that includes the MSS and two fabric peripherals. The MSS component is instantiated in a top level SmartDesign component with fabric peripherals. The fabric peripherals 1 and 2 are two instances of CoreGPIO (32-bits each). In this scenario, generating the MSS component produces the following four *bfm files for simulation. These BFM files are generated in the <project_dir>/simulation foldertest.bfm - Contains the BFM commands to initialize the simulation model. The BFM commands in this file are generated based upon your MSS configuration. This file is analogous to the system boot code, as it initializes the MSS and calls your user application. This file contains an include directive for user.bfm, and a procedure call to user_main (see below). Do not edit this file.user.bfm - You can customize this file to emulate CortexM3 transactions in your system. This file contains an include directive to subsystem.bfm. The memory map of MSS and Fabric peripherals is specified inside subsystem.bfm, you can refer to those defines inside user.bfm. This file is analogous to your user application code. This file contains the procedure user_main, which is analogous to your main function in your application. You can add BFM instructions and procedures to user.bfm to emulate your application. Refer to Microsemi's DirectCore AMBA BFM User's Guide for details on the supported instructions and syntax of the BFM.subysystem.bfm - Contains the memory map of all subsystems. You do not have to modify this file. Base addresses of AMBA slaves connected to the MSS via recognized AMBA buses in your design can be found here. This includes Fabric peripherals (connected to the MSS via the FICs) as well as MSS (Hard) peripherals.Peripheral_init.bfm - Contains the BFM commands to initialize the MDDR/FDDR and SERDESIF. If your top level design contains any MDDR/FDDR or SERDESIF, Libero SoC automatically generates the peripherals_init.bfm file to initialize these peripherals. During simulation, the simulator executes the BFM commands in the peripherals_init.bfm before executing the user BFM commands. Do not edit this file.The BFM files are summarized in Table 2-1.Figure 2-1 •Example MSS DesignThe BFM files can be accessed via the Files tab in the Simulation folder (as shown in Figure 2-2). To view the file content, double-click the file to open it in the Libero SoC Text Editor.Table 2-1 • BFM Files BFM File Name Function Remarks Test.bfm • Toplevel BFM • Contains the main function Libero-generated. Do not er.bfm• Contains user BFM commands • Calls subsystem_init function Edit this file to add user BFM commands. Subsystem.bfm • Contains subsystem memory map• Define name and base address of eachsubsystem resource• Call the init function to initialize subsystemDo not edit.Peripherals_init.bfm • Contains the Memory Map of all peripherals,including SERDES• Calls the SERDES_<0/1/2/3>_init.bfm toinitialize SERDESDo not edit.Figure 2-2 • Simulation BFM Files3 – BFM ExampleWriting and Verifying Fabric GPIO BitsIn the following example, two instances of CoreGPIO with 32 GPIO's per instance have been added intothe Fabric. Instance CoreGPIO_0 is mapped to address 0x40055000 and Instance CoreGPIO_1 ismapped to address 0x40057000. The subsystem.bfm is automatically generated by Libero SoC andcontains the memory map of the two CoreGPIO instances. CoreGPIO_0 and CoreGPIO_1 can bereferenced from within your user.bfm script.subsystem.bfm#===========================================================# Created by Microsemi SmartDesign## Syntax:# -------## memmap resource_name base_address;## write width resource_name byte_offset data;# read width resource_name byte_offset;# readcheck width resource_name byte_offset data;##===========================================================#-----------------------------------------------------------# Memory Map# Define name and base address of each resource.#-----------------------------------------------------------#Peripheral Base Addressesmemmap CoreGPIO_0 0x40055000;memmap CoreGPIO_1 0x40057000;The subsystem.bfm file is generated automatically every time you generate your MSS component; youdo not need to modify it.user.bfmTo add your own BFM commands, open the user.bfm file in the Libero SoC Text Editor.For example, in the user.bfm file below, a BFM write command is added to write the half word 0x5555 to the CoreGPIO_0 Output register. A BFM readcheck command is then added to read back from the Input Register and compared to the previously written data.To check the syntax of your BFM commands at the end of your edits, right-click and choose Check BFM file. Select the Log tab to view the result of the syntax check.#===========================================================# Enter your BFM commands in this file.#.# Syntax:# -------## memmap resource_name base_address;## write width resource_name byte_offset data;# read width resource_name byte_offset;# readcheck width resource_name byte_offset data;##===========================================================include "subsystem.bfm"procedure user_main;# perform subsystem initialization routinecall subsystem_init;# add your BFM commands below:# GPIO registers (byte wide)# Refer Table 3-1 of CoreGPIO_HB.pdf#Offsets from GPIO Base Addressconstant INREG0 0x90constant OUTREG0 0xA0print "Fabric GPIO Access Start";#Write halfword 0x5555 to CoreGPIO_0 Output Register write h CoreGPIO_0 OUTREG0 0x5555; wait 4;#Read halfword from CoreGPIO_0 Input Register and compare to previously written data #(0x5555)readcheck h CoreGPIO_0 INREG0 0x5555;wait 4;print "CoreGPIO_0 TEST ENDS";wait 4;print "CoreGPIO_1 TEST START";#Write word 0xFFFFFFFF halfword 0x5555 to CoreGPIO_1 Output register Registerwrite w CoreGPIO_1 OUTREG0 0xFFFFFFFF;wait 4;#Read word halfword 0xFFFFFFFF from CoreGPIO_1 Input Register and compare to previously #written data (0xFFFFFFFF )(0x5555)readcheck w CoreGPIO_1 INREG0 0xFFFFFFFF;wait 4;print "CoreGPIO_1 TEST ENDS";print "";returnBFM CompilerLibero SoC includes the BFM compiler, which converts the BFM script files into vector files (*.vec). Thevector files contain a sequence of 32-bit values, each represented by an 8-digit hexadecimal value.Libero SoC is configured to automatically execute the BFM compiler when you invoke ModelSim or othersupported third-party simulators from Libero SoC. Libero SoC then passes the BFM files to the Simulatorfor simulation (Figure3-1). The BFM compiler also verifies the syntax of the BFM file and displays theresult of the syntax check in the Log.Figure3-1 • BFM Compiler and SimulationA – Product SupportMicrosemi SoC Products Group backs its products with various support services, including CustomerService, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.This appendix contains information about contacting Microsemi SoC Products Group and using thesesupport services.Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades,update information, order status, and authorization.From North America, call 800.262.1060From the rest of the world, call 650.318.4460Fax, from anywhere in the world, 408.643.6913Customer Technical Support CenterMicrosemi SoC Products Group staffs its Customer Technical Support Center with highly skilledengineers who can help answer your hardware, software, and design questions about Microsemi SoCProducts. The Customer Technical Support Center spends a great deal of time creating applicationnotes, answers to common design cycle questions, documentation of known issues, and various FAQs.So, before you contact us, please visit our online resources. It is very likely we have already answeredyour questions.Technical SupportVisit the Customer Support website (/soc/support/search/default.aspx) for moreinformation and support. Many answers available on the searchable web resource include diagrams,illustrations, and links to other resources on the website.WebsiteYou can browse a variety of technical and non-technical information on the SoC home page, at/soc.Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center. The Technical Support Center can becontacted by email or through the Microsemi SoC Products Group website.EmailYou can communicate your technical questions to our email address and receive answers back by email,fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.We constantly monitor the email account throughout the day. When sending your request to us, pleasebe sure to include your full name, company name, and your contact information for efficient processing ofyour request.The technical support email address is **********************.5-02-00433-2/08.14© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at .Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo CA 92656 USAWithin the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996My CasesMicrosemi SoC Products Group customers may submit and track technical cases online by going to My Cases .Outside the U.S.Customers needing assistance outside the US time zones can either contact technical support via email (**********************) or contact a local sales office. Sales office listings can be found at /soc/company/contact/default.aspx.ITAR Technical SupportFor technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via ***************************. Alternatively, within My Cases , select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the I TAR web page.。
AXI总线介绍
主机 主机
保护类型。 写地址有效。 1 = 地址和控制信息有效 0 = 地址和控制信息无效
ห้องสมุดไป่ตู้
这个信号会一直保持，直到AWREADY变为高。
AWREADY 设备 写地址准备好。这个信号用来指明设备已经准备好接 受地址和控制信息了。 1 = 设备准备好 0 = 设备没准备好
11
AXI信号（3）
Write data channel :
30
Burst 方式
1、固定式突发读写是指地址是固定的，每一次传输的地址都不变。这样的突发式读写是 重复的对一个相同的位置进行存取。例如FIFO。 2、增值式突发读写是指每一次读写的地址都比上一次的地址增加一个固定的值。 包装式突发读写跟增值式突发读写类似。包装式突发读写的地址是包数据的低地址当到 达一个包边界。 3、包装式突发读写有两个限制： 1起始地址必须以传输的size对齐。 2突发式读写的长度必须是2、4、8或者16
信号 WID[3:0] WDATA[31:0] WSTRB[3:0] 源 主机 主机 主机 描述 写ID tag，WID的值必须与AWID的值匹配 写的数据。 写阀门。WSTRB[n]标示的区间为WDATA[(8*n)+7:(8*n)]
WLAST WVALID
主机 主机
写的最后一个数据。 写有效 1 = 写数据和阀门有效 0 = 写数据和阀门无效
WREADY
设备
写就绪。指明设备已经准备好接受数据了 1 = 设备就绪 0 = 设备未就绪
12
AXI信号（4）
Write response channel :
信号 BID[3:0] BRESP[1:0] 源 设备 设备 描述 响应ID ， 这个数值必须与AWID的数值匹配。 写响应。这个信号指明写事务的状态。可能有的响应：OKAY、 EXOKAY、SLVERR、DECERR。
第2章 AMBA协议规范
和PREADY都是高时，PSLVERR才认为是有效的。
24
AMBA APB协议规范
--AMBA APB错误响应
接收到一个错误的交易，可能改变外设的状态（这是由
外设指定的）。
当一个写交易接收到一个错误时，并不意味着外设内的寄存器
没有更新。 读交易接收到一个错误时，能返回无效的数据。
对于一个读错误，并不要求外设将数据总线驱动为0。
12
AMBA APB协议规范
--AMBA APB写传输
APB写传输包括两种类型：
无等待状态写传输 有等待状态写传输
13
AMBA APB写传输
--无等待写传输
一个基本的无等待状态的写传输
地址、写入数据、写入信号和选择信号都在时钟上升沿后改变。
14
AMBA APB写传输
--无等待写传输
T1：写传输开始于地址PADDR，写数据PWDATA，写信号
11
--AMBA APB规范
APB属于AMBA 3协议系列，它提供了一个低功耗的接口，
并降低了接口的复杂性。 APB接口用在低带宽和不需要高性能总线的外围设备上。 APB是非流水线结构，所有的信号仅与时钟上升沿相关，这 样就可以简化APB 外围设备的设计流程，每个传输至少消耗 两个周期。 APB可以与AMBA高级高性能总线和AMBA 高级可扩展接口 连接。
LOGO Xilinx大学计划课程
Xilinx All Programmable Zynq-7000 SoC 设计指南
主 讲：何宾 Email：hebin@
AMBA协议规范
AMBA协议是ARM公司制定的用于SOC内IP互联的规范 主要内容
AMBA规范概述、AMBA APB规范、AMBA AHB规范和 AMBA AXI4规范。本章除了详细介绍APB和AHB规范外，还详细
AHB及APB总线介绍
AHB TIC state
AHB TIC state
AHB control vector
Example for AHB test
Entering test mode
Example for AHB test
Write test vectors
Example for AHB test
Read test vectors
Test Interface Controller (TIC)
Test Interface Controller (TIC)
In test mode the internal bus clock is driven from the external TCLK source. TIC has limited capabilities for burst transfers and can only perform undefined-length incrementing bursts TIC can be used for diagnostic test during system operation as well as production testing.
Every transfer consists of
An address and control cycle One or more cycles for the data
Slaver can extend the data using HREADY signal.
Overview of AHB operation
ambaahbagendaahb?overviewoftheambabus?aboutambaahb?ahbinterconnection?overviewofahboperation?basictransfer?transfertype?burstoperation?controlsignals?addressdecoding?slavetransferresponses?arbitration?splittransfersaboutambaahbaboutambaahbslaveaboutambaahbmasteraboutambaahbdecoderahbinterconnectionaboutambaahboverviewofahboperation?busmastermustbegrantedaccesstothebus
AHB总线总结 ppt课件
is not ready, then hready=0; but if master is not ready, how to do?
17
17
传输类型
HTRANS[1:0]：传输类型
四种类型：IDLE、BUSY、NONSEQ、SEQ
00：IDLE
主设备占用总线，但没进行传输 两次burst传输中间主设备可发IDLE
PPT课件
3
3
一个典型的AMBA系统
处理器和其它主设备/从设备都是可以替换的
PPT课件
4
4
AHB
高速总线，高性能 流水线操作
可支持多个总线主设备（最多16个）
支持burst传输 总线带宽：8、16、32、64、128bits 上升沿触发操作
PPT课件
5
5
Topic 2
What constitutes the AHB ?
47
47
仲裁举例（1）
没有等待状态的grant
PPT课件
48
48
仲裁举例（2）
有等待状态的grant
PPT课件
49
49
仲裁举例（3）
Burst传输之后移交总线
PPT课件
50
50
总线主设备Grant信号
PPT课件
51
51
几点说明
对于固定长度的burst传输，不必持续请求总线
对于未定义长度的 burst 传输，主设备应该持续送 出request信号，直到开始最后一次传输。
PPT课件
42
42
Topic 5
SWD协议学习
SWD协议学习ARM调试原理【调试接⼝框图】【SWD时序】【SWD主机】调试接⼝框图ARM-M0《ARM Cortex-M0.pdf》⼿册上提到的调试框图如下：《debug_interface_v6_0_architecture_specification_IHI0074A.pd》提到的调试框图如下：由此可知DAP中分为了AP和DP再看m3内核框图：从这⾥可以看到AP是在芯⽚中的，⽽SWDP是在外⾯的（SWD仿真器）。
SWD时序关于⼀些中国⽹友的解释请看：https:///baiyibin0530/article/details/51682179内容摘录如下：以下我的模拟SWD接⼝的板⼦简称为Host,⽬标MCU(即我要连接的板⼦)简称为Target。
SWD协议故名思议，串⾏总线调试接⼝。
我们需要3根线与⽬标MCU相连，SWDIO,SWDCLK和GND。
-SWDIO 为双向Data⼝，主机到⽬标的数据传送。
-SWDCLK 为时钟⼝，主机驱动。
-GND GND脚。
⾸先参考《ARM Debug Interface V5》(注：该⽂档已有更新版本，并且对V5版本做了勘误)，对⼀些相关的协议相关说明有了较浅的认识。
那接下来便找了个带SWD接⼝的板⼦，我这⾸先选了STM32F030，因为以后可以为⽣产线做离线编程器，当然随后也出现了⼀些问题，下⽂会说明。
连上相关物理连线，开始折腾。
看⼿册中有⼏个相对较重要的时序说明。
Trn-Trn：即Line turn-round，当总线上的数据传输⽅向发送改变时（⽐如由Host->Target变为Target->Host），需要插⼊Trn，Trn为⼀个CLK时序，关于对于Trn的理解⾃⼰也有些疑问。
Idle cycles：在⼀个总线完成后，可以⽴即进⼊下⼀个总线操作或者是勒令总线进⼊Idle 状态，此时可以插⼊Idle cycle。
在这我⽤连续送出8个’0b0’来使得总线进⼊Idle状态。
AT91SAM7x256_128+参考手册(EMAC部分)
前 言Atmel公司去年八月(2005年)发布了最新的AT91SAM7X256/128芯片，该芯片实现了一个与IEEE 802.3标准兼容的以太网MAC，这引起了本人极大的兴趣。
为了能够让自己深入了解MAC模块的技术细节，同时提升自己的英文阅读及翻译水平，本人特意把该芯片携带的技术手册中对EMAC部分的介绍翻译成中文，为了方便中英文对照，文中仍然采用了英文版章节序号：第38节，与英文版一致。
38以太网MAC（EMAC）38．1 概览EMAC模块使用一个地址检查器，统计与控制寄存器组，接收与传输部件以及一个DMA 接口实现了一个与IEEE 802.3标准兼容的以太网MAC。
地址检查器识别四个特殊的48位地址，还包含一个匹配多播与单播地址的64位哈希（hash）寄存器。
它可以识别所有的广播地址，复制所有帧，还可以作用于一个外部地址匹配信号。
统计寄存器部件包含的寄存器组对传输接及收操作相关的不同的事件类型计数。
这些寄存器连同存储在接收缓冲区列表里的状态字一起，允许软件生成与IEEE 802.3兼容的网络管理统计表。
38．2 结构图图38-1 EMAC结构图38．3 功能描述图38-1显示了EMAC模块的不同部件。
控制寄存器组驱动MDIO（MDIO，数据输入/输出管理的简称，译注）接口，设置DMA行为，启动帧传输，选择像双工或半双工这样的操作模式。
接收部件检查前导字段的有效性，FCS（Frame Check Sequence，帧校验序列的简称，译注），对齐和长度，以及把接收到的帧交给地址检查部件和DMA接口。
传输部件从DMA接口取出数据，添加前导字段，并且，如果必要，填充数据（如果发送一个长度小于64个字节的数据包，MAC会生成填充字节将这个数据包扩展到64个字节的最小限制，译注）和FCS，然后按照CSMA/CD(carrier sense multiple access with collision detect，载波监听多路访问/冲突检测，译注)协议传输数据。
AMBA3apb
AMBA™ 3 APB Protocolv1.0Specification Copyright ©2003, 2004. ARM Limited. All rights reserved.ARM IHI 0024BAMBA 3 APB ProtocolSpecificationCopyright ©2003, 2004. ARM Limited. All rights reserved.Release InformationChange historyDate Issue Change25 September 2003A First release for v1.017 August 2004B Second release for v1.0Proprietary NoticeWords and logos marked with® or™ are registered trademarks or trademarks of ARM Limited in the EU andother countries, except as otherwise stated below in this proprietary notice. Other brands and namesmentioned herein may be the trademarks of their respective owners.Neither the whole nor any part of the information contained in, or the product described in, this documentmay be adapted or reproduced in any material form except with the prior written permission of the copyrightholder.The product described in this document is subject to continuous developments and improvements. Allparticulars of the product and its use contained in this document are given by ARM Limited in good faith.However, all warranties implied or expressed, including but not limited to implied warranties ofmerchantability, or fitness for purpose, are excluded.This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liablefor any loss or damage arising from the use of any information in this document, or any error or omission insuch information, or any incorrect use of the product.AMBA Specification License1.Subject to the provisions of Clauses 2 and 3, ARM hereby grants to LICENSEE a perpetual, non-exclusive,nontransferable, royalty free, worldwide licence to use and copy the AMBA Specification for the purpose ofdeveloping, having developed, manufacturing, having manufactured, offering to sell, selling, supplying orotherwise distributing products which comply with the AMBA Specification.2.THE AMBA SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES EXPRESS, IMPLIEDOR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORYQUALITY, MERCHANTABILITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULARPURPOSE.3. No licence, express, implied or otherwise, is granted to LICENSEE, under the provisions of Clause 1, touse the ARM tradename, or AMBA trademark in connection with the AMBA Specification or any productsbased thereon. Nothing in Clause 1 shall be construed as authority for LICENSEE to make anyrepresentations on behalf of ARM in respect of the AMBA Specification.ii Copyright ©2003, 2004. ARM Limited. All rights reserved.ARM IHI 0024BConfidentiality StatusThis document is Open Access. This document has no restriction on distribution.Product StatusThe information in this document is final, that is for a developed product.Web AddressARM IHI 0024B Copyright ©2003, 2004. ARM Limited. All rights reserved.iiiiv Copyright ©2003, 2004. ARM Limited. All rights reserved.ARM IHI 0024BContentsAMBA 3 APB Protocol SpecificationPrefaceAbout this specification (x)Feedb ack (xiii)Chapter1Introduction1.1About the AMBA 3 APB .............................................................................. 1-21.2Changes for AMBA 3 APB Protocol Specification v1.0 ............................... 1-3Chapter2Transfers2.1Write transfers ............................................................................................. 2-22.2Read transfers ............................................................................................ 2-42.3Error response ............................................................................................ 2-6Chapter3Operating States3.1Operating states .......................................................................................... 3-2Chapter4Signal Descriptions4.1AMBA 3 APB signals .................................................................................. 4-2 ARM IHI 0024B Copyright ©2003, 2004. ARM Limited. All rights reserved.vContentsvi Copyright ©2003, 2004. ARM Limited. All rights reserved.ARM IHI 0024BList of FiguresAMBA 3 APB Protocol SpecificationKey to timing diagram conventions (xi)Figure2-1Write transfer with no wait states .............................................................................. 2-2 Figure2-2Write transfer with wait states ................................................................................... 2-3 Figure2-3Read transfer with no wait states .............................................................................. 2-4 Figure2-4Read transfer with wait states ................................................................................... 2-5 Figure2-5Example failing write transfer .................................................................................... 2-6 Figure2-6Example failing read transfer .................................................................................... 2-7 Figure3-1State diagram ............................................................................................................ 3-2 ARM IHI 0024B Copyright ©2003, 2004. ARM Limited. All rights reserved.viiList of Figuresviii Copyright ©2003, 2004. ARM Limited. All rights reserved.ARM IHI 0024BPrefaceThis preface introduces the Advanced Microcontroller Bus Architecture (AMBA) 3Advanced Peripheral Bus (APB) protocol specification. It contains the followingsections:•About this specification on page x•Feedback on page xiii.ARM IHI 0024B Copyright ©2003, 2004. ARM Limited. All rights reserved.ixPrefaceAbout this specificationThis is the specification for the AMBA 3 APB protocol. All references to APB in thismanual refer to AMBA 3 (not AMBA 2 or earlier versions).Intended audienceThis specification is written to help hardware and software engineers to design systemsand modules that are compatible with the APB protocol.Using this specificationThis specification is organized into the following chapters:Chapter1 IntroductionRead this chapter for an overview of the APB protocol.Chapter2 TransfersRead this chapter for information about the different types of APBtransfer.Chapter3 Operating StatesRead this chapter for descriptions of the APB operating states.Chapter4 Signal DescriptionsRead this chapter for descriptions of the APB signals.ConventionsThis section describes the conventions that this specification uses:•Typographical•Timing diagrams on page xi•Signals on page xii.TypographicalThis specification uses the following typographical conventions:italic Highlights important notes, introduces special terminology,denotes internal cross-references, and citations.bold Highlights interface elements, such as menu names. DenotesARM processor signal names. Also used for terms in descriptivelists, where appropriate.x Copyright ©2003, 2004. ARM Limited. All rights reserved.ARM IHI 0024BPreface monospace Denotes text that you can enter at the keyboard, such ascommands, file and program names, and source code. monospace Denotes a permitted abbreviation for a command or option. Youcan enter the underlined text instead of the full command or optionname.monospace italic Denotes arguments to monospace text where the argument is to bereplaced by a specific value.monospace bold denotes language keywords when used outside example code.< and > Angle brackets enclose replaceable terms for assembler syntaxwhere they appear in code or code fragments. They appear innormal font in running text. For example:•MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>•The Opcode_2 value selects which register is accessed. Timing diagramsThe figure named Key to timing diagram conventions explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.Key to timing diagram conventionsPrefaceSignalsThe signal conventions are:Signal level The level of an asserted signal depends on whether the signal isactive-HIGH or active-LOW. Asserted means HIGH foractive-HIGH signals and LOW for active-LOW signals.Prefix P Denotes AMBA 3 APB signals.Suffix n Denotes AXI, AHB, and AMBA 3 APB reset signals.Further readingThis section lists publications that provide additional information about the AMBA 3protocol family.ARM periodically provides updates and corrections to its documentation. See for current errata sheets, addenda, and the Frequently AskedQuestions list.This document contains information that is specific to the APB interface. See thefollowing documents for other relevant information:•AMBA AXI Protocol Specification (ARM IHI0022).PrefaceFeedbackARM Limited welcomes feedback on the APB protocol and its documentation.Feedback on the productIf you have any comments or suggestions about this product, contact your suppliergiving:•the product name• a concise explanation of your comments.Feedback on this specificationIf you have any comments on this specification, send email to errata@ giving:•the title•the number•the relevant page number(s) to which your comments apply• a concise explanation of your comments.ARM Limited also welcomes general suggestions for additions and improvements.PrefaceChapter1IntroductionThis chapter provides an overview of the AMBA 3 APB. It contains the followingsection:•About the AMBA 3 APB on page1-2•Changes for AMBA 3 APB Protocol Specification v1.0 on page1-3.Introduction 1.1About the AMBA 3 APBThe APB is part of the AMBA 3 protocol family. It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity.The APB interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipelined bus interface. The APB has unpipelined protocol.All signal transitions are only related to the rising edge of the clock to enable theintegration of APB peripherals easily into any design flow. Every transfer takes at least two cycles.The APB can interface with the AMBA Advanced High-performance Bus Lite(AHB-Lite) and AMBA Advanced Extensible Interface (AXI). You can use it to provide access to the programmable control registers of peripheral devices.本页已使用福昕阅读器进行编辑。
BUSBAR SYSTEM
专利名称：BUSBAR SYSTEM发明人：BIERMEIER, EBERHARD,OUSMANE, MOUHAMADOU,WAGENER, HANS 申请号：EP96907335.0申请日：19960301公开号：EP0818073A1公开日：19980114专利内容由知识产权出版社提供摘要：The invention relates to a busbar system with busbars which are fitted in a trough-like lower securing section extending over their length, have a clamping arm perpendicular to the securing surface of the lower securing section on which the adapters fitted with terminals can be fitted and covered, in which the adapters can be secured to the lower securing section by mechanical catches. The invention improves the mechanical securing of covers and adapters in that the lower securing section has an outer and an inner wall longitudinally on both sides forming a longitudinal catch recess, the outer walls also have an outwardly directed longitudinal catch web, retaining springs with catch webs of the side walls of the cover and adapter housing running parallel to the busbars can be engaged in the longitudinal catch apertures and additional components securable to the adapter housing can engage with retaining springs on the outwardly directed longitudinal catch webs of the outer walls of the lower securing section as a tipping guard.申请人：RITTAL-WERK RUDOLF LOH GMBH & CO. KG地址：Auf dem Stützelberg 35745 Herborn DE国籍：DE代理机构：Fleck, Hermann-Josef, Dr.-Ing.更多信息请下载全文后查看。
AMBA总线介绍
第十页，共97页。
AHB组成(zǔ chénɡ)局部
AHB 主设备〔master〕 初始化一次读/写操作(cāozuò) 某一时辰只允许一个主设备运用总线 uP、DMA、DSP、LCDC … AHB从设备〔slave〕 照应一次读/写操作(cāozuò) 经过地址映射来选择运用哪一个从设备 外部存储器控制器EMI、APB bridge、UART、 … AHB仲裁器〔arbiter〕 允许某一个主设备控制总线 在AMBA协议中没有定义仲裁算法 AHB译码器〔decoder〕 经过地址译码来决议选择哪一个从设备
C Data
基本(jīběn)AHB传输〔续〕
Burst Transfer
A
A
A+4
A+4
A+8
A+8
A+12
A+12
During burst
Slave has know that master need 4 data, A/A+4/Atr+an8s/fAer,+if1s2lave not
ready, then
一次无需等候(děnghòu)形状的复杂传输
If slave hasn’t ready to receive data, how to do?
Master release aSddlarveessaamnpdlecothnetroaMdladsrtesr saamnpdlecothnetrodlata
Slave 1
(External)
Decoder
logic
case HADDR is when …. =>
HSELebi <= ‘1’; when …. =>
IEEE 30-BUS SYSTEM
CASE1: IEEE 30-BUS SYSTEMThe IEEE 30-bus system has 6 generator buses, 24 load buses and 41 transmission lines of which four branches are with the tap setting transformers. The real power settings are taken from [1]. The lower voltage magnitude limits at all buses are 0.95 p.u. and the upper limits are 1.1 for all the PV buses and 1.05 p.u. for all the PQ buses and the reference bus. The lower and upper limits of the transformer tappings are 0.9 and 1.1 p.u. respectively. The capacitor bank rating is set as 0-20 MVAR. The optimal settings of GA control parameters are given below:Maximum generation : 60Population size : 30Crossover Probability (P c) : 0.7Mutation Probability (P m) : 0.01Minimization of Real Power Loss (P loss)The proposed algorithm is applied for loss minimization in the base condition i) without considering FACTS devices, ii) with the inclusion of FACTS devices. Without FACTS devices, the algorithmreaches a minimum loss of 4.58MW. Fig 2 shows the power losses at different generation levels.The optimal values of the control variables obtained are given in the second column of Table 1 and it was found that all the state variables corresponding to these control variables satisfy their limits. The loss obtained is less than the value reported in [1, 2] for the same real power settings. The location of TCSC was found out using Genetic Algorithm. Initially, TCSC placed in minimum number of locations does not reduces the loss significantly. The placement of TCSC in five lines gives the optimum loss as 4.45 MW.Table 1.Optimalcontrol variables for IEEE 30-BusFig 2. Loss versus Generation curve for RPD problemCASE 2: IEEE 118-BUS SYSTEMThe IEEE 118-bus system has 54 generator buses, 64 load buses and 186 transmission lines of which nine branches are with the tap setting transformers. Minimization of real power loss is taken as the objective function.The algorithm reaches a minimum loss of 139.16MW. The placement of TCSC in five lines gives the optimum loss as 137.5 MW. The optimal values of the control variables obtained are given in Table 2Table 2. Optimal control variables for IEEE 118-Bus System。
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Introduction to AMBA Bus System工研院 / 系統晶片技術㆗心工程師吳欣龍1. 前言本篇文章主要是介紹ARM Limited.公司所推出的AMBA 協定(Advanced Micro-controller Bus Architecture)。
AMBA協定目前是open 且free的，讀者可從ARM的網站()㆘載完整的Specification。
這篇文章並沒有打算說明完整的AMBA協定內容，詳細的Spec.還是請讀者閱讀ARM所提供的文件。
原本的AMBA協定包含了㆕大部分: AHB, ASB, APB, Test Methodology，限於篇幅的關係，我們挑選較重要的AHB, APB加以基本的介紹，並探討AHB的㆒些重要的特性。
2. AMBA 概述AMBA協定的目㆞是為了要推出on-chip bus的規範，㆒開始AMBA 1.0只有ASB與APB，為了節省面積，所以這時候的bus協定都是tristate的bus，而到後來2.0的AHB為了能更方便設計者(trisate bus要花更多精力去注意timing)，因此改用bus改用multiplexor的架構，並增加了新的特性。
㆒個以AMBA架構的SOC，㆒般來說包含了 high-performance的system bus - AHB與low-power的peripheral bus - APB。
System bus是負責連接例如ARM之類的embedded processor與DMA controller，on-chip memory 和其他 interface，或其他需要high bandwidth 的元件。
而peripheral bus則是用來連接系統的周邊元件，其protocol相對AHB來講較為簡單，與AHB之間則透過Bridge相連，期望能減少system bus的loading。
㆒個典型的AMBA架構如圖2.1：圖2.13. AHB簡介ARM當初訂定AHB (Advanced High-Performance Bus)主要是想讓它能夠用來當作SOC的z single-clock edge operationz non-tristate implementationz burst transfersz split transactionz multiple bus master以㆘我們將簡單的介紹AHB 的協定及這些特性。
3.1 OverviewAHB System 是由Master ，Slave ，Infrastructure ㆔部分所組成。
整個AHB bus ㆖的傳輸(transfer)都是由master 所發出，由slave 負責回應。
而infrastructure 則由arbiter ，master to slave multiplexor ，slave to master multiplexor ，decoder ，dummy slave ，dummy master 所組成。
AHB 之所以會需要arbiter ，是因為它支援multiple master ，因此需要arbiter 來仲裁。
而decoder 則是負責位址的解碼，從multiple slave ㆗選擇要回應transfer 的slave 。
而兩個multiplexor 則是負責bus 的routing(為了不使用tristate bus)，將bus ㆖的訊號在master 和slave ㆗傳送，圖3.1說明了multiplexor 與master/slave 連結的情形。
Slave to Master Multiplexor Master to Slaver Multiplexor圖 3.1基本㆖bus ㆖傳輸的訊號，可以分成clock ，arbitration ，address ，control signal ，write data ，read data ，response signal 七種。
除了clock 與arbitration 訊號之外，其餘的訊號皆會經過multiplexor 。
會經過master to slave multiplexor 的訊號有address, control signal, write data ，而會經過slave to master multiplexor 的則有read data 與response signal 。
㆘面的table 列出所有的AHB 訊號，以及它的用途。
我們將在後面的章節介紹這些訊號，讀者可以先瀏覽㆒遍，有個基本的印象。
NameSource Description HCLKClock source Bus Clock 。
All signal timings are related to the rising edge of HCLK 。
HRESETnReset controller active LOW 。
reset whole system 。
在看過了AHB的訊號後，㆘圖3.2則介紹AHB大概的bus interconnection。
在圖3.2㆗，省略的部分有 (1)各種control signal (HBURST, HTRANS等)的連接，其實他們的連線與HADDR㆒致。
(2)Master與Arbiter之間的Request/Grant訊號。
(3)Decoder與各個Slave間會有Selection的訊號。
(4)control mux的output會有部分control訊號除了接到Slave外也會接到Arbiter (HTRANS/HBURST)。
(5)Response signal(HREADY, HRESP)的mux。
另外Arbiter 會輸出HMASTER訊號，這個訊號會接到master-to-slave multiplexor，以作為selection signal。
圖3.23.2 Basic transfer在AHB bus㆖，㆒次完整的transfer可以分成兩個phase：address phase與data phase。
address㆘圖3.3說明AHB㆖的basic transfer。
圖 3.3transfer在data phase時若無法在1個clock cycle內完成，slave可用HREADY訊號去延長(extend) transfer。
請參考㆘圖3.4，當HREADY為LOW時，表示transfer尚未結束，為HIGH 時，則代表目前的transfer結束了，但結束時的status則需看Slave回應的HRESP訊號(可能是OKAY, ERROR等)。
圖 3.4由於㆒次transfer需要兩個phase才能完成，為了增進bus的performance，AHB將multiple transfer給pipeline起來，transfer間的address phase和data phase是overlap在㆒起的，請見㆘圖3.5。
從圖3.5㆗我們可以看到由於現在目前transfer的data phase與㆘㆒次transfer的address phase是overlap的，所以當目前transfer的data phase被extend時，address phase也得跟著延長。
圖 3.53.3 Control signalAHB㆖的Control signal 共有五類，分別為z HTRANS[1:0] ：Transfer Typez HBURST[2:0] : Burst Typez HPROT[3:0] : Protection Controlz HSIZE[2:0] : Transfer Sizez HWRITE :Transfer Direction底㆘我們將㆒㆒介紹。
3.3.1 Transfer TypeAHB㆖共有㆕種transfer type：z IDLE：指示slave需忽略目前的transfer。
用於當master沒有資料需要傳送時，而此時slave 需在transfer的data phase回應zero wait cycle的OKAY response。
z BUSY : 在burst transfer時，master傳送連續的transfer給slave，若master因某些原因無法及時將資料準備好，則發出使用此 transfer type通知slave，slave的response應該與回應IDLE transfer時相同，也就是zero wait cycle的OKAY response。
z NONSEQ (Non-sequential) :指示目前transfer的address和control訊號與㆖㆒筆transfer 無關。
z SEQ (Sequential)):指示address和㆖㆒筆transfer相關，而control訊號則和㆖㆒筆transfer 相同，通常用在burst transfer㆗。
㆘圖3.6為transfer type的example。
從時序圖裡我們可以看出：第㆒筆burst transfer的type ㆒定為NONSEQ，另外因為master無法把㆘㆒筆資料在第㆓個cycle準備好，因此使用BUSY type去延遲第㆓筆transfer。
圖 3.63.3.2 Burst TypeBurst type是用來讓AHB master發出address彼此相關的連續transfer(control訊號需相同)。
AHB支援八種的burst type，用來指示burst的長度(transfer的個數，在AHB Spec.㆗使用beat 這個英文字)，與address間的關係。
請見表3.1。
其㆗incrementing的burst，每㆒筆的transfer address必定是前㆒筆transfer的address加㆖transfer size。
而wrapping burst則將memory切割成了(transfer size X transfer beat)大小的㆒個個memory boundary，當transfer address要跨越boundary時，㆘㆒筆transfer address會繞回boundary起點。
舉例來說，現在我們要傳送4筆wrapping burst，transfer size為word (4 byte)，第㆒筆transfer的address為0x34，此時(4 byte x 4 transfer)則transfer會在16-byte boundary繞回，所以4筆transfer的address分別是0x34, 0x38, 0x3C, 0x30。