Integrated Finite State Machine and RF Timing Modules for VMEbus and VXIbus Instrumentation

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计算机常见英文缩写

计算机常见英文缩写Virtue carries wealth. On the morning of November 2, 2022计算机常用英文缩写3DPA—3D Positional Audio—3D定位音频3DS—Three Dimension Studio—三维摄影室AAT—Average Access Time—平均存取时间ABS—Auto Balance System—自动平衡系统AC—Alternating Current—交流电ACOPS—Automatic CPU Overheat Prevention System—自动CPU过热预防系统ACPI—Advanced Configuration And Power Interface—高级配置与电源接口ADC—Analog To Digital Convent—模数转换器ADIMM—Advanced Dual In-line Memory Modules—高级双重内嵌式内存模块ADO—ActiveX Data Object—ActiveX数据对象ADSL—Asymmetric Digital Subscriber Line—非对称数字用户路线AE—Atmospheric Effect—雾化效果AGP—Accelerated Graphics Port—加速图形接口AGU—Address Generation Unit—地址产生单元AHA—Accelerated Hub Architecture—加速中心架构AH—Authentication Header—鉴定头文件AI—Artificial Intelligence—人工智能AL—Artificial Life—人工生命ALU—Arithmetic Logic Unit—算术逻辑单元ANSI—American National Standard Institute—美国国家标准协会AOL—American Online—美国在线APIC—Advanced Programmable Interrupt Controller—高级程序中断控制器APM—Advanced Power Management—高级电源管理APP—Accelerated Parallel Processing—AMD加速并行处理技术APPE—Advanced Packet Parsing Engine—高级数据包解析引擎ARP—Address Resolution Protocol—地址解析协议ASC—Anti Static Coating—防静电涂层ASCII—American Standard Code For Information Interchange—美国信息交换标准代码ASIC—Application Specific Integrated Circuit—特殊应用集成电路AST—Average Seek Time—平均寻道时间ATAPI—Advanced Technology Attachment Packet Interface—高级技术附加数据包接口ATL—ActiveX Template Library—ActiveX模版库ATM—Asynchronous Transfer Mode—异步传输模式AV—Analog Video—模拟视频AVI—Audio Video Interleave—音频视频插入B2C—Business To Custom—商家对客户BASIC—Beginner—All-Purpose Symbolic Instruction Code—初学者通用符号指令代码BBS—Bulletin Board System—公告牌系统BCF—Boot Catalog File—启动目录文件BGA—Ball Grid Array—球栅阵列BIF—Boot Image File—启动映像文件BIOS—Basic Input Output System—基本输入输出系统BIS—Boot Integrity Service—启动整体服务BMS—Black Matrix Screen—超黑矩阵屏幕BOPS—Billion Operation Per Second—十亿次计算每秒BPT—Branch Prediction Table—分支预测表BTB—Branch Target Buffer—分支目标缓冲CAD—Computer Aided Design—计算机辅助设计CAE—Computer Aided Engineering—计算机辅助工程CAI—Computer Aided Instruction—计算机辅助教学CAM—Common Access Mode—公共存取模型CAM—Computer Aided Manufacturing—计算机辅助制造CBIC—Cell based Integrated Circuit—基于单元的集成电路CC—Companion Chip—同伴芯片CCD—Charge Coupled Dvice—电流连接设备CCM—Call Control Management—拨号控制管理CC-NUMA—Cache Coherent Non Uniform Memory Access—连贯缓冲非统一内存寻址CCT—Clock Cycle Time—时钟周期CDMA—Code Division Multiple Access—码分多址CDR—Compact Disc Recordable—可刻录光盘CD-ROM—Compact Disc Read Only Memory—光驱CD-RW—Compact Disc Rewriter—刻录机CDSL—Consumer Digital Subscriber Line—消费者数字订阅线路CE—Consumer Electronic—消费电子CEM—Cube Environment Mapping—立方环境映射CEO—Chief Executive Officer—首席执行官CG—Computer Graphic—计算机生成图像CGI—Common Gateway Interface—通用网关界面CHRP—Common Hardware Reference Platform—公用硬件平台CIEA—Commercial Internet Exchange Association—商业英特网交易协会CIR—Committed Information Rate—约定信息速率CISC—Complex Instruction Set Computing—复杂指令集计算机CLV—Constant Linear Velocity—恒定线速度CMOS—Complementary Metal Oxide Semiconductor—互补金属氧化物半导体存储器COB—Cache On Board—板上集成缓存COD—Chip On Board—芯片内集成缓存COM—Component Object Model—组件对象模型COO—Chief Organization Officer—首席管理官CPGA—Ceramic Pin Grid Array—陶瓷针形栅格阵列CPLD—Complex Programmable Logic Device—复杂可编程逻辑器件CPS—Characters Per Second—每秒字符数CPU—Central Processing Unit—中央处理器CRC—Cyclical Redundancy Check—循环冗余检查CRM—Custom Relationship Management—客户关系管理CRT—cathode Ray Tube—阴极射线管CSE—Configuration Space Enable—可分配空间CSS—Cascading Style Sheets—层叠样式表CTO—Chief Technology Officer—首席技术官CTS—Carpal Tunnel Syndrome—腕管综合症CUDA—Computer Unified Device Architecture—计算机统一装置结构CVS—Computer Visual Syndrome—计算机视觉综合症DAC—Dual Address Cycle—双重地址周期DAE—Digital Audio Extraction—数字音频抓取DB—Deep Buffer—深度缓冲DCD—Dynamic Content Delivery—动态内容推送DC—Domain Controller—域控制器DCE—Data Communication Equipment—数据通信设备DCOM—Distributed Component Object Model—分布式组件对象模型DCT—Display Compression Technology—显示压缩技术DDC—Display Data Chanel—显示数据通道DDN—Digital Data Network—数字数据网DDR—Double Data Rate—双倍速率DDSS—Double Dynamic Suspension System—双层动力悬吊系统DEC—Direct Etching coating—表面蚀刻涂层DES—Data Encryption Standard—数据加密标准DFP—Dynamic Feedback Protocol—动态反馈协议DHCP—Dynamic Host Configuration Protocol—动态主机配置协议DIB—Dual Independent Bus—双独立总线DIC—Digital Image Controller—数字图像控制DIMM—Dual Inline Memory Module—双列直插内存模块DIP—Double In-line Package—双列直插式封装DIR—Direct Infrastructure rendering—基层直接渲染DLL—Dynamic Link Library—动态数据链接库DLP—Digital Light Process—数字光处理DME—Direct Memory Execute—直接内存执行DMI—Desktop Management Interface—桌面管理界面DMI—Dynamic Method Invocation—动态方法调用DNS—Digital Nervous System—数字神经系统DNS—Domain Name System—域名系统DOS—Disk Operating System—磁盘操作系统DP—Dual Processor—双处理器DPI—Dots Per Inch—每英寸点数DPMS—Display Power Management Signal—显示能源管理信号DQL—Dynamic Quadrapole Lens—动态四极镜DRC—Design Rule Check—设计规则检查DSD—Direct Stream Digital—直接比特流数字DSL—Digital Subscriber Line—数字用户专线DSP—Digital Signal Processing—数字信号处理DST—Drive Self Test—驱动自检程序DTD—Document Type Definition—文件类型定义DTE—Digital Terminal Equipment—数据终端设备DVD—Digital Versatile Disc—数字多功能光DVD—Digital Video Disc—数字视频光盘DVD-RAM—Digital Versatile Disc Random Access Memory—DVD随机存储器DVI—Digital Video Interface—数字视频接口E3—Electronic Entertainment Expo—美国E3大展EAX—Environment Audio Extension—环境音效扩展EB—Expansion Bus—扩展总线EBR—Excess Burst Rate—超频突发速率ECC—Elliptical Curve Crypto—椭圆曲线加密EC—Embedded Controller—嵌入式控制ECP—Extended Capabilities Port—扩展并行口ECTS—European Computer Trade Show—欧洲计算机商贸展示会EDIF—Electronic Design Interchange Format—电子设计交换格式EEPROM—Electrically Erasable Programmable Read Only Memory—电擦可编程只读存储器EFEAL—Extension Field Elliptically Aperture Lens—可扩展扫描椭圆孔镜头EIDE—Enhanced Integrated Driver Electronic—增强电子集成驱动器EISA—Enhanced Industry Standard Architecture—增强工业标准架构EMI—Electromagnetic Interference—电磁干扰EMP—Emergency Management Port—紧急事情管理端口EPP—Enhanced Parallel Port—增强并行口EPU—Energy Processing Unit—能耗调控单元ERC—Electronic Rule Check—电气规则检查ERP—Enterprise Resource Planning—企业资源计划ERP—Estimated Retail Place—估计零售价ESCD—Extended System Configuration Data—扩展系统配置数据FADD—Floating Addition—浮点加FAT—File Allocation Table—文件分配表FBC—Frame Buffer Cache—帧缓冲缓存FCPGA—Flip Chip Pin Grid Array—反转芯片针脚栅格阵列FDBM—Fluid Dynamic Bearing Motor—液态轴承马达FDC—Floppy Disk Controller—软盘控制装置FDD—Floppy Disk Drive—软盘FDIV—Floating Divided—浮点除FDM—Frequency Division Multiplexing—频分多路复用FIR—Finite Impulse Response—有限推进响应FMUL—Floating Multiplication—浮点乘FMV—Full Motion Video—全动态影像FPGA—Filed Programmable Grate Array—现场可编程门阵列FPS—First Person Shooting—第一人称射击FPU—Floating Processing Unit—浮点运算单元—Frames Per Second—每秒传输帧数FRICC—Federal Research Internet Coordinating Committee—联邦调查因特网协调委员会FSAA—Full Scene Anti—aliasing—全景抗锯齿FSE—Frequency Shifter Effect—频率转换效果FSM—Finite Status Machine—有限状态机FSUB—Floating Subtraction—浮点减FTP—File Transfer Protocol—文件传输协议FWH—Firmware Hub—固件中心GDI—Graphic Device Interface—图形设备接口GIF—Generalized Timing Formula—一般程序时间GMCH—Graphic Memory Control Hub—图形内存控制中心GMR—Giant Magneto Resistive—巨型磁阻GPF—Generation Protection Fault—一般保护性错误GPS—Global Positioning System—全球定位系统GPU—Graphic Processing Unit—图形处理器GSM—Global System For Mobile Communication—全球移动通讯系统GUI—Graphical User Interface—图形用户界面GVPP—Generic Visual Perception Processor—常规视觉处理器HAL—Hardware Abstraction Layer—硬件抽象化层HCI—Host Control Interface—主机控制接口HCT—Hardware Compatibility Test—硬件兼容性测试HDA—Head Disk Assembly—磁头集合HDCP—High-Bandwidth Digital Content Protection—高带宽数字内容保护HDD—Hard Disk Drive—硬盘HDL—Hardware Description Language—硬件描述语言HDMI—High Definition Multimedia Interface—高清晰度多媒体接口HDSL—High-Speed Digital Subscriber Line—高速率数字用户路线HDTV—High Definition TV—高清电视HEL—Hardware Emulation Layer—硬件模拟层HiFDA—High_Capacity Floppy Disk—高容量软盘HMOS—High Performance Metal Oxide Semiconductor—高性能金属氧化物半导体HPA—High Power Amplifier—高功率放大器HPS—High Performance Server—高性能服务器HPW—High Performance Workstation —高性能工作站HRIF—Head Related Transfer Function—头部关联传输功能HTML—Hyper Text Markup Language—超文本标志语言HTPC—Home Theater Personal Computer—家庭影院电脑HTTP—Hyper Text Transmission Protocol—超文本传输协议HUD—Head Up Display—平视显示器IA—Intel Architecture—英特尔架构ICD—Installable Client Drive—可安装客户端驱动程序ICMP—Intel Control Message Protocol—英特尔控制报文协议ICU—Instruction Control Unit—指令控制单元IDCT—Inverse Discrete Cosine Transfer—非连续反余弦变换IDF—Intel Developer Forum—因特尔开发者论坛IEEE—The Institute Electrical And Electronic Engineerings—美国电气和电子工程师协会IETF—Intel Engineer Task Force—因特网工程任务组IEU—Integer Excute Unit—整数执行单元IID—Interaural Intensity Difference—两侧声音强度差别IIR—Infinite Impulse Response—无限推进响应IIS—Internet Information Service—互联网信息服务IKE—Intel Key Exchange—因特网密钥交换协议IMM—Intel Mobil Module—因特尔移动模块IP—Internet Protocol—互联网协议IPPR—Image Processing And Pattern Recognition—图像处理和模式识别IPS—In Plane Switching—平面转换IRC—Internet Relay Chat—互联网接力聊天IRQ—Interrupt Request—中断请求IRST—Intel Rapid Storage Technology—英特尔快速存储技术ISA—Industry Standard Architecture—工业标准结构ISA—Instruction Set Architecture—指令集架构ISDN—Integrated Service Digital Network—综合服务数字网络IS—Internal Stake—内置堆栈ISO—International Standard Organization—国际标准化组织ISP—Intel Service Provider—因特网服务供应商JIT—Just In Time—准时制生产JVM—Java Virtual Machine—Java虚拟机KBC—Keyboard Controller—键盘控制器LBA—Logical Block Addressing—逻辑块寻址LCD—Liquid Crystal Display—液晶显示屏LCM—LCD Module—LCD显示模组LCOS—Liquid Crystal On Silicon—硅上液晶LDAP—Lightweight Directory Access Protocol—轻权目录访问协议LDT—Lighting Data Transport—闪电数据传输LED—Light Emitting Diode—发光二极管LF—Linear Filtering—线性过滤LMDS—Local Multipoint Distributed System—局域多点分布式系统LPM—Library Parameterized Module—参数化模块库LTE—Long Term Evolution—长期演进LVDS—Low Voltage Differential Single—低压差分信号LVS—Layout Versus Schematic—版图原理图对比MAC—Media Access Controller—介质访问控制MALS—Multi Astigmatism Lens System—多重散光聚焦系统MB—Motherboard—主机板MDC—Mobile Daughter Card—移动式子卡MFC—Microsoft Foundation Classes—微软基础库MFD—Multi Function Device—多功能设备MIDI—Musical Instrument Digital Interface—乐器数字接口MIME—Multipurpose Internet Mail Extension—多用途因特网邮件扩展协议MIOC—Memory And I/O Bridge Controller—内存和I/O桥控制器MiPad—Multimodal Interactive Notepad—多语态互动式记事本MIS—Management Information System—管理信息系统MMVF—Multi-Media Video File—多媒体视频文件MPEG—Moving Picture Expert Group—运动图像专家组MPP—Massive Parallel Processing—巨量平行处理MPS—Multi Processor Specification—多重处理器规范MRP—Manufacturing Resource Planning—制造资源计划MRW—Midrange Workstation—中型工作站MSI—Microsoft Installer—微软安装程序MS—Magnetic Sensor—磁场感应器MSN—Microsoft Network—微软网络MSP—Media Stream Processor—媒体流处理器MTBF—Mean Time Before Failure—平均故障时间MTH—Memory Transfer Hub—内存转换中心MUD—Multiple User Dungeon—多用户地牢NAOC—No-Account Overclock—无效超频NAS—Network Attached Storage—网络连接式存储NAT—Network Area Translation—网络地址转换NBC—North Bridge Chip—北桥芯片NDIS—Network Driver Interface specification—网络驱动接口规范NDS—Novell Directory Service—网威目录服务NE—Netlist Extract—网表提取NIC—Network Interface Card—网络接口卡NNTP—Network News Transport Protocol—网络新闻传输协议NPC—Non Player Character—非玩着人物NT—New Technology—新技术OCR—Optical Character Recognition—光学字符识别OEM—Original Equipment Manufacturer—原始设备制造商OLGA—Organic Land Grid Array—基板栅格阵列OOP—Object Oriented Programming—面向对象的程序设计OPT—Optimized Production Technology—优化生产技术OS—Operating System—操作系统PCAV—Part Constant Angular Velocity—部分恒定角速度PCB—Printed Circuit Board—印刷电路板PCI—Peripheral Component Interconnect—外围装置连接端口PC—Personal Computer—个人计算机PC—Perspective Correction—透视纠正PDA—Personal Digital Assistant—个人数字助理PDS—Public Directory Support—公众目录支持PE—Parameter Extract—参数提取PGC—Parallel Graphic Configuration—并行图像设置PIB—Processor In a Box—盒装处理器PIC—Programmable Interrupt Controller—可编程中断控制器PICS—Platform For Internet Content Selection—英特网内容选择平台PIM—Personal Information Management—个人信息管理系统PLCC—Plastic Leadless Chip Carrier—塑料无引脚芯片载体PLD—Programmable Logic Device—可编程逻辑器件PLL—Phase Locked Loop—锁相环PNP—Plug And Play—即插即用POF—Polymer Optical Fiber—聚合体光纤POST—Power On Self Test—开机自检PPM—Pages Per Minute—每分钟打印页数PPTP—Point To Point Tunneling Protocol—点对点通道协议PQFP—Plastic Quad Flat Package—塑料方型扁平式封装PRML—Partial Response Maximum Likelihood—最大可能部分反应PSK—Pre-Shared Key—预共享密钥PSN—Processor Serial Numbers—处理器序列号PSU—Power Supply Unit—计算机电源PSW—Program Status Word—程序状态字PXE—Per-boot Execution Environment—预启动运行环境QBM—Quad Band Memory—四倍边带内存QOS—Quality Of Service—服务质量QPA—Quad Port Acceleration—四倍接口加速RADSL—Rate Adaptive Digital Subscriber Line—速率自适应数字用户路线RAM—Random Access Memory—内存随机存储器RARP—Reverse Address Resolution Protocol—反相地址解析协议RDF—Resource Description Framework—资源描述框架RISC—Reduced Instruction Ser Computing—精简指令集计算机RMA—Real Media Architecture—实媒体架构RNG—Random Number Generator—随即数字发生器ROB—Reorder Buffer—重新排列缓存区RPG—Role Playing Game—角色扮演游戏RPM—Revolution Per Minute—每分钟转数RRVP—Resource Reser Vation Protocol—资源保留协议RSD—Removable Storage Device—移动式存储设备RSDS—Reduced Swing Differential Single—小幅度摆动差动信号RTC—Real Time Clock—实时时钟RTL—Register Transmit Level—寄存器传输级RTSP—Real Time Streaming Protocol—实时流协议RTS—Real Time Strategy—即时战略RTS—Request To Send—需求发送SAM—Sales Available Market—可发售市场SAP—Sideband Address Port—边带寻址端口SATA—Serial Advanced Technology Attachment—串行高级技术附件SBC—South Bridge Chip—南桥芯片SBFS—Sample Boot Flag Specification—简单引导标记规范SCSI—Small Computer System Interface—小型计算机系统接口SC—Static Core—静态内核SCT—Software Compatibility Test—软件兼容性测试SDK—Software Development Kit—软件开发工具包SDRAM—Synchronous Dynamic Random Access Memory—同步动态随机存储器SDTV—Standard Definition Television—标准清晰度电视SEC—Single Edge Connector—单边连接器SEM—Spherical Environment Mapping—球形环境映射SET—Secure Electronic Transaction—安全电子交易SGML—Standard Generalized Markup Language—标准通用标记语言SIMD—SIngle Instruction Multi Data—单指令多数据SIV—System Information Viewer—系统信息观察SLI—Scanline Interleave—扫描线间插SMART—Self-Monitoring Analysis And Reporting Technology—自动检测、分析和报告技术SMB—System Management Bus—系统管理总线SMD—Surface Mount Device—表面安装设备SMIL—Synchronous Multimedia Integrated Language—同步多媒体集成语言SMIP—Simple Mail Transfer Protocol—简单邮件传输协议SMI—System Management Interrupt—系统管理中断SMM—System Management Mode—系统管理模式SMP—Symmetric Multi-Processing—对称式多重处理器架构SNMP—Simple Network Management Protocol—简单网络管理协议SNR—Single To Noise Rate—信噪比SOAC—System ON A Chip—系统集成多功能芯片SOC—System On Chip—片上系统SOI—Silicon On Insulator—绝缘体硅片SOS—Server Operating Systems—服务器操作系统SPD—Serial Presense Detect—串行存在检查SPEC—System Performance Evaluation Check—系统性能评估测试SPS—Shock Protection System—震动保护系统SP—Stack Pointing—堆栈指针SQRC—Square Root Calculation—平方根计算SRA—Symmetric Rendering Architecture—对称渲染架构SRR—Segment Register Rewrite—区段寄存器重写SRS—Sound Retrieval System—声音修复系统SSB—Super South Bridge—超级南桥芯片SSD—Solid State Disk—固态硬盘SSE—Streaming SIMD Extensions—单一指令多数据流扩展SSI—Small Scall Integration—小规模集成STB—Set Top Boxes—电视顶置盒STD—Suspend To Disk—磁盘唤醒STR—Suspend To RAM—内存唤醒STS—Switched Internet working Service—交换式网络互联服务SUA—Single User Account—单用户账号SVR—Switching Voltage Regulator—交换式电压调节TCA—Twin Cache Architecture—双缓冲结构TCO—Total Cost Of Ownership—拥有总成本TCP—Transmission Control Protocol—传输控制协议TCP—Transmission Control Protocol—传输控制协议TDP—Thermal Design Power—散热设计功耗TFT—Thin Film Transistor—薄膜晶体管TLB—Translate Look Side Buffers—翻译旁视缓冲器TOP—The Olympic Partner—奥林匹克全球合作伙伴TPS—Transactions Per Second—每秒处理事项数TQM—Total Quality Management—全面质量管理UART—Universal Asynchronous Receive/Transmitter—通用异步收发器UCC—Ultra Clear Coating—超清晰涂层UDMA—Ultra Direct Memory Access—高级直接内存访问UDP—User Datagram protocol—用户数据报协议UDP—User Datagram Protocol—用户数据报协议ULS—User Location Service—用户定位服务UPA—Ultra Port Architecture—超级端口结构UPS—Uninterrupted Power Supply—不间断电源USB—Universal Serial Bus—通用串行总线USDM—Unified System Diagnostic Manager—统一系统检测管理USWC—Uncacheabled Speculative Write Combination—无缓冲随即联合写操作VALU—Vector Arithmetic Logic Unit—向量算术逻辑单元VBI—Vertical Blanking Interval—垂直空白间隙VCMA—Virtual Channel Memory Architecture—虚拟通道内存结构VDM—Windows Driver Model—视窗驱动程序模块VDSL—Very-high-bit-rate Digital Subscriber Loop—甚高速数字用户环路VDT—Video Display Terminal—视频显示终端VESA—Video Electronic Standard Association—视频电子标准协会VFAT—Virtual File Allocation Table—虚拟文件分配表VFM—Wired For Management—有线管理VGA—Video Graphics Array—视频图形阵列VID—Voltage Identification Definition—电压识别认证VIP—Video Interface Port—视频接口VLIW—Very Long Instruction Word—超长指令集VLSI—Very Large Scale Integrated—超大规模集成电路VOD—Video On Demand—视频点播VPN—Virtual Private Network—虚拟局域网VPU—Vector Permutate Unit—向量排列单元VQTC—Vector-Quantization Texture Compression—向量纹理单元VRE—Voltage Reduction Enhance—增强型电压调节VRML—Virtual Reality Makeup Language—虚拟现实结构化语言VRM—Voltage Regulator Module—电压调整模块VSA—Virtual System Architecture—虚拟系统架构VSIS—Video Single Standard—视频信号标准VXML—Voice Extensible Markup Language—语音扩展标记语言WAIS—Wide Area Information Service—广义信息服务器WAN—Web Area Network—广域网WG—Wave Guide—波导合成Wi—Fi—Wireless Fidelity—无线保真WLAN—Wireless Local Area Network—无线局域网络WMI—Wired For Management Initiative—主动式管理线路WOL—Wake On Lan—局域网唤醒WPAN—Wireless Personal Area Network—无线个域网WSH—Windows Scripting Host—视窗脚本程序—World Wide Web—万维网XSL—Extensible Style Sheet Language—可扩展设计语言ZAM—Zero Administration For Windows—零管理视窗系统ECL—Emitter Couple Logic—射极耦合逻辑CAM—Content Addressable Memory—内容寻址存储器MIPS—Million Instruction Per Second—每秒处理百万级指令。

android状态机(wifi statemachine)之无线状态机

mDriverLoaded State
mSupplicantSt artingState
mSupplicantSt artedState
①
②
CMD_LOAD_DRIVER
③
④
⑤ ⑥
mDriverStarte dState
CMD_START_SUPPLICANT
① ② ③ ④ ⑤ ⑥ ⑦
If(WifiNative.isDriverLoaded) transitionTo Case:CMD_LOAD_DRIVER transitionTo Case:WifiP2pService.WIFI_ENABLE_PROCEED(from P2pStateMachine) transitionTo Case: CMD_LOAD_DRIVER_SUCCESS(send by loadingstate) transitionTo Case: CMD_START_SUPPLICANT,If(WifiNative.startSupplicant) transitionTo Case: WifiMonitor.SUP_CONNECTION_EVENT, transitionTo if (mIsScanMode), transitionTo
A particular FSM is defined by a list of its states, and the triggering condition for each transition. Example: vending machines, elevators, traffic lights , and combination locks ,wifistatemachine. Note： hierarchy

常用集成电路名词缩写

PLCC Plastic Leaded Chip Carrier
PLE Physical Layout Estimator
PLI Programming Language Interface
PLL Phase Locked Loop
POP Process Oriented Programming
PPA Performance，Power，Area
APR Auto place and route
ARM Advanced RISC Machines
ASB ASCII ASIC
Advanced System Bus
American standard code for information interchange
Application Special Integrated Circuit
DVE Discovery Visualization Environment
DVFS Dynamic Voltage Frequency Scaling
DVR Design Rule Violation
DVT Design verification test
ECC Error Correcting Code
CTL Computation tree logic
CTS Clock Tree Synthesis
DAC Digital-to-Analog Converter
DC Design compiler
DCM Digital Clock Manager
DCT Discrete cosine transform
SEB Single Event Burnout
SEE Single Event Effect

Debussy 仿真快速上手教程

Debussy 仿真快速上手教程Debussy 介绍Debussy 是NOVAS Software, Inc(思源科技)发展的HDL Debug & Analysis tool，这套软体主要不是用来跑模拟或看波形，它最强大的功能是：能够在HDL source code、schematic diagram、waveform、state bubble diagram之间，即时做trace，协助工程师debug。

可能您会觉的：只要有simulator如ModelSim就可以做debug了，我何必再学这套软体呢? 其实Debussy v5.0以后的新版本，还提供了nLint -- check coding style & synthesizable，这蛮有用的，可以协助工程师了解如何写好coding style，并养成习惯。

下图所示为整个Debussy 的原理架构，可归纳几个结论：Debussy有四个主要单元(component)，nTrace、nWave、nSchema、nStatenTrace -- Hypertext source code analysis and browse tool (为%Debussy &所开启的主画面)nWave -- Waveform analysis tool (可由nTrace内开启，或直接%nWave &开启)nSchema -- Hierarchy schematic generatornState -- Finite State Machine Extraction and analysis toolDebussy本身不含模拟器(simulator)，必须呼叫外部模拟器(如Verilog-XL or ModelSim)产生FSDB file，其显示波形的单元"nWave"透过读取FSDB file，才能显示波形或讯号值的变化快速上手五部曲：(Debussy v.5.2)1. Import Files and generate FSDB file2. Trace between hierarchy browser and source code3. Trace between hierarchy browser、source code and schematic4. Trace between hierarchy browser、source code、schematic and waveform5. nLint(nState本文没介绍，有兴趣的读者，请依文后的连结，自行下载CIC所提供的NOVAS原厂编写教材参考)1. Import Files and generate FSDB file1-1 启动Debussy：% Debussy & (此处的D大小写都可以，但其它指令的大小写可能就有差别)开启nTrace window如下，此时工作目录下会新建一个"DebussyLog"目录1-2 Import Files：File \ Import Design...结果如下图所示：nTrace视窗中，含有三个区域，Hierarchical Brower、Source code window、Message window。

EDA名词解释

EDA名词解释ASIC:专用集成电路(Application Specific Integrated Circuit)AMPP:Altera宏功能模块和IP核开发伙伴组织(Altera Megafunction Partners Program)BGA:球状矩阵排列(ball grid array)BSDL:边界扫描描述语言(Boundary-Scan Description Language) BST:边界扫描测试(Boundary-Scan Testing)CAD:计算机辅助设计(Computer - Aided Design) CAE:计算机辅助工程(Computer Aided Engineering) CAM:计算机辅助制造(computer-aided manufacturing);中央地址存储器(Central AddressMemory)CAT:计算机辅助测试(computer-aided test)CPLD:复杂可编程逻辑器件(Complex Programable Logic Device) DFT:可测试设计(Design For Test)EAB:嵌入式阵列块(Embedded Array Block)EDA:电子设计自动化(Electronic Design Automation) EDIF:电子设计交换格式(electronic design interchange format) EEPROM:电可擦除可编程只读存储器(Electrically Erasable Programmable Read-OnlyMemory)EPROM:可擦除可编程ROM(Erasable Programmable Read-Only Memory) FPGA:现场可编程门阵列(Field Programmable Gata Array) EPLD:可擦除可编程逻辑器件(Erasable Programmable Logic Device) FPSLIC:现场可编程系统级集成电路(Field Programmable System Level Integration Circu) FSM:有限状态机(Finite State Machine)GAL:通用阵列逻辑(Generic Array Logic)HDL:硬件描述语言(hardware description language)IEEE:电子电气工程师协会(Institute of Electrical and Electronic Engineers) IP:知识产权核(Intellectual Property)ISP:在系统可编程(In System Programmability)JTAG:联合测试行动组(Joint Test Action Group);在EDA领域又称“边界扫描测试技术”，常用于可编程逻辑器件的测试下载LAB:逻辑阵列块(Logic Array Block)LE:逻辑单元(Logic Element)LPM:参数可设置模块库(Library of Parameterized Modules) LUT:查找表(lookup talbe)OLMC: 输出逻辑宏单元(Output Logic Macro Cell)OTP:一次性可编程(One Time Programmable)PAL:可编程阵列逻辑:(Programmable Array Logic)PCB:印刷电路板PGA:可编程门阵列(Programmable Gate Array)PIA:可编程连线阵(Programmable Interconnect Array) PLA:可编程逻辑阵列(Programmable Logic Array)PLD:可编程逻辑电路(Programable Logic Device)PROM:可编程序只读存储器(Programmable Read-Only Memory) ROM:只读内存(Read-Only Memory)SRAM:静态随机存储器(Static Random Access Memory)RTL:寄存器传输级(Register Transport Level) SOC:单芯片系统(System on a Chip) SOPC:片上可编程系统(System On Programmable Chip) UART:通用异步收发器(Universal Asynchronous Receiver,Transmitter)VHDL:超高速集成电路硬件描述语言(Very High Speed Integrated Circuits HardwareDescription Language)UES:用户电子标签(User Electronic Signature)ASIC:专用集成电路CPLD:复杂可编程逻辑器件EAB:嵌入式阵列块EDA:电子设计自动化FPGA:现场可编程门阵列GAL:通用阵列逻辑HDL:硬件描述语言IEEE:电子电气工程师协会IP:知识产权核JTAG:联合测试行动组LAB:逻辑阵列块LPM:参数可设置模块库LUT:查找表PLD:可编程逻辑器件RTL:寄存器传输级SOPC:可编程片上系统VHDL:超高速集成电路硬件描述语言。

FPGA名词概念

FPGA名词概念1、ASIC:application-specific integrated circuits专用集成电路是指应特定用户要求和特定电子系统的需要而设计、制造的集成电路。

ASIC分为全定制和半定制。

ASIC的特点是面向特定用户的需求，ASIC在批量生产时与通用集成电路相比具有体积更小、功耗更低、可靠性提高、性能提高、保密性增强、成本降低等优点。

全定制设计需要设计者完成所有电路的设计，因此需要大量人力物力，灵活性好但开发效率低下。

如果设计较为理想，全定制能够比半定制的ASIC芯片运行速度更快。

半定制使用库里的标准逻辑单元(Standard Cell)，设计时可以从标准逻辑单元库中选择SSI(门电路)、MSI(如加法器、比较器等)、数据通路(如ALU、存储器、总线等)、存储器甚至系统级模块(如乘法器、微控制器等)和IP核，这些逻辑单元已经布局完毕，而且设计得较为可靠，设计者可以较方便地完成系统设计。

2、ALU:arithmetic an logic unit算术逻辑单元是中央处理器(CPU)的执行单元，是所有中央处理器的核心组成部分，由“And Gate”（与门）和“Or Gate”（或门）构成的算术逻辑单元，主要功能是进行二位元的算术运算，如加减乘(不包括整数除法)。

基本上，在所有现代CPU体系结构中，二进制都以补码的形式来表示。

3、BCD:binary-coded decimal BCD码或二-十进制代码，亦称二进码十进数是一种二进制的数字编码形式，用二进制编码的十进制代码。

这种编码形式利用了四个位元来储存一个十进制的数码，使二进制和十进制之间的转换得以快捷的进行。

4、CLBs:configurable logic blocks可配置逻辑模块。

包含一个可配置开关矩阵，此矩阵有选型电路（多路复用器），触发器和4或6个输入组成。

在Xilinx公司的FPGA器件中，CLB由多个（一般为4个或2个）相同的slice和附加逻辑构成。

计算机组成与设计第五版答案

计算机组成与设计：《计算机组成与设计》是2010年机械工业出版社出版的图书，作者是帕特森(DavidA.Patterson）。

该书讲述的是采用了一个MIPS 处理器来展示计算机硬件技术、流水线、存储器的层次结构以及I/O 等基本功能。

此外，该书还包括一些关于x86架构的介绍。

内容简介：这本最畅销的计算机组成书籍经过全面更新，关注现今发生在计算机体系结构领域的革命性变革：从单处理器发展到多核微处理器。

此外，出版这本书的ARM版是为了强调嵌入式系统对于全亚洲计算行业的重要性，并采用ARM处理器来讨论实际计算机的指令集和算术运算。

因为ARM是用于嵌入式设备的最流行的指令集架构，而全世界每年约销售40亿个嵌入式设备。

采用ARMv6（ARM 11系列）为主要架构来展示指令系统和计算机算术运算的基本功能。

覆盖从串行计算到并行计算的革命性变革，新增了关于并行化的一章，并且每章中还有一些强调并行硬件和软件主题的小节。

新增一个由NVIDIA的首席科学家和架构主管撰写的附录，介绍了现代GPU的出现和重要性，首次详细描述了这个针对可视计算进行了优化的高度并行化、多线程、多核的处理器。

描述一种度量多核性能的独特方法——“Roofline model”，自带benchmark测试和分析AMD Opteron X4、Intel Xeo 5000、Sun Ultra SPARC T2和IBM Cell的性能。

涵盖了一些关于闪存和虚拟机的新内容。

提供了大量富有启发性的练习题，内容达200多页。

将AMD Opteron X4和Intel Nehalem作为贯穿《计算机组成与设计:硬件/软件接口(英文版·第4版·ARM版)》的实例。

用SPEC CPU2006组件更新了所有处理器性能实例。

图书目录：1 Computer Abstractions and Technology1.1 Introduction1.2 BelowYour Program1.3 Under the Covers1.4 Performance1.5 The Power Wall1.6 The Sea Change: The Switch from Uniprocessors to Multiprocessors1.7 Real Stuff: Manufacturing and Benchmarking the AMD Opteron X41.8 Fallacies and Pitfalls1.9 Concluding Remarks1.10 Historical Perspective and Further Reading1.11 Exercises2 Instructions: Language of the Computer2.1 Introduction2.2 Operations of the Computer Hardware2.3 Operands of the Computer Hardware2.4 Signed and Unsigned Numbers2.5 Representing Instructions in the Computer2.6 Logical Operations2.7 Instructions for Making Decisions2.8 Supporting Procedures in Computer Hardware2.9 Communicating with People2.10 ARM Addressing for 32-Bit Immediates and More Complex Addressing Modes2.11 Parallelism and Instructions: Synchronization2.12 Translating and Starting a Program2.13 A C Sort Example to Put lt AU Together2.14 Arrays versus Pointers2.15 Advanced Material: Compiling C and Interpreting Java2.16 Real Stuff." MIPS Instructions2.17 Real Stuff: x86 Instructions2.18 Fallacies and Pitfalls2.19 Conduding Remarks2.20 Historical Perspective and Further Reading2.21 Exercises3 Arithmetic for Computers3.1 Introduction3.2 Addition and Subtraction3.3 Multiplication3.4 Division3.5 Floating Point3.6 Parallelism and Computer Arithmetic: Associativity 3.7 Real Stuff: Floating Point in the x863.8 Fallacies and Pitfalls3.9 Concluding Remarks3.10 Historical Perspective and Further Reading3.11 Exercises4 The Processor4.1 Introduction4.2 Logic Design Conventions4.3 Building a Datapath4.4 A Simple Implementation Scheme4.5 An Overview of Pipelining4.6 Pipelined Datapath and Control4.7 Data Hazards: Forwarding versus Stalling4.8 Control Hazards4.9 Exceptions4.10 Parallelism and Advanced Instruction-Level Parallelism4.11 Real Stuff: theAMD OpteronX4 （Barcelona）Pipeline4.12 Advanced Topic: an Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipelineand More Pipelining Illustrations4.13 Fallacies and Pitfalls4.14 Concluding Remarks4.15 Historical Perspective and Further Reading4.16 Exercises5 Large and Fast: Exploiting Memory Hierarchy5.1 Introduction5.2 The Basics of Caches5.3 Measuring and Improving Cache Performance5.4 Virtual Memory5.5 A Common Framework for Memory Hierarchies5.6 Virtual Machines5.7 Using a Finite-State Machine to Control a Simple Cache5.8 Parallelism and Memory Hierarchies: Cache Coherence5.9 Advanced Material: Implementing Cache Controllers5.10 Real Stuff: the AMD Opteron X4 （Barcelona）and Intel NehalemMemory Hierarchies5.11 Fallacies and Pitfalls5.12 Concluding Remarks5.13 Historical Perspective and Further Reading5.14 Exercises6 Storage and Other I/0 Topics6.1 Introduction6.2 Dependability, Reliability, and Availability6.3 Disk Storage6.4 Flash Storage6.5 Connecting Processors, Memory, and I/O Devices6.6 Interfacing I/O Devices to the Processor, Memory, andOperating System6.7 I/O Performance Measures: Examples from Disk and File Systems6.8 Designing an I/O System6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks6.10 Real Stuff: Sun Fire x4150 Server6.11 Advanced Topics: Networks6.12 Fallacies and Pitfalls6.13 Concluding Remarks6.14 Historical Perspective and Further Reading6.15 Exercises7 Multicores, Multiprocessors, and Clusters7.1 Introduction7.2 The Difficulty of Creating Parallel Processing Programs7.3 Shared Memory Multiprocessors7.4 Clusters and Other Message-Passing Multiprocessors7.5 Hardware Multithreading 637.6 SISD,MIMD，SIMD，SPMD，and Vector7.7 Introduction to Graphics Processing Units7.8 Introduction to Multiprocessor Network Topologies7.9 Multiprocessor Benchmarks7.10 Roofline：A Simple Performance Model7.11 Real Stuff：Benchmarking Four Multicores Using theRooflineMudd7.12 Fallacies and Pitfalls7.13 Concluding Remarks7.14 Historical Perspective and Further Reading7.15 ExercisesInuexC D-ROM CONTENTA Graphics and Computing GPUSA.1 IntroductionA.2 GPU System ArchitecturesA.3 Scalable Parallelism-Programming GPUSA.4 Multithreaded Multiprocessor ArchitectureA.5 Paralld Memory System G.6 Floating PointA.6 Floating Point ArithmeticA.7 Real Stuff：The NVIDIA GeForce 8800A.8 Real Stuff：MappingApplications to GPUsA.9 Fallacies and PitflaUsA.10 Conduding RemarksA.1l HistoricalPerspectiveandFurtherReadingB1 ARM and Thumb Assembler InstructionsB1.1 Using This AppendixB1.2 SyntaxB1.3 Alphabetical List ofARM and Thumb Instructions B1.4 ARM Asembler Quick ReferenceB1.5 GNU Assembler Quick ReferenceB2 ARM and Thumb Instruction EncodingsB3 Intruction Cycle TimingsC The Basics of Logic DesignD Mapping Control to HardwareADVANCED CONTENTHISTORICAL PERSPECTIVES & FURTHER READINGTUTORIALSSOFTWARE作者简介：David A.Patterson，加州大学伯克利分校计算机科学系教授。

开题报告

开题报告毕业设计题目：基于IronPython的EFSM模型动态解释技术研究一、选题意义与可行性分析1.1选题意义扩展有限状态机EFSM模型具有较强的数据建模和行为建模能力，被广泛的作为通信协议的形式化建模技术[1-4]。

基于协议规范的EFSM模型进行协议实现的一致性测试是确保网络通信质量的重要手段。

协议EFSM模型动态行为的解释执行是基于EFSM模型进行一致性测试的关键技术之一。

此外，EFSM模型在诸多领域如模式识别、专家系统、机器理解、词法分析等领域都有着很广泛的应用。

IronPython是一个在.NET平台上的Python的实现，2010年微软发布了C#4.0,最大的创新点就是拥有的动态编程语言的特性，与C#和Java这些已经非常成熟且功能强大的静态编程语言相比，动态语言有的自身的优势。

它支持Read-evaluate-print-Loop 开发模式，整个过程简洁明了。

扩展方便，用户可以随时对代码进行调整。

而且它的类型是在运行时完成的，可以省去许多不必要的类型转换代码，与静态语言相比，动态编程语言写的代码往往更精练。

未来的编程语言绝大部分可能是多范式的，具有高度的可组合型，在项目或产品中组合多个编程语言、使用多种编程范式会变得越来越普遍[9]。

2.1 可行性分析EFSM模型系统主要由EFSM模型编辑器和EFSM模型动态解释执行两部分构成。

模型编辑器主要给用户提供一个可构建EFSM模型的开发环境，接着设定模型系统的初始状态，基于IronPython与C#动态交互的过程以及广度优先的搜索算法来动态解释执行EFSM模型。

1.2.1 .NET Framework 4.0的DLR(Dynamic Language Runtime)为了让C#等.NET编程语言具备动态编程语言的特性，.NET Framework 4.0引入了DLR(Dynamic Language Runtime，动态语言运行时)。

DLR运行在CLR之上，提供了一个动态语言的运行环境，从而允许Python、Ruby等动态语言编写的程序在.NET 平台上运行，同时，现有的.NET静态类型编程语言，比如C#和VB，也可以利用DLR 拥有一些动态编程语言的特性。

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INTEGRATED FINITE STATE MACHINE AND RF TIMINGMODULES FOR VMEBUS AND VXIBUS INSTRUMENTATIONK. Woodbury, C. McClureFermi National Accelerator Laboratory*Batavia, Illinois 60510 USAABSTRACTA set of control and timing modules that provide a combination of a finite state machine (FSM) interface to the accelerator clock systems and RF resolution timing have been developed. These modules provide external process control and synchronization with accelerator events. Designed for both VMEbus and VXIbus platforms, these devices provide an integrated timing resource that has been utilized by various distributed control systems at Fermilab.1. INTRODUCTIONMuch of the timing and synchronization of the accelerators at the Fermi National Accelerator Laboratory complex is done through the use of global clock-timing systems; primarily the Tevatron Clock (TCLK) and Beam Synchronous Clocks (BSCLK). These clock signals carried on serial data links consist of a carrier (TCLK = 10MHz, BSCLKs = approximately 7.5 MHz, based on the RF frequency), onto which are encoded 8 bit events. Bi-phase Mark (modified Manchester) encoding is used. Events are decoded off the data stream and delays timed using the carrier. Beam synchronous clocks exist for almost all of the major accelerators at Fermilab.In addition, primary machine parameters, such as the Main Ring and Tevatron accelerator dipole magnet currents, are transmitted on another serial link called the Machine Data (MDAT) link. MDAT data frames are also encoded using Bi-phase Mark, however, no continuous carrier is provided. Data frames on the MDAT link are 24 bits in length, including an 8 bit data frame type identifier and 16 bit data value.These clocks are distributed throughout the accelerator complex via a system of repeaters and fan-out modules, and are used by a wide variety of control and timing modules and systems.2. UNIVERSAL DECODING RESOURCEThe initial motivation for this project was the pending retirement of the Unibus Clock Decoder [1]. This module, which resided in a PDP-11 computer, was responsible for receiving and storing Tevatron Clock event data. Data received was then distributed over Ethernet for transfer to the accelerator control consoles. For compatibility with previous system development efforts, a VMEbus replacement for this module was desired.For the VME/VXIbus system designer there was also the desire to use a single module to receive and decode the various clocks described above. This would, of course, reduce the amount of crate space used, as well as eliminating the need for managing module inter-activity.In response to both of these requirements, a universal decoding module was designed. This first module was most aptly named, the VMEbus Universal Clock Decoder (VUCD) [2].3. SYSTEM ARCHITECTUREThe VUCD can decode and process the TCLK, a BSCLK, and MDAT simultaneously. The overall module architecture is shown in figure 1 below.__________________________________* Work supported by the U.S. Department of Energy, contract No. DE-AC02-76CH03000.Figure 1. VUCD Block DiagramThe major components of the module can be divided into two functional subgroups; Event Reporting, with features similar to those found on the Unibus Clock Decoder and Process Control, which is primarily used for control system and instrumentation applications.Event reporting features include:•Event FIFO memory and free-running time stamp counter with programmable time-base (1 KHz - 1 MHz).•Two commercial interrupt controllers (MX68C153) used for immediate event interrupts.•One custom, FIFO-based, interrupt controller, which is preceded by event scalers. This controller is used for generating interrupts after a programmed number of event occurrences.•MDAT memory, which hold the current machine parameter values.•Two independent event bit-map memories, one for TCLK and one for a BSCLK. These are 16 bit x 16 bit matrices which record all incoming event occurrences. Automatic clear on read and time stamp support are also provided.Process control features include:•Two independent RAM-based finite state machines (FSM), one for the TCLK and one for a BSCLK.•Output control logic for processing FSM outputs.3.1 I/O ConfigurationThe clock inputs are taken either from the front panel or the rear P2 connector of the card. Outputs generated from the TCLK or the BSCLK (shown as BSYNC), can also be presented to the front panel or to the P2 connector. Outputs are predominantly used for external instrument timing or triggering.All outputs on the P2 match VXIbus TTLTRGn* assignments and only require output driver replacement for specification compatibility.3.2 RAM-Based Finite State MachinesThe core components of the module are the two RAM based finite state machines. Figure 2 shows the basicEach FSM consists of two elements: the Option Memory (FSM RAM) which holds a list of immediate actions to be completed when a particular clock event is decoded and the Page Control Logic which contains the state register. When a particular event is decoded and all programmed actions are completed, the new state, defined by the lower four bits of the active memory location, is placed in the state register. A change in the state register value forces the Page Control Logic to point to a different section of memory and therefore an entirely different response configuration for the incoming clock events. The FSMs for the TCLK and BSCLK operate independently from one another.As shown in Figure 2, the VME/VXIbus can force the FSM to a particular state in between clock events. This capability can be used to configure a FSM with a hold state and having the exit from the hold state under program control. Additional control of the FSM is also provided by allowing the VME/VXIbus to suspend event input into the FSM. VME/VXIbus actions are arbitrated to avoid collisions with clock events.Note that there is an extra line coming from the VME/VXIbus interface into the page control. This allows for programmed transition into anther state machine stored in a different bank of memory. This effectively doubles the number of possible states from 16 to 32.These FSMs can operate very rapidly as TCLK event spacing can be as little as 1.2 µs.For a more detailed example of a RAM Based FSM see reference [3].3.3 Event Triggered ActionsEvent triggered actions can either occur automatically or are programmed into the FSM RAM.Automatically occurring actions include the following:•Marking the event in the event bit map.•Updating system status.Programmed actions include the following:•Writing the event and current time stamp into the FIFO memory.•Resetting the time stamp counter.•Counting the event and automatically generating an interrupt on terminal count (often used for process scheduling).•Generating an immediate interrupt.•Generating an output pulse.•Setting or re-setting an output level.•Changing FSM state as outlined above.3.4 MDAT data storageAll current machine parameter values received from MDAT are stored in a dual port memory for immediate access.3.5 Combined FSM OutputAs described above, the two state machines, operate independently from one another. The FSM output control bits, however, feed a common output logic block. This provides a mechanism for providing RF synchronous outputs following a pre-determined TCLK event sequence.The BSCLK resolution is 132 ns (RF frequency / 7). To provide RF resolution timing two more modules were developed as described below.4. RF RESOLUTION TIMING SUPPORT4.1 VXI-UCDThe first module to be built with RF resolution timing was a "C sized" VXIbus card called the VXI Universal Clock Decoder (VXI-UCD) [4]. The core of VXI-UCD is identical to the VUCD, however, there have been some significant features added to the board. Among them are:•8 channels of independent event delay timers (time-base options: TCLK, BSCLK, VXIbus CLK10, External to 15 MHz).•Added interrupt based on programmed MDAT frame type arrival and•RF based Pulse Pattern Generator (PPG).4.1 RF Pulse Pattern GeneratorThe PPG consists of two elements, a 64K x 8 pattern memory and a programmable address counter which is used to index into the memory. Each bit position in the memory can be thought of as a column in a table which is either a "0" or a "1". Each of these columns can be directly mapped to one of the outputs. Pattern generation is initiated by programming a start address in the address counter and an end address in the address counter. Once a trigger is received by the address counter the pattern that is programmed in the memory is then presented to the output(s).The address counter can be programmed to play a selected number of pattern cycles, or can free-run until triggered or programmed to stop.The frequency that this PPG operates in is the range 35 - 53 MHz which corresponds to the frequencies of operation for the Fermilab accelerators.4.2 VMEbus RF TimerIn order to provide the same functionality as the VXI-UCD in a 6U VMEbus form factor, a third card was made, the VMEbus RF Timer (VRFT) [5]. The VRFT combined with a VUCD provides the same essential capabilities as the VXI-UCD.4.3 Example usageAn excellent example of the use of the VXI-UCD is described below (excerpt from reference [6]).The upgrade of the Fermilab Linac from 200 MeV to 400 MeV has reduced the losses in the Booster due to space charge effects, but the increased beam current causes greater coupled bunch mode instabilities. The challenges associated with designing a coupled bunch mode damper for the Booster are a large dynamic range, afast sweeping RF system, and a large spread in tunes through the cycle. A digital system is ideal for handling these problems; therefore, digital bunched beam dampers were designed. The damper configuration is shown in Figure 3. It consists of a common mode rejection front-end, digitizing units, fast memory, a D/A unit, and power amplifiers. All of the components, except for the power amplifiers, are VXI compatible and can be controlled with a personal computer or any other VXI control system.Figure 3: Block diagram of Fermilab Booster transverse digital damper system.The RF accelerating voltage in the Booster must ramp from a frequency of 37 MHz to 53 MHz in a cycle time of 33 ms, and the non-linear frequency ramp has a peak slope of 1 GHz/s near the beginning of the cycle. The revolution period varies from 2.8µs to 1.59µs. To maintain feedback on the proper bucket, the processing system must handle 1.21µs of delay change quickly.The VXI-UCD cards maintain the proper delay by remaining locked to the beam. The waveform generator memory is programmed with an interleaving pattern and clocked with an external reference which is the beam reference oscillator. This pattern triggers the digitzers to sample the beam and also triggers the digitizers to send signal to the kicker. The pattern can also be fine tuned to allow for single bucket precision in adjusting the delay.VXI-UCD cards also act as interpreters of the laboratories global trigger system. These triggers are used to control the start and stop times of the system as well as external gates which turn of the signal during delicate times of the acceleration cycle.5. POSSIBLE IMPROVEMENTSPossible improvements for these modules include:5.1 State TracingState tracing capabilities can be especially useful for process control and interfacing. This feature requires storing not only event and time stamp information, but state and possibly state transition information as well.5.2 Enhanced Multi-processor SupportTo improve support for multi-processor systems, an effective method for providing several message queues could be employed. This could include state tracing information as described above.5.3 Improved PPG output phase adjustmentImproved linearity of the PPG output phase adjustment circuitry would be beneficial, as the current circuitry shows significant phase variation over the full frequency range of operation.6. CONCLUSIONThese modules have proven to be an effective tool for the Fermilab VME/VXIbus system designer. They provide a seamless interface to the accelerator timing systems and provide RF resolution synchronization capabilities as well.7. ACKNOWLEDGMENTSWe wish to acknowledge David DuPuis who did the layout and prototype assembly of all of these modules and Jay Ticku who designed several of the timer chips used on the boards. We also wish to acknowledge all of the users, whose support and encouragement helped make these modules a reality. Special thanks to Jim Steimel for providing the module usage example (4.3) for this manuscript.8. REFERENCES[1]W. Knopf, "Unibus Clock Decoder", Controls Hardware Release 30.0, 1983. Fermi National AcceleratorLaboratory document.[2] C. McClure, Kerry Woodbury, et. al., "VUCD User's Manual", Controls Hardware Release 90.01, 1994.Fermi National Accelerator Laboratory document.[3] D. Beechy, "A Programmable Finite State Module for use with the Fermilab Tevatron Clock", Fermi NationalAccelerator Laboratory document.[4]K. Woodbury, Craig McClure, et. al., "VXI-UCD User's Manual", Controls Hardware Release 91.0, 1994.Fermi National Accelerator Laboratory document.[5]K. Woodbury, "VRFT-beta User's Manual", Controls Hardware Release 93.0, 1995. Fermi NationalAccelerator Laboratory document.[6]J. Steimel, "Fast Digital Dampers for the Fermilab Booster", Proceedings of the 1995 Particle AcceleratorConference, publication pending.。