全加器及半加器verilog
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module quanjiaqi(ain,bin,c,out);
input [3:0]ain,bin;
output [3:0]out;
output c;
wire c1,c2,c3;
fulladder u0(.a(ain[0]),.b(bin[0]),.cin(1'b0),.cout(c1),.out(out[0]));
fulladder u1(.a(ain[1]),.b(bin[1]),.cin(c1),.cout(c2),.out(out[1]));
fulladder u2(.a(ain[2]),.b(bin[2]),.cin(c2),.cout(c3),.out(out[2]));
fulladder u3(.a(ain[2]),.b(bin[2]),.cin(c3),.cout(c),.out(out[3]));
endmodule
module fulladder(a,b,cin,out,cout);
input a,b,cin;
output cout,out;
assign out=a^b^cin;
assign cout=(a&b)|(a&cin)|(b&cin);
endmodule
`timescale 1ns/1ns
module top;
reg [3:0]ain,bin;
wire [3:0] out;
wire c;
quanjiaqi m(ain,bin,out,c);
initial
begin
ain=4'b0000;bin=4'b0000;
#100 ain=4'b0111;bin=4'b0101;
#100 $stop;
end
endmodule
半加器
module mux(a,b,sl,out);
input a,b,sl;
output out;
assign out=(sl==0)?a:b;
endmodule
module erjiaqi(a,b,c,sum);
input a,b;
output c,sum;
mux u0(.a(a),.b(b),.sl(a),.out(c));
mux u1(.a(~c),.b(a),.sl(~b),.out(sum));
endmodule
`timescale 1ns/1ns
module top;
reg a,b;
wire c,sum;
erjiaqi m(a,b,c,sum);
initial
begin
a=0;
b=0;
#100 a=1;b=0;
#100 a=1;b=1;
#100 a=0;b=1;
#100 $stop;
end
endmodule