frequwent4位十进制VHDL语言写的

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library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity freqtest is

PORT ( CLK:IN STD_LOGIC;

Fsin:IN STD_LOGIC;

DOUT0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

DOUT1:OUT STD_LOGIC_VECTOR(7 DOWNTO 4);

DOUT2:OUT STD_LOGIC_VECTOR(11 DOWNTO 8);

DOUT3:OUT STD_LOGIC_VECTOR(15 DOWNTO 12);

ou : OUT STD_LOGIC);

end freqtest;

architecture struc of freqtest is

component TESTCTL

PORT( CLKK:IN STD_LOGIC;

CNT_EN,RST_CNT,LOAD:OUT STD_LOGIC);

END component;

component cnt10

PORT(en:in std_logic;

rst:in std_logic;

clk:in std_logic;

cq:out std_logic_vector(3 downto 0);

cout:out std_logic);

END component;

component REG4B

PORT( LOAD : IN STD_LOGIC;

DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );

END component;

signal tsten1,clr_cnt1,load1,CARRY_OUT0,CARRY_OUT1,CARRY_OUT2: std_logic;

signal DIN : STD_LOGIC_VECTOR( 15 DOWNTO 0);

begin

u1: TESTCTL port map(CLKK=>CLK,CNT_EN=>tsten1,RST_CNT=>clr_cnt1,LOAD=>load1);

u2: cnt10 port map(en=>tsten1,clk=>Fsin,rst=>clr_cnt1,cq=>DIN(3 DOWNTO 0),cout=>carry_OUT0);

U3: cnt10 port map(en=>tsten1,clk=>carry_OUT0,rst=>clr_cnt1,cq=>DIN(7 DOWNTO 4),cout=>carry_OUT1);

U4: cnt10 port map(en=>tsten1,clk=>carry_OUT1,rst=>clr_cnt1,cq=>DIN(11 DOWNTO 8),cout=>carry_OUT2);

U5: cnt10 port map(en=>tsten1,clk=>carry_OUT2,rst=>clr_cnt1,cq=>DIN(15 DOWNTO 12),cout=> ou);

U6: REG4B port map(LOAD=>load1,DIN=>DIN(3 downto 0),DOUT => DOUT0(3 downto 0)); U7: REG4B port map(LOAD=>load1,DIN=>DIN(7 downto 4),DOUT => DOUT1(7 downto 4));

U8: REG4B port map(LOAD=>load1,DIN=>DIN(11 downto 8),DOUT => DOUT2(11 downto 8));

U9: REG4B port map(LOAD=>load1,DIN=>DIN(15 downto 12),DOUT => DOUT3(15 downto 12));

END struc;