基于VHDL语言的时钟电路设计
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基于VHDL语言的时钟电路设计LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count6 IS
PORT(clk :IN STD_LOGIC;
clr,en:IN STD_LOGIC;
q2:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0); CO:out STD_LOGIC);
END count6;
ARCHITECTURE a OF count6 IS
BEGIN
PROCESS(clk)
BEGIN
IF clr='0'THEN
q2<="0000";
ELSIF clk'event AND clk='1'THEN
IF en='1'THEN
IF q2="0101"THEN
q2<="0000";
CO<='1';
ELSE
q2<=q2+1;
CO<='0';
END IF;
END IF;
END IF;
END PROCESS;
END a;
十进制程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count1 IS
PORT(clk :IN STD_LOGIC;
clr,en:IN STD_LOGIC;
q0:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0); CO:out STD_LOGIC);
END count1;
ARCHITECTURE a OF count1 IS
BEGIN
PROCESS(clk)
BEGIN
IF clr='0'THEN
q0<="0000";
ELSIF clk'event AND clk='1'THEN
IF en='1'THEN
IF q0="1001"THEN
q0<="0000";
CO<='1';
ELSE
q0<=q0+1;
CO<='0';
END IF;
END IF;
END IF;
END PROCESS;
END a;
二十四进制程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count24 IS
PORT(clk :IN STD_LOGIC;
clr,en:IN STD_LOGIC;
q6,q7:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); END count24;
ARCHITECTURE a OF count24 IS
BEGIN
PROCESS(clk,en,clr)
BEGIN
if clr='0' then
q7<="0000";
q6<="0000";
elsif clk'event and clk='1' then
if en='1' then
IF q6="0010" AND q7="0011" THEN
q6<="0000";
q7<="0000";
elsif q7="1001" then
q7<="0000";
q6<=q6+1;
else
q7<=q7+1;
end if;
end if;
end if;
END PROCESS;
END a;
六十进制(秒表)程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count60 IS
PORT(clk :IN STD_LOGIC;
clr,en : IN STD_LOGIC;
q1,q3 : BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0); CO : OUT STD_LOGIC);
END count60;
ARCHITECTURE a OF counT60 IS
COMPONENT count1
PORT(clk :IN STD_LOGIC;
clr,en : IN STD_LOGIC;
q0 : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
CO : OUT STD_LOGIC);
END COMPONENT;
COMPONENT count6
PORT(clk :IN STD_LOGIC;
clr,en : IN STD_LOGIC;
q2 : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
CO : OUT STD_LOGIC);
END COMPONENT ;
signal n1: STD_LOGIC;
BEGIN
h0:count1
PORT map(clk=>clk,clr=>clr,en=>en,q0=>q1,co=>n1);
h1:count6
PORT map(clk=>n1,clr=>clr,en=>en,q2=>q3,co=>co);
END a;
分钟程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count120 IS
PORT(clk :IN STD_LOGIC;
clr,en : IN STD_LOGIC;
q1,q2,q4,q5 : BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0); CO : OUT STD_LOGIC);
END count120;
ARCHITECTURE a OF counT120 IS
COMPONENT count60
PORT(clk :IN STD_LOGIC;
clr,en : IN STD_LOGIC;
q1,q3 : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
CO : OUT STD_LOGIC);