Timing Acquisition for Distributed Antenna Systems by Exploiting the Advantages of Cooperation

合集下载

北斗定位-毕业论文外文文献翻译

外文文献原稿和译文原稿Beidou positioningPrefaceNavigation satellite systems can provide all time, all weather and high accuracy positioning, navigation and timing services to users on the earth surface or in the near-earth space. It is an important space inf rastructure, which extends people’s range of activities and promotes social development. Satellite navigation is bringing up revolutionary changes to the world politics, economy, military, technology and culture.With a long history and a splendid culture, China is one of the important cradles of early human civilization. In ancient times, Chinese people used the Big Dipper (Beidou) for identifying directions, and invented the world’s first navigation device, the ancient compass (Sinan), which was a great contribution to the development of world civilization. In modern society, the Chinese-built BeiDou（COMPASS） system will become another contribution to the mankind.In early 1980s, China began to actively study the navigation satellite systems in line with C hina’s conditions. In 2000, BeiDou Navigation Demonstration System is basically established, which made China the third nation in possession of an independent navigation satellite system following the United States and Russia. At present, China is steadily accelerating the construction of the BeiDou Navigation Satellite System, and has already successfully launched 10 satellites so far.The BeiDou system will meet the demands of China’s national security, economic development, technological advances and social progress, safeguard national interests and enhance the comprehensive national strength. The BeiDou system will commit to providing stable, reliable and quality satellite navigation services for global users. Along with other GNSS providers, the BeiDou system will jointly promote the development of satellitenavigation industry, make contributions to human civilization and social development, serve the world and benefit the mankind.I. System DescriptionThe BeiDou system is comprised of three major components: space constellation, ground control segment and user terminals. The space constellation consists of five GEO satellites and 30 non-GEO satellites. The GEO satellites are positioned at 58.75°E, 80°E, 110.5°E, 140°E and 160°E respectively. The non-GEO satellites include 27 MEO satellites and three IGSO satellites. The MEO satellites are operating in an orbit with an altitudeof 21,500 km and an inclination of 55°, which are evenly distributed in three orbital planes. The IGSO satellites are operating in an orbit with an altitude of 36,000 km and an inclination of 55°, which are evenly distributed in three inclined geo-synchronous orbital planes. The subsatellite track for the three IGSO satellites are coincided while the longitude of the intersection point is at 118°E, with a phase difference of 120°.Ground control segment consists of several Master Control Stations (MCS), Upload Stations (US) and a network of globally distributed Monitor Stations (MS). The main tasks of MCS are to collect observing data from each MS, to process data, to generate satellite navigation messages, wide area differential data and integrity information, to perform mission planning and scheduling, and to conduct system operation and control. The main tasks of Upload Stations include completing the upload of satellite navigation messages, wide area differential data and integrity information, controlling and managing the payload. The tasks of Monitor Stations include continuous tracking and monitoring of navigation satellites, receiving navigation signals, sending observational data to the Master Control Station for the satellites orbit determination and time synchronization.The user terminals include various BeiDou user terminals, and terminals compatible with other navigation satellite systems, to meet different application requirements from different fields and industries.The time reference for the BeiDou Navigation Satellite System uses BeiDou Time (BDT). BDT’s length of second is a SI second. BDT was zero at 0:00:00 on Janu ary 1, 2006 Coordinated Universal Time (UTC). BDT is a continuous system, traceable to the UTC time maintained by the National Time Service Center (NTSC) of ChineseAcademy ofSciences, which is referred to as UTC (NTSC). The leap seconds with UTC information is broadcasted in the navigation messages. The difference between BDT and UTC maintains within 100ns.The coordinate framework of BeiDou system adopts China Geodetic Coordinate System 2000 (CGCS2000).Upon the full system completion, the BeiDou Navigation Satellite System can provide positioning, navigation and timing services to worldwide users. It can also provide wide area differential services with the accuracy of 1m and short messages services with the capacity of 120 Chinese characters each time.·Main functions: positioning, velocity measurement, one-way and two-way timing, short messages·Service area: global·Positioning accuracy: better than 10m·Velocity accuracy: better than 0.2m/s·Timing accuracy: 20nsII. System DevelopmentThe BeiDou system has followed the development concept of starting with regional services first and expanding to global services later. A three-step development strategy has been taken, with specifics as follows:Phase I: BeiDou Navigation Satellite Demonstration System. In 1994, Chinastarted the construction of BeiDou Navigation Satellite Demonstration System. In 2000, two BeiDou navigation experiment satellites were launched, and the BeiDou Navigation Satellite Demonstration System was basically established. In 2003, the third BeiDou navigation experiment satellite was launched, further enhancing the performance of the BeiDou Navigation Satellite Demonstration System.BeiDou Navigation Satellite Demonstration System consists of three major components: space constellation, ground control segment and user terminals. The space constellation includes three geostationary orbit (GEO) satellites, positioned at longitude of 80 degrees East, 110.5 degrees East and 140 degrees East respectively above the equator. Ground control segment consists of the ground control center and a number of calibrationstations. The ground control center is to complete satellite orbit determination, ionospheric correction, user location determination and user short message information exchange and processing. The calibration ground control stations are mainly to provide the distance measurement and correction parameters to the ground control center.The user terminals include the hand-held type, vehicle type, command type and other types of terminals, capable of position service application, location coordinates information receiving and other functions.The main functions and performance specifications of the BeiDou Navigation Satellite Demonstration System are as follows:·Main functions: positioning, one-way and two-way timing, short message communications;·Service Area: China and the surrounding areas;·Positioning Accuracy: better than 20 meters;·Timing Accuracy: 100 ns one-way, two-way 20 ns;·Short message communications: 120 Chinese characters per time.Phase II: BeiDou Navigation Satellite (regional) System. In 2004, Chinastarted construction of BeiDou Navigation Satellite System. In 2007, the first satellite, a round medium earth orbit satellite (COMPASS-M1) was launched. By 2012, the BeiDou system will consist of 14 satellites, including five GEO satellites, five IGSO satellites (two in-orbit spares), and four MEO satellites.The functions and performance parameters of BeiDou Navigation Satellite (regional) System are as follows:·Main functions: positioning, velocity measurement, one-way and two-way timing, short message communications;·Service Area: China and part of Asia- Pacific region ;·Positioning Accuracy: better than 10 meters;·Velocity Accuracy: better than 0.2 m/s;·Timing Accuracy: 50 ns;·Short message communications: 120 Chinese characters per message.Phase III: BeiDou Navigation Satellite System will completely be established by 2020.III. System ApplicationsSince it was officially brought into service in 2003, the BeiDou Navigation Satellite Demonstration System has been widely used in transportation, marine fisheries, hydrological monitoring, weather forecasting, forest fire prevention, timing for communication systems, power distribution, disaster mitigation, national security, and many other fields, which has been resulting in significant social and economic benefits. Particularly, the system has played an important role in the South China frozen disaster, earthquake relief in Wenchuan, SichuanProvince and Yushu, Qinghai Province, the Beijing Olympic Games, and the Shanghai World Expo.—In the field of transportation, built on the Beidou Navigation Satellite Demonstration System, applications such as Xinjiang Satellite Navigation Monitoring System of Public Transport, the Highway Infrastructure Safety Monitoring System, and the Port Scheduling High-precision Real-time Position Monitoring System, have promoted the BeiDou system and achieved a good demonstration effect.—In marine fisheries, built on the BeiDou Navigation Satellite Demonstration System, the marine fisheries integrated information service platform has provided vessel position monitoring, emergency rescue, information distribution, fishing boats in and out of port management and other services to the fishery administration departments.—The hydrological monitoring system, based on the BeiDou Navigation Satellite Demonstration System, has realized the real-time transmission of hydrological forecast information in mountainous regions, which has improved the accuracy o f the disaster forecasting and has helped the planning and scheduling programs for the flood and drought control.—In the field of weather forecasting, a series of BeiDou terminal equipment have been developed for weather forecast, and various practical and feasible system solutions have been worked out to address the automatic data transmission issues for the China Meteorological Administration and a number of local weather centers and stations.—In the field of forest fire prevention, the BeiDou Navigation Satellite Demonstration System has been successfully used in forest fire prevention system. Its positioning and short message communication services have achieved good results.—In the field of time synchronization for communication systems, the successful implementation of BeiDou two-way timing demonstration program has achieved breakthroughs in some key technical areas such as long distant fiber technology, and an integrated satellite-based timing system has been developed.—In the field of power distribution, built on the BeiDou Navigation Satellite Demonstration System, the successful implementation of power system time synchronization demonstration program has created basis for the high precision applications such as the electric accident analysis, the electricity early warning and protection systems.—In the field of disaster mitigation, the navigation, positioning, short message communications and position reporting capabilities of the BeiDou Navigation Satellite Demonstration System have provided services for the nationwide real-time disaster relief commanding and dispatching, emergency communications, rapid reporting and sharing of disaster information, which has significantly improved the rapid response of the disaster emergency relief and decision-making capability.Upon the full completion, the BeiDou Navigation Satellite System will provide more high-performance positioning, navigation, timing and short-message communication services for civil aviation, shipping, railways, finance, postal and other industries.IV. International Exchange and CooperationThe international exchange and cooperation for the BeiDou Navigation Satellite System will be carried out in an active and pragmatic way, which is in line withChina’s foreign policies, focusing on China's basic tasks and strategic objectives for the construction of navigation satellite systems, using the domestic and international markets and resources in a coordinated way. The international exchange and cooperation will be proceeded in a phased, focus-centered, non-discriminatory and selective approach in accordance with the overall development plan of China's navigation satellite system. It will be built upon the basis of equality, mutual benefit, mutual complementarity, peaceful utilization and mutual development and the generally accepted principles of the international laws.The BeiDou Navigation Satellite System adheres to the open and friendly attitude, and has already carried out extensive exchanges and consultation with the countries that have navigation satellite systems, to promote navigation satellite system compatibility and interoperability globally. Through the exchange and cooperation with countries that do not have a navigation satellite system, we also support their use of the existing resources globally and share the benefits of the satellite navigation development.China's international exchange and cooperation in the field of satellite navigation started in the 1990s. In nearly 20 years, various forms of activities have been carried out with extensive results.In 1994, under the framework of International Telecommunication Union(ITU),China started the BeiDou Navigation Satellite System frequency coordination activities. Satellite network information was submitted in accordance with the BeiDou system construction plan and progress. International frequency coordination has been carried out in a phased, step by step, focus-centered approach. China has actively participated bilateral frequency coordination activities with Europe, the UnitedStates and Russia, and has actively taken part in the World Radiocommunication Conference and the meetings of ITU study groups and working groups.China, as an important member of the International Committee on Global Navigation Satellite Systems (ICG), has participated in every ICG General Assembly Meeting and the ICG Providers Forum. In 2007, China became one of the four core providers designated by the organization. Focusing on compatibility and interoperability, China has carried out the extensive exchange and cooperation with the other navigation satellite systems in the world. The Technical Working Group (TWG) on compatibility and interoperability between BeiDou and Galileo was established. Until now, seven TWG meetings have been held.China actively participates, organizes and hosts international academic exchanges on satellite navigation, which include the American Institute of Navigation (ION) Conferences, the International Symposium on GPS/GNSS (ISGNSS), Munich Satellite Navigation Summit and other international conferences and forums. The China academic conferenceon satellite navigation is held annually, together with many other forums and seminars.China encourages and supports domestic research institutions, industrial enterprises, universities and social organizations, under the guidance of the government policy, to carry out international exchanges, coordination and cooperation activities with other countries and international organizations in the fields of the compatibility and interoperability, satellite navigation standards, coordinates frame, time reference, application development and scientific research. China has been actively engaged in international activities in terms of monitoring and assessment of open service for GNSS to promote the BeiDou Navigation Satellite System better serving the global users, and to promote the development of satellite navigation technology.ConclusionThe rapid development of the BeiDou Navigation Satellite System is attributedto China's reform and opening-up policy as well as the sustainable development of economy. As always, China will continue to promote the Global Navigation Satellite System construction and industrial development, to encourage the use of new satellite navigation technologies to provide new services, meeting the growing diversified needs of the people. By actively propelling international exchanges and cooperation, China will realize the compatibility and interoperability between the BeiDou Navigation Satellite System and other navigation satellite systems in the world. China will provide global customers with high performance and highly reliable positioning, navigation and timing services.The Launch Record of BeiDouNavigation Satellites·October 31, 2000, launch of 1st BeiDou navigation experiment satellite.·December 21, 2000, launch of 2nd BeiDou navigation experiment satellite.·May 25, 2003, launch of the 3rd BeiDou navigation experiment satellite.·February 3, 2007, launch of the 4th BeiDou navigation experiment satellite.·April 14, 2007, launch of the 1st BeiDou navigation satellite.·April 15, 2009, launch of the 2nd Beidou navigation satellite.·January 17, 2010, launch of the 3rd BeiDou navigation satellite.·June 2, 2010, launch of the 4th BeiDou navigation satellite.·August 1, 2010, launch of the 5th BeiDou navigation satellite.·November 1, 2010, launch of the 6th BeiDou navigation satellite. ·December 18, 2010, launch of the 7th BeiDou navigation satellite. ·April 10, 2011, launch of the 8th BeiDou navigation satellite. ·July 27, 2011, launch of the 9th BeiDou navigation satellite. ·December 2, 2011, launch of the 10th BeiDou navigation satellite.译文北斗定位前言卫星导航系统可以提供所有的时间，所有天气情况下用户在地球表面或近地空间的高精度定位、导航和授时服务。

关于PLC的中英文对照翻译

原文：PLC Communication using PROFINET: ExperimentalResults and AnalysisAbstractPROFINET is the Industrial Ethernet Standard devised by PROFIBUS International for “Ethernet on the plant ﬂoor”. PROFINET allows to implement a comprehensive communications solution on Ethernet which includes peer-to-peer communication between controllers, distributed I/O, machine safety, motion control and data acquisition. In this paper an analysis is conducted on the peer-to-peer interlocking performance based on PROFINET speciﬁcation. Tests were performed to determine the performance of the peer-to-peer communication mechanism, to evaluate the impact of switches on the system, and to measure the impact of data size on peer-to-peer communication performance. The paper summarizes the test results. 1.IntroductionAlthough a wide variety of networks and ﬁeldbuse s have been used in the manufacturing industry over the past decade [1], the widespread adoption of Ethernet as a de facto standard in other domains (e.g., the internet) has made it an attractive option to consider. The increased network speed and the reduced cost of devices has further heightened interest. The introduction of switched Ethernet has allowed formore deterministic behavior and alleviated many of the concerns about unbounded delays [2, 3, 4]. Ethernet is already being widely used as a diagnostic network in manufacturing systems and is making inroads into the control networking domain [5, 6].However, standard Ethernet (IEEE 802.3) is not a deterministic protocol, and network quality of service cannot be guaranteed. To address this inherent nondeterminism, different “ﬂavors” of Ethernet have been proposed for use in industrial automation. Several of these add layers on top of standard Ethernet or on top of the TCP/IP protocol suite to enable the behavior of Ethernet to be moredeterministic [7]. However, the network solutions may no longer be “Ethernet” other than at the physical layer.Since time delay is an important issue in control systems, there have been a number of projects devoted to analyzing and experimentally testing network performance for use in control systems. It has been shown that the largest component of the time delay in sending messages from one node to another is typically not on the network itself, but rather the application layer that interfaces to the network [8, 9]. Experimental analyses have been carried out to speciﬁcally address the issue of delays in switched Ethernet [10, 4]. However, due to the relatively recent introduction of commercial devices that implement the new industrial Ethernet protocols, there have been only a few published accounts of their actual performance [11, 12].Over the past six months, our group at the University of Michigan has undertaken an industrial Ethernet testing project [13]. The goal of the project was to evaluate the suitability of real-time Ethernet for peer-to-peer communication between PLCs on a factory ﬂoor. The purpose of this paper is to summarize the results of our tests on PROFINET, and discuss our ﬁndings.The outline of the paper is as follows. In Section II, we summarize how PROFINET enables real-time communication over Ethernet. In Section III, we describe the tests that were performed. Section IV presents the results of those tests, and conclusions are given in Section V.2.PROFINET CBA with Real-Time Channel Communication PROFINET distinguishes two views: PROFINET IO for integration of distributed I/O and PROFINET CBA (Component Based Automation) for creation of peer-to-peer communication and interlocking between controllers in modular plants (Figure 1)All other PROFINET applications such as safety, motion control, and HMI (Human Machine Interface) are based on these communication modes. PROFINET communication is scalable in three levels: PROFINET TCP/IP Communication (NRT) enables cycle times as low as 100 ms, PROFINET Real-Time Communication (RT) enables cycle times up to 1-10 ms and Isochronous Real-Time Communication (IRT) enables cycle times up to 1 ms with Jitter less than 1µs.Component based communication is realized through PROFINET CBA which uses selectively the TCP/IP or the Real-Time (RT) channel. Communication for distributed I/O is implemented through PROFINET I/O which uses Real-Time and Isochronous Real-Time (IRT) communication.PROFINET Real-Time Channel The PROFINET Real Time Channel is a cyclic communication path used by individual stations to exchange time critical data at periodic intervals speciﬁed by the programmer. It is based on the IEEE and IEC deﬁnition s [14], which only permit a limited time for execution of Real-Time services within a bus cycle. Real-Time data are handled with higher priority than Non-Real-Time (NRT) data. The tightness of the window depends on the Real-Time characteristics. The Real-Time mechanism is based on Layer 2 of the OSI model and several protocol layers are omitted. Thus the communication overhead associated with preparing data, transferring it and making it available to the overlying application for use are reduced. Using Ethereal it was found that the total overhead associated with Cyclic Real Time communication is 56 bytes.3.Tests PerformedThe following tests were designed to measure the impact of system parameters on peer-to-peer interlocking performance using PROFINET CBA with RTcommunication method. The system parameters include data size and number of switches. The tests are vendor neutral so that any implementation can be conﬁgured to undergo each test. Connection failures or errors are not included in this test plan. To perform tests the following equipment was used: one computer with Matlab and the protocol analyzer Ethereal, SIMATIC iMap and STEP7 as conﬁguration software, ﬁve switches from Hirschmann and two Siemens SIMATIC PLCs (Programmable Logic Controllers). The PLCs were conﬁgured using the factory defaults for processor and communication allocation options. The Hirschmann switches (100Mbps) were conﬁgured for port speed auto negotiation. Due to the fact that PROFINET is based on Unicast communication the Multic ast functionality was not conﬁgured in the switches.3.1 PerformanceMetricsThe performance metrics analyzed are PLC1 Packet Time Interval and Round Trip Time Interval.PLC1 Packet Time Interval is the time between two successive transmittals of packets from PLC1. Ideally, the PLC1 Packet Time Interval is always exactly the same as the conﬁgured update interval in the PLC. However, in practice there is some variability associated with this interval. The experimental results that follow summarize the average (mean value) and the jitter (standard deviation) of the PLC1 packet time interval. These metrics (mean and standard deviation) are important, as they give ameasure of the determinismthat can be obtained for realtime control using PROFINET.Round Trip Time Interval is deﬁned as the Time Interval needed for a packet from PLC1 to reach PLC2, be echoed and come back to PLC1. Consider a test where PLC1 generates data and PLC2 echoes themback to PLC1 through a switch.Figure 2 shows the timing chart for the communication between PLC1 and PLC2 where PLC1 sends messages at T1, T2, T3,. . . and PLC2 echoes at t1, t2, t3,. . . . PLC1 Packet Time Interval should be equal to the conﬁgured update interval on PLC1, and PLC2 Packet Time Interval should be equal to conﬁgured update interval on PLC2. If the echo from PLC2 arrives before T2, then the round trip counter getsincremented and the new value is transmitted from PLC1 at T2. Since the increment of the round trip counter is taken for calculation of the Round Trip Time Interval, in this case it should be equal to the PLC1 Packet Time Interval. Consider the case when t1 shifts relative to T2. Then the echo fromPLC2 is received after T2, and the round trip counter is not incremented in themessage transmitted from PLC1 at T2. Hence, the Round Trip Time Interval becomes twice the PLC1 Packet Time Interval.Figure 2. Timing chartFrom the above observations it is noticed that Round Trip Time interval mean and standard deviation are also important as measures of the degree of synchronization for real-time control using PROFINET.3.2 Test DescriptionsTest1: Benchmark Test1 is the benchmark test. The other tests are compared to Test1. In this test PLC1 generates eight bytes of data and PLC2 echoes it back to PLC1 through a switch. PLC1 uses the last 4 bytes (dint) of the data for a new data received counter. PLC1 increments this counter as discussed in section 3.1.To perform measurements, a PC running Ethereal was connected to the managed switch which connects to the PLCs. All packets going to and from PLC2 and theirrespective timestamps were mirrored onto this port.Test2: Network Switches The objective of Test2 is to evaluate the impact that switches introduce to the system. The number of switches between two PLCs is the test variable. The same variables are measured as in Test1. We will consider the case of three and ﬁve switches between the PLCs.Test3: Size of Data The objective of Test3 is to measure the impact of data size on peer-to-peer communication performance. The test variable is the data size. Measurements are performed as described in Test1. We will consider two cases. In the ﬁrst case 216 bytes of unused data, in the second 440 bytes of unused data.4.Test ResultsIn performing the tests and analyzing the results a data capture of 5000 packets per PLC is considered in order to assess the timing performance. The average and standard deviation values of PLC1 Packet Time Interval and Round Trip Time Interval are measured in milliseconds and rounded off to th ree signiﬁcant digits after the decimal point. All tests are performed with an update time of 8ms which is typical for these applications in the factory. Figures 3, 4 and 5 show the benchmark test results, PLC1 Packet Time Interval, Round Trip Time Interval histogram, and Round Trip Time Interval scattering diagram respectively. We can notice the highly deterministic behavior of the network. Since we are using the PROFINET RT protocol a similar behavior is expected also from the other tests.Figure 3. Test1 PLC1 Packet Time Interval histogram4.1 Network SwitchesTo evaluate the impact that switches introduce to the system, data results from Test1 will be compared to those obtained from Test2. Tables 1 and 2 show that, in the case of three or ﬁve switche s between two PLCs, there are no signiﬁcant changes between the two tests. PLCs Packet Time Interval and Round Trip Time Interval present the same average value and similar standard deviation. Figure 6 shows the histogram of round trip time interval for Test2 which is close to that of Test1 (Figure 4). As expected the switches do not alter the performance metrics. Similar resultswere found in [10].Figure 4. Test1 Round Trip Time Interval histogramFigure 5. Test1 Round Trip Time Interval scattering diagramFigure 6. Test2 Round Trip Time Interval histogram, case with 3 switches4.2 Size of DataBy comparing the results of Test1 and Test3 we will measure the impact of data size on peer-to-peer communication performance. As observed in Tables 1 and 2, PLC1 packet and Round Trip Time Interval average values are the same. In both PLC1 packet and Round Trip Time Intervals there is a decrease of value in standard deviation. Figure 7 shows the Round Trip Time Interval of Test3 with three switches which behaves like Test1 round trip interval (Figure 4). From the results obtained (Tables 1 and 2) we can conclude that data size does not impact Packet and RoundTrip Time Interval.Figure 7. Test3 Round Trip Time Interval histogram, case with 216 bytes 5.ConclusionsTo measure the impact of data size carried by a packet and switches on a PROFINET CBA with RT communication based network three tests were designed. Test1, represented by a simple network made of two PLCs and one switch, was used as benchmark. Figures 3, 4 and 5 showed the deterministic behavior of the network. Test2 is similar to Test1 but instead of one switch, three to ﬁve have been used. Test3 is also similar to Test1 but, instead of using 8 bytes data per packet, 216 and 440 bytes were used. To investigate the delay introduced by the switches Test1 and Test2 results were compared. The impact of data size was analyzed by comparing Test1 and Test3. Results show that PLC1 Packet Time Interval and Round Trip Time Interval are unaffected by data size per packet and number of switches. AcknowledgementsThis work was supported in part by the Engineering Research Center for Reconﬁgurable Manufacturing Systems of the National Science Foundation under Award Number EEC-9529125. The authors would also like to acknowledge the support received from General Motors Powertrain, Siemens and Hirschmann in thecompletion of the tests.References[1] J.-P. Thomesse, “Fieldbus Technology in Industrial Automation”, Proc. of theIEEE, vol. 93, no. 6, 2005.[2] J. M oyne and F. Lian, “Design considerations for a sensor bus system insemiconductor manufacturing”, in International SEMATECH AEC/APC Workshop XII, 2000.[3] P. G. Otanez, J. T. Parrott, J. R.Moyne, and D. M. Tilbury, “The Implications ofEthernet as a Co ntrol Network”, in Proc. of the Global Powertrain Congress, 2002.[4] K. C. Lee and S. Lee, “Performance evaluation of switched Ethernet fornetworked control systems”, in Proc. of IEEE Conf. of the Industrial Electronics Society, volume 4, 2002.[5] J.-D. Decotignie, “Ethernet-Based Real-Time and Industrial Communications”,Proc. of the IEEE, vol. 93, no. 6, 2005.[6] J. Montague, “Networks Busting Out All Over”, Control Engineering, vol. 52, no.3, March 2005.[7] M. Felser, “Real-Time Ethernet—Indus try Prospective”, Proc. of the IEEE, vol. 93,no. 6, 2005.[8] F.-L. Lian, J. R. Moyne, and D. M. Tilbury, “Network Design Consideration forDistributed Control Systems”, IEEE Trans. on Control Systems Technology, vol.10, no. 2, 2002.[9] J. T. Parrott, J. R. Moyne, and D. M. Tilbury, “Experimental Determination ofNetwork Quality of Service in Ethernet: UDP, OPC, and VPN”, in Proc. of the American Control Conf., 2006.[10] E. V onnahme, S. Ruping, and U. Ruckert, “Measurements in switched Ethernetne tworks used for automation systems”, in Proc. of IEEE International Workshop on Factory Communication Systems, 2000.[11] P. Ferrari, A. Flammini, and S. Vitturi, “Response Times Evaluation ofPROFINETNetworks”, in Proc. of the IEEE Int. Symposium on IndustrialElectronics, 2005.[12] P. Ferrari, A. Flammini, D.Marioli, and A. Taroni, “Experimental evaluation ofPROFINET performance”, in Proc.of the IEEE Int.Workshop on Factory Communication Systems (WFCS), 2004.[13] K. Acton, S. Mantri, J. Parrott, N. Kalappa, M. Antolovic, J. Luntz, J. Moyne,and D. Tilbury, “UM-ERC Industrial Ethernet Evaluation Project: Peer-to-peer Interlockign Performance Report”, Technical report, University of Michigan Engineering Research Center for Reconﬁgurable Manufactu ring Systems, February 2006.[14] M. Popp, K. Weber, “The Rapid Way to PROFINET”,Editor PROFIBUSNutzeroranisation e.V., 2004.译文：PROFINET在PLC通讯中的使用：实验结果及分析摘要：PROFINET是国际现场总线在“以太网物理层”分离出来的工业以太网标准。

Later Can Be Better Increasing Concurrency of Distributed Transactions

Later Can Be BetterIncreasing Concurrency of Distributed TransactionsWeihai YuDepartment of Computer ScienceUniversity of TromsøNorwayweihai@cs.uit.noAbstractDistributed transactions have poor scalability, both in terms of the amountof concurrent transactions, and the number of sites a distributed transactionmay involve. One of the major factors that limit distributed transactionscalability is that every site that a transaction involves has to hold dataresources until the termination of the entire transaction, i.e., every sub-transaction’s lifetime of resource consumption is bounded to the slowestsub-transaction. There are several solutions to this problem. The basic ideaof these solutions is to release data resources as early as possible before thetermination of the entire distributed transaction. These solutions eithersuffer from cascading aborts or require knowledge of application businessdetails such as the use of compensation. In this paper, we present a totallydifferent approach that delays altruistically the execution of fast sub-transactions. We will show that this approach increases concurrency of theentire distributed system without sacrificing transaction response time.Furthermore, this approach assumes no more than strict two-phase lockingand requires very little knowledge of specific application business process.1 IntroductionDistributed transactions are essential for large-scale distributed applications like e-commerce, enterprise applications, and so on. However, distributed transactions are limited by their scalability, mainly due to sharing of data resources. When a transaction is updating a piece of data, other transactions are excluded from accessing the same data. Typically, the exclusion of access will last until the updating transaction terminates. In fact, nearly all commercial transaction processing systems and transaction processing standards use strict two-phase locking [8][11][15], i.e., locks acquired by a transaction are held until its termination. When transactions get long or involve many sites, they tend to hold data resources exclusively for long duration.However, holding data resources such long may be unnecessary. A lot of research has focused on how data updated by a transaction can be released early such that other transactions will not be unnecessarily blocked (many examples can be found in [6]). Releasing resources early, however, is not without problems. One difficult problem is that a transaction that releases its updated data might be aborted later. Concurrency control mechanisms that allow (somewhat) early release of data resources, like non-strict two-phase locking [3] and altruistic locking [13], suffer from the problem of cascading aborts. Moreover, non-strict two-phase locking requires notification of thestart of the shrinking phase, and is thus not particularly suitable in a distributed environment. Another commonly applied approach to remedy the inconsistency due to early release is the use of compensation [7]. Compensation is not a silver bullet, either. Some operations cannot be compensated. Even when all operations can be compensated, applications must provide compensation transactions, making the development of the application more complicated.We present a totally different approach to reducing blocking without incurring the problem of early release of data resources. More specifically, our approach • reduces unnecessary resource holding, and therefore increases systemconcurrency,• does not release data resources before transaction termination, and therefore does not lead to cascading aborts and does not require compensation, • ensures transaction response time at least as good as with strict two-phase locking, and• is likely to be supported by middleware without application involvement.This paper is organized as follows. Section 2 presents the intuition behind our approach. The key idea is to delay altruistically the execution of fast sub-transactions such that no sub-transaction finishes local processing unnecessarily earlier than other sub-transactions. Section 3 presents the execution model of distributed transactions for further discussions. Section 4 discusses how altruistic delays can be determined in the transaction execution model. Section 5 argues that altruistic delays can also be determined in a generalized transaction execution model. Section 6 discusses how to control altruistic delays in practice. Section 7 presents our plan for future research. Section 8 discusses some related work. Finally Section 9 summarizes the contributions of this work.2 Approach OverviewFigure 1 illustrates the timing of a typical execution of a transaction distributed at processes 1, 2, 3 and 4 as sub-transactions. The execution of each sub-transaction consists of the following stages:1. Start of the sub-transaction. A request is delivered to the process on behalf of thetransaction. The necessary initiation and enlistment is done at this stage.2. Acquisition of data resources. Locks are acquired on the data the sub-transactionis going to access.3. Data processing. The data on which the sub-transaction has acquired locks areread and updated.4. Unnecessary holding of data resources. After processing the data, the sub-transaction has to hold the locks until the termination of the transaction, i.e., until it is notified of the outcome of the transaction.5. Release of data resources. Finally the locks are released upon termination of thetransaction.As mentioned in the introduction, one major factor that limits the scalability of distributed transactions is stage 4 above. That is, sub-transactions have to hold data resources unnecessary after having accessed them. The duration of this unnecessaryholding can be long and is generally not decidable locally at the sites of the sub-transactions.In our approach, we introduce altruistic delays to the executions of sub-transactions. A sub-transaction acquires locks on data resources only after the altruistic delay. Ideally, by executing local data processing after the altruistic delays, the sub-transactions do not hold data resources unnecessarily (Figure 2). In practice, however, it is impossible to totally eliminate unnecessary holding of data resources. Our goal is therefore to minimize, or at least significantly reduce, unnecessary holding of data resources.issue in three steps:• We start with a primitive transaction execution model where the necessary timing of transaction invocation and execution is known. This execution modelis defined in Section 3. We will show in Section 4 that in this model altruistic delays of sub-transactions can be determined locally at their parent nodes.• Next, we will show in Section 5 that the result in the primitive transaction execution model applies also to a generalized execution model where the necessary timing is still known.• Our ultimate goal is to improve performance of distributed transaction processing in practice where the timing is generally unknown in advance. This will be our future work. In Section 6, we will discuss some possible approaches to achieving this goal.3 An execution model of distributed transactionsWe model execution of distributed transactions in a multi-tier client-server architecture, which typically consists of a presentation tier, a business process tier, a data access tier and a database tier. A transaction is typically started at a process of some tier, say near or at the presentation tier. A transaction at a process may invoke one or more sub-transactions at other processes, possibly at the next tier. Here a process is loosely defined as an address space. The only way for processes to share information is via message sending. Processes may run on different machines. The invocations of sub-transactions form a tree (transaction invocation tree). In the tree, the nodes are sub-transactions at different processes; an invoking process is the parent of the invoked processes; the root is the process where the transaction is started. A distributed transaction is terminated via an atomic commitment protocol, the most widely used of which is the two-phase commitment protocol. In an atomic commitment protocol, a process is also called a participant. Usually, the root of the transaction invocation tree is also the coordinator of the commitment protocol, and the voting and the decision notifications (commit or abort) are communicated between the participants and the coordinator through the invocation tree.The execution of a distributed transaction T is modeled as a tree:T = (N, E, exec, inv, res), where• N = {0, 1, 2, …, n} is the set of nodes and 0 is the root,• E⊆N×N is the set of edges,• exec: N→ Reals, is the time needed to execute sub-transactions locally at nodes,• inv: E→ Reals, is the time needed to invoke sub-transactions, and• res: E→ Reals, is the time needed to send replies.Figure 3 illustrates a transaction as a tree. Every node of the tree is a sub-transaction at a process. Suppose there is no re-entrant invocation at the same process by the same transaction. Thus node i denotes both process i and the sub-transaction at the process. Assume also that there is no message other than those for requests, replies and atomic commitment processing, so executions at different nodes are not synchronized beyond these. An edge from parent node i to child node j indicates an invocation from process i to process j. exec(i) is the time needed to execute sub-transaction locally at process i. inv(i, j) is the time needed to invoke from process i to process j. res(i, j) is the corresponding reply from j to i. Note usually inv(i, j) ≠res(i, j), because the management operations associated with invocations and replies are quite different.Associated with invocations are operations like authentication, authorization, transaction enlistment, initiation, etc., whereas with replies (implicit yes-votes, explained shortly in this sub-section), force-writing of prepare log records etc..For an intermediate node i , the local sub-transaction is executed in parallel with the child sub-transactions. Note that this does not exclude the cases where the local sub-transaction is executed before or after the child sub-transactions. In those case, the local execution time is included in inv (p ,i ) (the before case) or res (p ,i ) (the after case) where p is the parent of i , and exec (i ) is simply 0.The “non re-entrant invocation” assumption is not unrealistic. After all, distributed applications should be designed to avoid a component invocating the same remote component multiple times (see for example [2]). An exception can occur at the data access tier where a component invokes a database multiple times in the same transaction via the same database connection (stored procedures are a way of avoiding multiple invocations of this kind). In this case, we can model the entire data access tier as a single node and our non re-entrance assumption still holds. In Section 5, we will see that even the non re-entrance assumption is not necessary.In our transaction execution model, we assume strict two-phase locking and the two-phase commitment protocol [3], which are used in nearly all transaction processing products and standards. The root of the transaction tree is the coordinator of the two-phase commitment protocol. We assume the implicit yes-vote optimization of the two-phase commitment protocol [14], because it can be applied more directly in the subsequent discussions. A leaf node generates an implicit yes-vote right after its execution of all the local operations of the transaction. Note in our model there is no re-entrant invocation to the same process. In general, however, the last successful return from the requests of the same transaction is regarded as an implicit yes-vote. A non-leaf node generates an implicit yes-vote when it has received implicit yes-votes from all its children and when it has finished its local execution. So the implicit yes-votes are propagated from the child nodes to their parents and recursively upward to the root.Figure 3. Distributed transaction as a tree 0 exec (0)res (0,2) 1 exec (1)3 exec (3)4 exec (4)5 exec (5)6 exec (6)7 exec (7)8 exec (8) 2 exec (2) inv (1,3)inv (1,4) inv (0,1)inv (0,2) inv (2,5) inv (5,7) inv (5,6)inv (6,8)res (0,1)res (1,3)res (1,4) res (2,5) res (5,7) res (5,6)res (6,8)Ideally, every implicit yes-vote should arrive at the root at the same time, so no node is unnecessarily holding data resources while the root is waiting for the implicit yes-vote yet to be generated or delivered from some other node.4 Determining altruistic delaysFirst, we define the height h i of node i as the time interval between the process i receives a request and it is ready to reply with an implicit yes-vote:h i = max (exec(i), max(j is a child of i) (inv(i, j) + h j + res(i, j)))That is, after receiving the request, it concurrently starts local execution and sends requests to all subsequent processes. It is ready for replying with implicit yes-vote when it finishes local execution and receives implicit yes-votes from all child sub-transactions.Ideally for every non-leaf node, i, the implicit yes-votes from all its children arrive exactly at the moment the local execution finishes. The delay d(j) of its child j and delay of its own local execution d_local(i) can be assigned such thatinv(i, j) + d(j) + h j + res(i, j) = d_local(i) + exec(i) = h iNote that the altruistic delay at node, i, consists of two parts:• d(i), delay all activities, including local execution and invocations to the children, and• d_local(i), delay of local execution in addition to d(i).Now the altruistic delays of all nodes can be obtained, starting from the root.main(){d[0] ß 0;assign_delay_for_children(0);}assign_delay_for_children(i){d_local[i] = h i – exec[i];if “there is no child”return;for every child j{d[j] ß h i – (inv[i,j] + h j + res[i,j]);assign_delay_for_children(j);}}Figure 4 shows the executions of the distributed transaction in Figure 3, with and without altruistic delays, given some hypothetical values of inv(), exec(), and res(). Notice that no altruistic delay is introduces at node 8, due to the slowest path 0à2à5à6à8. At all other nodes (with the exception of node 2), the time lengths for resource blocking are significantly reduced with the introduction of altruistic delays. At node 2, exec(2) is 0, whereas inv(1,2) is quite long, a case in which local sub-transactionis executed before the child sub-transactions. Like at other nodes, at node 2, locks acquired during local execution must be held until the termination of the entire distributed transaction.5 Generalization of the execution modelOur transaction execution model presented in Section 3 can be generalized. In the generalized model, a node can be re-entrant and the execution of some children may be dependent on the execution of some other children of the same parent.In Figure 5, execution of a consists of a 1, a 2, a 3 and a 4. Execution of b is independent of its parent a and other children of a . Execution of c is dependent on a 1. Execution of d is dependent on both a 2 (which is dependent on c ) and sibling c . a is re-entrant with a 3 executing the invocation from d . Finally, the execution a 4 is dependent on the execution of d .1342568713425687Figure 4. Executions with and without altruistic delaysFigure 5. Node in the generalized execution modelExecution dependencies among child transactions introduce some complexity in determining the altruistic delays. For example, delaying at c will postpone the execution of d, which will incur even more unnecessary delay of the entire transaction. One way to model this is to regard the entire A = (a1àcàa2àd1àa3àd2àa4) as a single sequential execution in parallel with b. Altruistic delays of b and A are thus decidable at a using the algorithm in Section 4.In essence, altruistic delays should only be considered at the forks of concurrent execution branches. Sequential executions, albeit distributed over different nodes, will not benefit from the introduction of altruistic delays.6 Controlling altruistic delays in practiceIn reality, local execution time and message delays are non-deterministic and unknown in advance. Non-determinism is a combined effect of factors like workload variation, race conditions, run-time resource scheduling, network protocol queue lengths, paging, caching, query spaces, program branching, etc. Controlling any of these factors is a major issue of research in areas like QoS management.We propose here two possible approaches to control altruistic delays in practice: • Control based on static analysis. Here timing of different components is obtained based on a white-box analysis of the application. This approach is particularly suitable for tuning benchmarks or applications whose business process structure is pretty static.• Control based on dynamic analysis. Here altruistic delays are dynamically determined based on analysis on statistics of previous executions of transactions.This can be done either by the application or by the middleware.Next, we briefly discuss these different approaches.6.1 Control based on static analysisIn this approach, the application execution without altruistic delay is first profiled. Profiling at components that create concurrent sub-transactions is particularly important, because as shown in Section 4, altruistic delays can be determined locally at parent nodes. If the differences of response time of sub-transactions are stable and considerable, the slowest sub-transaction is the basis for determining the altruistic delays of the other sibling sub-transactions. Care must be taken of whether the slowest sub-transaction is dependent on some other sibling sub-transaction (as in the generalized execution model).6.2 Control based on dynamic analysisThis approach can be implemented either directly by the application or by the supporting middleware.Implementation by the application is similar to the approach based on static analysis. Statistics on response time is taken at components that create concurrent sub-transactions. Again, if the differences of response time of sub-transactions are stable and considerable, executions of sub-transactions are aligned with the slowest sub-transaction.Ultimately, control of altruistic delays should be supported by middleware, whose main task is to support large-scale distributed applications.Basically, analysis can be done by interceptors on a per remote invocation basis. In transactional component middleware such as EJB and COM+, the run-time such as a container intercepts every incoming and outgoing request.For example, the middleware run-time records in the thread-specific transaction contexts (such as the context objects in COM+) the timestamp of the sending of every request and the reception of every reply. In this way, the recording is thread-specific and need not be synchronized with other threads. The recorded data is flushed to a shared data structure during component life-cycle operations (such as returning to object pool, deactivation etc.). A low-priority thread periodically reads the shared data structure and adjusts altruistic delays using certain forecasting methods.One of the difficulties with middleware support is the lack of knowledge of the structure of application business process. Particularly useful is the knowledge of execution dependencies. Hopefully, detailed statistic analysis will uncover the dependencies. For example, a clear indication of some dependency between two child sub-transactions of the same parent is that a request message to one child is always sent after the parent receives a reply from the other child. This is one of the issues we will work on in the future.7 Future WorkWe are now evaluating the benefits of our approach with static analysis of some typical distributed applications.Our ultimate goal is middleware support for altruistic delays of distributed transactions in large-scale applications. This work is part of the Arctic Beans project [1]. The primary aim of Arctic Beans is to provide a more open and flexible enterprise component technology, with intrinsic support for configurability, re-configurability and evolution, based on the principle of reflection [4]. Enterprise components arecomponents at server sites running within so called containers which provide support for complicated mechanisms like resource management (threads, memory, sessions etc.), security and transactions. The project focuses on the security and transaction services and how to adapt these services according to the application needs and its environment. We believe a container is the right place to support control of altruistic delays.We will also study if altruistic delays can be applied in adaptive applications. For example, if one sub-transaction is often dominantly long, due to weak connections or even occasional disconnections, executions of other sub-transactions should be aligned with this long sub-transaction.8 Related WorkMost researches that aim at reducing unnecessary resource holding is based on early release of data resources. The key problem is to maintain database consistency when the transaction that has already released some of its updates finally aborts.With non-strict two-phase locking, locks can be released during the shrinking phase [3]. Altruistic locking allows even earlier release of locks if more knowledge of the data access patterns is available [13]. Serializability of transaction executions is ensured. The well-known problem with these approaches is cascading aborts, which can be even more costly to deal with than unnecessary resource holding, particularly in large-scale systems. They are generally unsuitable for distributed transactions because of the extra notification, such as of the termination of the expanding phase, required among involved sites. Moreover, independence of data accesses among different sites is not fully explored.With the use of compensation [7], the early released effects of a transaction can be logically undone if the transaction finally aborts. One problem with this approach is that not every operation is compensatable. Some compensatable operations still have some effects on end-users, such as charge of cancellation (of reservations) fee. In general, implementing a compensation transaction for every (sub-) transaction is not an easy task.With dynamic re-structuring [9], a long transaction can be split into multiple smaller ones. Some of them can commit early. There may or may not be cascading aborts, depending on the dependencies among the new split transactions. Again, detailed knowledge of application business process is required.Both compensation and dynamic re-structuring can be used to deal with transactions with long sequential executions, whereas our approach cannot. All these methods can be used jointly in particular applications.We use the implicit yes-vote optimization [14] of the two-phase commitment protocol to reason about our approach. There are several improvements to the implicit yes-vote optimization (some of them can be found in [5]). One noticeable improvement is called the dynamic two-phase commitment protocol (D2PC) [12]. Actually, D2PC is not limited to implicit yes-votes, though the gain of D2PC in implicit yes-votes is more significant because of the difference in time yes-votes are generated. The basic idea is that propagation of yes-votes does not stop at the root of the tree while some slow sub-transaction is still busy processing. The propagation will go on toward the slowest node (which will become the new coordinator). With D2PC, the total response time is improved, therefore also entire system concurrency. While D2PC focuses on“smoothing out” the effect of the slowest sub-transaction during commitment processing, we consider the combined effect of execution and message delays. With D2PC, when one sub-transaction is considerably longer than the others (say all other yes-votes have already “piled up” at this slowest node), the others still have to hold data resources unnecessarily (possibly considerably long). There is also an additional cost associated with transfer of coordinator in D2PC. It would be interesting to compare quantitatively the D2PC with our approach.As a final remark, the problem our work seeks to address is different from that of scheduling workflow tasks on a set of resources (such as the job-shop scheduling [9]), where the set of workflows with (more complex) inter-task dependencies is known in advance. The goal with task scheduling is either to minimize total execution time of workflows or to meet deadlines of workflows. In our work, although the inter-transaction dependencies could be simple, the total set of transactions is not known in advance. Nor is our goal to meet deadlines or to minimize total execution time.9 ConclusionOne major factor that limits the scalability of distributed transactions is that all sub-transactions have to hold data resources until the slowest sub-transaction finishes. Holding of data resources this long can be unnecessary, because some sub-transaction may have already finished processing its local data. In contrast with the approaches that release data resources before the termination of the entire distributed transaction, we introduce altruistic delays to the executions of sub-transactions. We show in transaction execution models where the necessary timing is known in advance, with the introduction of proper altruistic delays, no sub-transaction holds data resources unnecessarily after local processing. Furthermore, we show some nice properties of our approach: concurrency of the system is enhanced without sacrificing transaction response time; altruistic delays can be determined locally at parent sub-transactions. We also discussed how altruistic delays could be controlled in practice. It seems that altruistic delays can be supported by middleware without specific knowledge about application business structure. How this can be realized will be part of our future research work.10 References[1] Anders A., G. S. Blair, V. Goebel, R. Karlsen, T. Stabell-Kulø and W. Yu, “Arctic Beans:Configurable and Reconfigurable Enterprise Component Architectures”, Middleware 2001 Work-in-Progress paper, IEEE Distributed Systems Online, 2(7), On-line at: /0107/features/and0107.htm, 2001.[2] Alur, D., J. Crupi and D. Malks, Core J2EE Patterns, Best Practice and DesignStrategies, Upper Saddle River, NJ: Printice Hall PTR, 2001.[3] Bernstein, P. A., V. Hadzilacos and N. Goodman, Concurrency Control andRecovery in Database Systems, Reading, MA: Addison-Wesley, 1987.[4] Blair, G., G. Coulson, P. Robin and M. Papathomas, “An Architecture for NextGeneration Middleware”, In Proceedings of Middleware '98, 1998.[5] Chrysanthis, P. K., G. Samaras and Y. J. Al-Houmaily, “Recovery and Performanceof Atomic Commit Processing in Distributed Database Systems”, In Kumar V. and M. Hsu (Eds.), Recovery Mechanisms in Database Systems. Upper Saddle River, NJ: Printice Hall, pp. 370-416, 1998.[6] Elmagarmid, A. (ed.), Database Transaction Models for Advanced Applications,Morgan Kaufman Publishers, 1992.[7] Garcia-Molina, H. and K. Salem, “SAGAS”, In Proceedings of the ACM SIGMODInternational Conference on Management of Data, 1987.[8] Gray, J. and A. Reuter, Transaction Processing: Concepts and Techniques, MorganKaufman Publishers, 1993.[9] Jain, A. S., and S. Meeran “Deterministic Job Shop Scheduling: Past, Present,Future”, European Journal of Operation Research, Elsevier Science, Vol 113, pp 390-434, 1999.[10] Kaiser, G. E., C. Pu, “Dynamic Restructuring of Transactions”, In [6], pp. 265-295,1992.[11] Object Management Group, CORBA Services Specification, Chapter 10,Transaction Service Specification, December, 1998.[12] Raz, Y., “The Dynamic Two Phase Commitment (D2PC) Protocol”, In Gottlob G.and M. Y. Vardi (Eds.), Proceedings of 5th International Conference on Database Theory, LNCS 893, Springer, 1995[13] Salem, K., H. Garcia-Molina and J. Shands, “Altruistic Locking”, ACMTransactions on Database Systems, 19(1), pp. 117-165, 1994.[14] Stonebraker, M., “Concurrency Control and Consistency of Multiple Copies ofData in Distributed INGRES”, IEEE Transactions on Software Engineering, 5(3), pp 188-194, 1979.[15] X/Open Company Ltd., Distributed Transaction Processing: The XA Specification.Document number XO/CAE/91/300, 1991.。

美国伦布科技 Agilent 16800 Series Portable Logic Analyze

Agilent 16800 SeriesPortable Logic AnalyzersData SheetQuickly debug, validate,and optimize your digitalsystem – at a price thatfits your budget.Features and benefits•250 ps resolution (4 GHz) timingzoom to find elusive timing problemsquickly, without double probing•15” display, with available touchscreen, allows you to see more dataand navigate quicklymeasurements and displays of yourlogic analyzer and oscilloscope datalet you effectively track downproblems across the analog anddigital portions of your design•Eight models with34/68/102/136/204 channels,up to 32M memory depth andmodels with a pattern generatorprovide the measurement flexibilityfor any budget•Application support for every aspectof today’s complex designs – FPGAdynamic probe, digital VSA (vectorsignal analysis) and broad processorand bus support2Selection Guide for 16800 Series Portable Logic AnalyzersModels with a built-in pattern generator give you more measurement flexibility1Pattern generator available with 16821A, 16822A and 16823A.Choose from eight models to get the measurement capability for your specific applicationProbes are ordered separately. Please specify probes when ordering to ensure the correct connection between your logic analyzer, pattern generator, and the device under test.Agilent 16800 Series portable logic analyzers offer the performance, applications, and usability your digital development team needs to quickly debug, validate, and optimize your digital system – at a price that fits your budget.The logic analyzer’s timing and state acquisition gives you the power to:•Accurately measure precise timing relationships using4GHz (250ps) timing zoomwith 64K depth•Find anomalies separated in time with memory depthsupgradeable to 32M•Buy what you need today and upgrade in the future. 16800Series logic analyzers comewith independent upgrades for memory depth and state speed •Sample synchronous buses accurately and confidentlyusing eye finder. Eye finderautomatically adjuststhreshold and setup andhold to give you the highestconfidence in measurementson high-speed buses•Track problems from symptom to root cause across severalmeasurement modes byviewing time-correlated datain waveform/chart, listing,inverse assembly, source code, or compare display •Set up triggers quickly andconfidently with intuitive,simple, quick, and advancedtriggering. This capabilitycombines new triggerfunctionality with an intuitiveuser interface•Access the signals that holdthe key to your system’sproblems with the industry’swidest range of probingaccessories with capacitiveloading down to 0.7 pF•Monitor and correlate multiplebuses with split analyzercapability, which providessingle and multi-bus support(timing, state, timing/state orstate/state configurations)Accurately measure precisetiming relationships16800 Series logic analyzers letyou make accurate high-speedtiming measurements with 4GHz(250ps) high-speed timing zoom. Aparallel acquisition architectureprovides high-speed timingmeasurements simultaneouslythrough the same probe used forstate or timing measurements.Timing zoom stays active all thetime with no tradeoffs. View dataat high resolution over longerperiods of time with 64-K-deeptiming zoom.Figure 1. With eight models to choose from, you can get alogic analyzer with measurement capabilities that meetyour needs.3Automate measurement setup and quickly gain diagnostic clues16800 Series logic analyzers make it easy for you to get up and running quickly by automating your measurement setup process. In addition, the logic analyzer’s setup/hold window (or sampling position) and threshold voltage settings are automatically determined so you can capture data on high-speed buses with the highest accuracy. Auto Threshold and Sample Position mode allow you to...•Obtain accurate and reliable measurements•Save time during measurement setup•Gain diagnostic clues and identify problem signalsquickly•Scan all signals and buses simultaneously or just a few•View results as a composite display or as individual signals•See skew between signals and buses•Find and fix inappropriate clock thresholds•Measure data valid windows•Identify signal integrityproblems related to rise times,fall times, data valid windowwidths Identify problem signals overhundreds of channels simultaneouslyAs timing and voltage marginscontinue to shrink, confidencein signal integrity becomes anincreasingly vital requirementin the design validation process.Eye scan lets you acquire signalintegrity information on allthe buses in your design, undera wide variety of operatingconditions, in a matter ofminutes. Identify problem signalsquickly for further investigationwith an oscilloscope. Results canbe viewed for each individualsignal or as a composite ofmultiple signals or buses.Extend the life of your equipmentEasily upgrade your 16800 Serieslogic analyzer. “Turn on”additional memory depth andstate speed when you need more.Purchase the capability youneed now, then upgrade as yourneeds evolve.Figure 2. Identify problem signals quickly by viewing eye diagrams across all buses and signals simultaneously.4578910A Built-in Pattern Generator Gives You Digital Stimulus and Responsein a Single InstrumentSelected 16800 Series models (16821A, 16822A and 16823A)also include a 48-channel pattern generator to drive down risk early in product development. With a pattern generator you can:•Substitute for missing boards,integrated circuits (ICs) or buses instead of waiting for missing pieces •Write software to createinfrequently encountered test conditions and verify that the code works – before complete hardware is available •Generate patterns necessary to put a circuit in a desired state,operate the circuit at full speed or step the circuit through a series of states •Create a circuit initialization sequence Agilent 16800 Series portable logic analyzers with a pattern generator offer a variety offeatures that make it easier for you to create digital stimulus tests.Vectors up to 48 bits wideVectors are defined as a “row” of labeled data values, with each data value from one to 48 bits wide. Each vector is output on the rising edge of the clock.Create stimulus patterns for the widest buses in your system.Depth up to 16 M vectorsWith the pattern generator, you can load and run up to 16Mvectors of stimulus. Depth on this scale is most useful when coupled with powerful stimulus generated by electronic design automation tools, such as SynaptiCAD’sWaveFormer and VeriLogger.These tools create stimulus using a combination of graphicallydrawn signals, timing parameters that constrain edges, clock signals,and timing and Boolean equations for describing complex signal behavior. The stimulus also can be created from design simulation waveforms. The SynaptiCAD tools allow you to convert .VCD files into .PGB files directly, offering you an integrated solution that saves you time.Synchronized clock outputYou can output data synchronized to either an internal or external clock. The external clock is input via a clock pod, and has nominimum frequency (other than a 2ns minimum high time).The internal clock is selectable between 1MHz and 300MHz in 1-MHz steps. A Clock Out signal is available from the clock pod and can be used as an edge strobe with a variable delay of up to 8ns.Initialize (INIT) block for repetitive runsWhen running repetitively, the vectors in the initialize (init)sequence are output only once,while the main sequence isoutput as a continually repeating sequence. This “init” sequence is very useful when the circuit or subsystem needs to be initialized.The repetitive run capability is especially helpful whenoperating the pattern generator independent of the logic analyzer.“Send Arm out to…” coordinates activity with the logic analyzerVerify how your system responds to a specific stimulus sequence by arming the logic analyzer from the pattern generator. A “Send Arm out to…” instruction acts as a trigger arming event for the logic analyzer or other test equipment to begin measurements. Arm setup and trigger setup of the logic analyzer determines the action initiated by “Send Arm out to…”.Figure 3. Models with a built-in pattern generator give you more measurement flexibility.“Wait for External Event…” forinput patternThe clock pod also accepts a 3-bit input pattern. These inputs are level-sensed so that any number of “Wait for External Event”instructions can be inserted into a stimulus program. Up to four pattern conditions can be defined from the OR-ing of the eight possible 3-bit input patterns. A “Wait for External Event” also can be defined to wait for an Arm. This Arm signal can come from the logic analyzer. “Wait for External Event…” allows you to executea specific stimulus sequence only when the defined external event occurs.Simplify creation of stimulus programs with user-defined macros and loops User macros permit you to define a pattern sequence once, then insert the macro by name wherever it is needed. Passing parameters to the macro will allow you to create a more generic macro. For each call to the macro you can specify unique values for the parameters.Loops enable you to repeat a defined block of vectors for a specified number of times. Loops and macros can be nested, except that a macro cannot be nested within another macro. At compile time, loops and macros are expanded in memory to alinear sequence.Convenient data entry andediting featureYou can conveniently enterpatterns in hex, octal, binary,decimal, and signed decimal(two’s complement) bases. Tosimplify data entry, you can viewthe data associated with anindividual label with multipleradixes. Delete, Insert, and Copycommands are provided for easyediting. Fast and convenientPattern Fills give the programmeruseful test patterns with a fewkey strokes. Fixed, Count, Rotate,Toggle, and Random patterns areavailable to help you quicklycreate a test pattern, suchas “walking ones.” Patternparameters, such as step size andrepeat frequency, can be specifiedin the pattern setup.ASCII input file format: your designtool connectionThe pattern generator supportsan ASCII file format to facilitateconnectivity to other tools in yourdesign environment. Because theASCII format does not support theinstructions listed earlier, theycannot be edited into the ASCIIfile. User macros and loops alsoare not supported, so the vectorsneed to be fully expanded in theASCII file. Many design tools willgenerate ASCII files and outputthe vectors in this linear sequence.Data must be in hex format, andeach label must represent a set ofcontiguous output channels.ConfigurationThe pattern generator operateswith the clock pods, data pods,and lead sets described later inthis document. At least one clockpod and one data pod must beselected to configure a functionalsystem. You can select from avariety of pods to provide thesignal source needed for your logicdevices. The data pods, clock podsand data cables use standardconnectors. The electricalcharacteristics of the data cablesare described for users withspecialized applications who wantto avoid the use of a data pod.Direct connection to yourtarget systemYou can connect the patterngenerator pods directly to astandard connector on your targetsystem. Use a 3M brand #2520Series or similar connector. Theclock or data pods will plug rightin. Short, flat cable jumpers canbe used if the clearance aroundthe connector is limited. Use a 3M#3365/20, or equivalent, ribboncable; a 3M #4620 Series orequivalent connector on thepattern generator pod end of thecable, and a 3M #3421 Series orequivalent connector at yourtarget system end of the cable.Probing accessoriesThe probe tips of theAgilent10474A, 10347A, 10498A,and E8142A lead sets plugdirectly into any 0.1-inch gridwith 0.026-inch to 0.033-inchdiameter round pins or 0.025-inchsquare pins. These probe tipswork with the Agilent5090-4356surface mount grabbers andwith the Agilent5959-0288through-hole grabbers, providingcompatibility with industrystandard pins.A Built-in Pattern Generator Gives You Digital Stimulus and Response in a Single Instrument3-STATE IN TTLPattern generator cable pin outsData cable (Pod end)Clock cable (Pod end)2122Unleash the Complementary Power of a Logic Analyzer and an Oscilloscope Seamless scope integrationwith View ScopeEasily make time-correlatedmeasurements between Agilentlogic analyzers and oscilloscopes.The time-correlated logic analyzerand oscilloscope waveforms areintegrated into a single logicanalyzer waveform display foreasy viewing and analysis. Youcan also trigger the oscilloscopefrom the logic analyzer (or viceversa), automatically de-skew thewaveforms and maintain markertracking between the twoinstruments. Perform thefollowing more effectively:•Validate signal integrity•Track down problems caused by signal integrity•Validate correct operation of A/D and D/A converters •Validate correct logical and timing relationships betweenthe analog and digital portions of a designConnectionThe Agilent logic analyzer and oscilloscope can be physically connected with standard BNC and LAN connections. Two BNC cables are connected for cross triggering, and the LAN connection is used to transfer data between the instruments. The View Scope correlation software is standard in the logic analyzer’s application software version 3.50 or higher. The View Scope software includes:•Ability to import some or all of the captured oscilloscopewaveforms•Auto scaling of the scopewaveforms for the best fit inthe logic analyzer displayFigure 4. View Scope seamlessly integrates your scopeand logic analyzer waveforms into a single display.2324Acquisition and analysis tools provide rapid insight into your toughest debug problemsYou have unique measurement and analysis needs. When you want to understand what your target is doing and why, you need acquisition and analysis tools that rapidly consolidate data into displays that provide insight into your system’s behavior.Figure 5. Perform in-depth time, frequency and modulation domain analysis on your digital baseband and IF signals with Agilent’s 89600 Vector Signal Analysis software.Save time analyzing your unique design with a turnkey setup Agilent Technologies and our partners provide an extensive range of bus and processor analysis probes. They provide non-intrusive, full-speed,real-time analysis to accelerate your debugging process.•Save time making bus-and processor-specificmeasurements withapplication specific analysisprobes that quickly andreliably connect to yourdevice under test•Display processor mnemonicsor bus cycle decode•Get support for acomprehensive list ofindustry-standard processorsand buses252627ProgrammabilityYou can write programs to control the logic analyzer application from remote computers on the local area network using COM or ASCII. The COM automation serveris part of the logic analyzer application. This software allows you to write programs to control the logic analyzer. All measurement functionality is controllable via the COM interface.The B4608A Remote ProgrammingInterface (RPI) lets you remotelycontrol a 16800 Series logicanalyzer by issuing ASCIIcommands to the TCP socketon port 6500. This interface isdesigned to be as similar aspossible to the RPI on 16700Series logic analysis systems,so that you can reuse existingprograms.The remote programminginterface works through the COMautomation objects, methods,and properties provided forcontrolling the logic analyzerapplication. RPI commands areimplemented as Visual Basicmodules that execute COMautomation commands, translatetheir results, and return propervalues for the RPI. You can use theB4606A advanced customizationenvironment to customize andadd RPI commands.Figure 6. 16800 Series programming overview2816800 Series Interfaces2930Figure 9. 16800 Series back panelFull profile PCI card expansion slotExternal display portParallel portSerial port10/100 Base T LAN 2.0 USB ports (4)Clock inTrigger out Trigger in Keyboard Mouse AC power Figure 8. 16800 Series front panelOn/Off power switch 15 inch built-in color LCD display, Touch Screen available General purpose knob Run/stop keys Touch screen on/off (if ordered)16800 Series Physical CharacteristicsDimensionsPower 16801A 115/230 V, 48-66 Hz, 605 W max 16802A 115/230 V, 48-66 Hz, 605 W max 16803A 115/230 V, 48-66 Hz, 605 W max 16804A 115/230 V, 48-66 Hz, 775 W max 16806A 115/230 V, 48-66 Hz, 775 W max 16821A 115/230 V, 48-66 Hz, 775 W max 16822A 115/230 V, 48-66 Hz, 775 W max 16823A 115/230 V, 48-66 Hz, 775 W max Weight Max net Max shipping 16801A 12.9 kg 19.7 kg (28.5 lbs)(43.5 lbs)16802A 13.2 kg 19.9 kg (28.9 lbs)(43.9 lbs)16803A 13.7 kg 20.5 kg (30.3 lbs)(45.3 lbs)16804A 14.2 kg 21.0 kg (31.3 lbs)(46.3 lbs)16806A 14.6 kg 21.4 kg (32.1 lbs)(47.1 lbs)16821A 14.2 kg 20.9 kg (31.2 lbs)(46.2 lbs)16822A 14.2 kg 21.1 kg (31.6 lbs)(46.6 lbs)16823A14.5 kg 21.3 kg (32.0 lbs)(47.0 lbs)Instrument operating environment Temperature 0˚ C to 50˚ C (32˚ F to 122˚ F)Altitude To 3000 m (10,000 ft)Humidity8 to 80% relative humidity at 40˚ C (104˚ F)Figure 7. 16800 Series exterior dimensionsFigure 10. 16800 Series side view330.32(13.005)Dimensions: mm (inches)28.822(11.347)443.23(17.450)Agilent 1184A TestmobileThe Agilent 1184A testmobile gives you a convenient means of organizing and transporting your logic analyzer and accessories.The testmobile includes the following:•Drawer for accessories(probes, cables, power cords)•Keyboard tray with adjustable tilt and height•Mouse extension on keyboard tray for either right or lefthand operation•on uneven surfaces••Load limits:Total: 136.4 kg (300.0 lb.)Figure 11. Agilent 1184A testmobile cartFigure 12. Agilent 1184A testmobile cart dimensions3132Stationary shelfThis light-duty fixed shelf isdesigned to support 16800 Series logic analyzers. The shelf can be used in all standard Agilent racks. The stationary shelf is mounted securely into placeusing the supplied hardware and is designed to sit at the bottom of the EIA increment. Features of the stationary shelf include:•Snap-in design for easy installation •Smooth edgesRack accessoriesSliding shelfThe sliding shelf provides a flat surface with full product accessibility. It can be used in all Agilent racks to support 16800Series logic analyzers. The shelf and slides are preassembled for easy installation. Features of the sliding shelf include:•Snap-in design for easy installation •Smooth edgesConsider purchasing the steel ballast (C2790AC) to use with the sliding shelf. The ballast provides anti-tip capability when the shelf is extended.Figure 15. Sliding shelf (J1526AC)Figure 14. Stationary shelf (J1520AC)Figure 13. Sliding shelf installed in rackEach 16800 Series portable logicanalyzer comes with one PS/2keyboard, one PS/2 mouse,accessory pouch, power cord and1-year warranty standard.Selecting a logic analyzer to meet your application and budget is as easy as 1, 2, 3333435。

synopsys iC Compiler II 数据手册说明书

DATASHEETOverview IC Compiler™ II is the industry leading place and route solution that delivers best-in-class quality-of-results (QoR) for next-generation designs across all market verticals and process technologies while enabling unprecedented productivity. IC Compiler II includes innovative for flat and hierarchical design planning, early design exploration, congestion aware placement and optimization, clock tree synthesis, advanced node routing convergence, manufacturing compliance, and signoff closure.IC Compiler II is specifically architected to address aggressive performance, power, area (PPA), and time-to-market pressures of leading-edge designs. Key technologies include a pervasively parallel optimization framework, multi-objective global placement, routing driven placement optimization, full flow Arc based concurrent clock and data optimization, total power optimization, multi-pattern and FinFET aware flow and machine learning (ML) driven optimization for fast and predictive design closure. Advanced Fusion technologies offer signoff IR drop driven optimization, PrimeTime ® delay calculation within IC Compiler II, exhaustive path-based analysis (PBA) and signoff ECO within place and route for unmatched QoR and design convergence. F U S I O N D E S I G N P L A T F O R M PrimeTime, StarRC, PrimePower,IC Validator, RedHawk Analysis Fusion Fusion Compiler IC Compiler II Design Compiler NXT TestMAX F o r m a l i t y ECO Fusion S i g n o f f F u s i o n S i g n o f f F u s i o n Test Fusion Figure 1: IC Compiler II Anchor in Synopsys Design PlatformAccelerating DesignClosure on AdvancedDesignsIC Compiler II Industry Leading Place and Route SystemKey BenefitsProductivity• The highest capacity solution that supports 500M+ instances with a scalable and compact data model• A full suite of design planning features including transparent hierarchical optimization• Out-of-the-box simple reference methodology for easy setup• Multi-threaded and distributed computing for all major flow steps• Golden signoff accuracy with direct access to PrimeTime delay calculationPPA• Unified TNS driven optimization framework• Congestion, timing, and power-driven logic re-synthesis• IEEE 1801 UPF/multi-voltage support• Arc-based concurrent clock and data optimization• Global minima driven total power optimizationAdvanced Nodes• Multi-pattern and FinFET aware design flow• Next generation advanced 2D placement and legalization• Routing layer driven optimization, auto NDR, and via pillar optimization• Machine learning driven congestion prediction and DRC closure• Highest level of foundry support and certification for advanced process nodes• IC Validator in the loop signoff driven DRC validation and fixingAdvanced Fusion Technology• Physically aware logic re-synthesis• IR drop driven optimization during all major flow steps• PrimeTime delay calculation based routing optimization for golden accuracy• Integrated PrimeTime ECO flow during routing optimization for fastest turnaround timeEmpowering Design Across Diversified ApplicationsThe dizzying pace of innovation and highly diversified applications across the design spectrum is forcing a complete rethink of the place and route systems to design and implement differentiated designs in a highly competitive semiconductor market on schedule. Designers on emerging process nodes must meet aggressive PPA and productivity goals. It essentially means efficient and intelligent handling of 100s of millions of place-able instances, multiple levels of hierarchy, 1000s of hard macros, 100s of clocks, wide busses, and 10s of modes and corners power domains and complex design constraints and process technology mandates. Emphasis on Designer ProductivityIC Compiler II is architected from the ground up for speed and scalability. Its hierarchical data model consumes 2-3X less memory than conventional tools, boosting the limits of capacity to 500M placeable instances and beyond. Adaptive abstraction and on-the-fly data management minimize memory requirements and enable fast responsive data manipulation. Near-linear multi-core threading of key infrastructural components and core algorithms such as database access and timing analysis speed up optimization at all phases of design. Patented, lossless compact modeling and independent R and C extraction allow handling more modes and corners (MCMM scenarios) with minimal runtime impact.IC Compiler II has built-in Reference Methodology(RM) that ensures fast flow bring up. This RM Flow is Foundry Process/Design Type specific to ensure a robust starting point and seamless bring up. IC Compiler II has direct access to the Golden PrimeTime delay calculation engine to minimize ECO iterations.IC Compiler II’s new data model enables designers to perform fast exploration and floorplanning with complex layout requirements. IC Compiler II can create bus structures, handle designs with n-levels of physical hierarchy, and support Multiply Instantiated Blocks (MIBs) in addition to global route driven pin assignment/feedthrough flow, timing driven macro placement, MV area design planning.A design data mismatch inferencing engine analyzes the quality of inputs and drives construct creation on the fly, delivering design insights even with “incomplete” data early in the design cycle. Concurrent traversal of logical and physical data models enables hierarchical Data-Flow Analysis (DFA) and fast interactive analysis through multi-level design hierarchies and MIBs. Data flow and feedthrough paths highlighted in Figure 2 allow analysis and manipulation through n-levels of hierarchy to complete early design exploration and prototyping.Figure 2: Fast interactive analysis through multiple-levels of physical hierarchy and MIBPipeline-register-planning shown in Figure 3, provides guidance for optimal placement to meet the stringent timing requirementsof high-performance designs. Interactive route editor integrated which is advanced node aware shown in Figure 4, allows intricate editing and routing functions, including the creation of special signal routes, buses, etc.Figure 3: Pipeline register placement enables superior QoR for designs with complex busesAchieving Best Performance, Power, Area, and TATIC Compiler II features a new optimization framework built on global analytics. This Unified TNS Driven Optimization framework is shared with Design Compiler NXT synthesis to enable physically-aware synthesis, layer assignment, and route-based optimization for improved PPA and TAT. Multi-Corner Multi-Mode (MCMM) and Multi-Voltage (MV) aware, level-based analytical algorithms continuously optimize using parallel heuristic algorithms. Multi-factor costing functions deliver faster results on both broad and targeted design goals. Concurrent PPA driven logic remapping, rewiring, and legalization interleaved with placement minimizes congested logic, resulting in simple localized logic cones that maximize routability and QoR.IC Compiler II minimizes leakage with fast and efficient cell-by-cell power selection across HVT, SVT and LVT cells and varying channel lengths. Activity-driven power optimization uses VCD/ SAIF, net toggle rates, or probability functions to drive placement decisions and minimize pin capacitances. Multi-bit register banking optimizes clock tree structures, reduces area, and net length, while automatically managing clock, data, and scan chain connections.Advanced modeling of congestion across all layers highlighted in Figure 4 provides accurate feedback throughput the flow from design planning to post- route optimization.Figure 4: Intelligent and accurate analysis for congestion and powerIC Compiler II introduces a new Concurrent Clock and Data (CCD) analysis and optimization engine that is built-in to every flow step resulting in meeting both aggressive performance and minimizing total power footprint. ARC-based CCD optimization performs clock tree traversal across all modes/corners in path-based fashion to ensure optimal delay budgeting.Robust support for clock distribution enables virtually any clock style, including mesh, multi-source, or H-tree topologies. Advanced analysis and debugging features perform accurate clock QoR analysis and debugging as highlighted in Figure 5.Figure 5: Accurate clock QoR analysis and debugging (a & b) Abstracted clock graph and schematic.(c) Latency clock graph. (d) Colored clock tree in layout.IC Compiler II features many innovative technologies that make it the ideal choice for high-performance, energy-efficient Arm®processor core implementation, resulting in industry-best milliwatts/megahertz (mW/MHz) for mobile and other applications across the board. Synopsys and Arm work closely together to offer optimized implementation of popular Arm cores for IC Compiler II,with reference flows available for Arm Cortex®-A high-performance processors and Mali GPUs. In addition, Arm offers off-the-shelf Artisan® standard cell and memory models that have been optimally tuned and tested for fast deployment in an IC Compiler II environment. Continuous technology innovation and close collaboration makes IC Compiler II the leading choice for Arm-based high- performance design.Highest Level of Advanced Node Certification and SupportIC Compiler II provides advanced node design enablement across major foundries and technology nodes—including 16/14nm,12/10nm, 7/5nm, and sub-5nm geometries. Zroute digital router technology ensures early and full compliance with the latest design rules required for these advanced node technologies. Synopsys collaborates closely with all the leading foundries to ensure that IC Compiler II is the first to deliver support for early prototype design rules and support for the final production design rules. IC Compiler II design technologies maximize the benefits of new process technologies and offer optimal return on investment for cutting-edge silicon applications.IC Compiler II advanced node design support includes multi-pattern/FinFET aware placement and routing, Next-generation advanced 2D placement and legalization, routing layer driven optimization, auto NDR, and via pillar optimization. IC Validator in the loop provides signoff DRC feedback during Implementation.Foundry ﬁll Track based ﬁllFigure 6: IC Validator In-Design metal fill color aware metal fill, optimized for density and foundry requirementsMachine learning driven congestion prediction and DRC closure allow for fastest routing convergence with best PPA. Multiple sets of training data are used to extract key predictive elements that guide the pre-route flow.Advanced Fusion TechnologyThe Fusion Design Platform™ delivers unprecedented full-flow QoR and time-to-results (TTR) to accelerate the next wave of semiconductor industry innovation. The industry’s first AI-enhanced, cloud-ready Design Platform with Fusion Technology™ isbuilt from Synopsys’ market-leading, massively-parallel digital design tools, and augmented with innovative capabilities to tacklethe escalating challenges in cloud computing, automotive, mobile, and IoT market segments and accelerate the next wave of industry innovation.Fusion Technology redefines conventional EDA tool boundaries across synthesis, place-and-route, and signoff, sharing integrated engines across the industry’s premier digital design products. It enables designers to accelerate the delivery of their next-generation designs with the industry-best QoR and the TTR.©2019 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks isavailable at /copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.。

Moxa CP-114UL 四口RS-232 422 485多口PCI串口板说明书

CP-114UL Series4-port RS-232/422/485Universal PCI serial boards with optional2kV isolationFeatures and Benefits•Over700kbps data throughput for top performance•128-byte FIFO and on-chip H/W,S/W flow control•Universal PCI compatible with3.3/5V PCI and PCI-X•921.6kbps maximum baudrate for fast data transmission•Drivers provided for a broad selection of operating systems,includingWindows and Linux•Easy maintenance with built-in LEDs•Wide-temperature model available for-40to85°C environmentsCertificationsIntroductionMoxa’s CP-114UL Series of multiport serial boards is designed to be used by industrial automation system integrators for long-distance, multipoint,PC-based data acquisition applications.On-chip Automatic Data Direction Control for precision RS-485communication requires precise timing control to enable and disable the line driver.The Moxa Turbo Serial Engine™chip that powers the CP-114UL boards come with on-chip ADDC®,which makes RS-485as easy to use as RS-232.In RS-485mode,the serial port can connect up to31daisy-chained RS-485devices within a range of1.2km.For long-distance RS-485communication,2kV electrical isolation protections are available to prevent equipment damage.Drivers Provided for Windows,Linux,and UNIXMoxa continues to support a wide variety of operating systems,and the CP-114UL boards are no exception.Reliable Windows and Linux/UNIX drivers are provided for all Moxa boards,and other operating systems,such as WEPOS,are also supported for embedded integration.SpecificationsSerial InterfaceComm.Controller MU860(16C550C compatible)Bus32-bit Universal PCIConnector DB44femaleFIFO128bytesMax.No.of Boards per PC8No.of Ports4Serial Standards RS-232,RS-422,RS-485Baudrate50bps to921.6kbpsData Bits5,6,7,8Stop Bits1,1.5,2Flow Control None,RTS/CTS,XON/XOFFParity None,Even,Odd,Space,MarkIsolation CP-114UL-I Series:2kVSerial SignalsRS-232TxD,RxD,RTS,CTS,DTR,DSR,DCD,GNDRS-422Tx+,Tx-,Rx+,Rx-,GNDRS-485-4w Tx+,Tx-,Rx+,Rx-,GNDRS-485-2w Data+,Data-,GNDSerial Software FeaturesWindows Drivers DOS,Windows95/98/ME/NT/2000,Windows XP/2003/Vista/2008/7/8/8.1/10(x86/x64),Windows2008R2/2012/2012R2/2016/2019(x64),Windows Embedded CE5.0/6.0,Windows XP EmbeddedLinux Drivers Linux kernel2.4.x,Linux kernel2.6.x,Linux kernel3.x,Linux kernel4.x,Linux kernel5.x UNIX Drivers QNX6,SCO OpenServer,UnixWare7,Solaris10,FreeBSDPower ParametersInput Current CP-114UL Series:320mA@5VDCCP-114UL-I Series:465mA@5VDCPhysical CharacteristicsDimensions CP-114UL Series:64.4x120mm(2.53x4.72in)CP-114UL-I Series:64.4x130mm(2.53x5.12in)LED InterfaceLED Indicators Built-in Tx,Rx LEDs for each portEnvironmental LimitsOperating Temperature Standard Models:0to55°C(32to131°F)Wide Temp.Models:-40to85°C(-40to185°F)Storage Temperature(package included)-40to85°C(-40to185°F)Ambient Relative Humidity5to95%(non-condensing)Standards and CertificationsEMC EN55032/35EMI CISPR32,FCC Part15B Class BEMS All models:IEC61000-4-2ESD:Contact:4kV;Air:8kVIEC61000-4-3RS:80MHz to1GHz:3V/mCP-114UL-I Series:IEC61000-4-4EFT:Power:1kV;Signal:0.5kVIEC61000-4-5Surge:Power:2kVIEC61000-4-6CS:150kHz to80MHz:3V/m;Signal:3V/mIEC61000-4-8International Approval CP-114UL-DB9M:KCDeclarationGreen Product RoHS,CRoHS,WEEEMTBFTime114,223hrsStandards Telcordia SR332WarrantyWarranty Period5yearsDetails See /warrantyPackage ContentsDevice1x CP-114UL Series serial boardCable1x M44to4x DB9-M cable,50cm(-DB9M models)1x M44to4x DB25-M cable,50cm(-DB25M models) Documentation1x quick installation guide1x substance disclosure table1x warranty cardDimensionsCP-114UL CP-114UL-IOrdering InformationModel Name Serial Bus No.of Serial Ports Serial IsolationProtectionOperating Temp.Included CableCP-114UL w/o Cable Universal PCI4–0to55°C–CP-114UL-T Universal PCI4–-40to85°C–CP-114UL-DB9M Universal PCI4–0to55°C CBL-M44M9x4-50 CP-114UL-DB25M Universal PCI4–0to55°C CBL-M44M25x4-50 CP-114UL-I Universal PCI42kV0to55°C–CP-114UL-I-DB9M Universal PCI42kV0to55°C CBL-M44M9x4-50 CP-114UL-I-DB25M Universal PCI42kV0to55°C CBL-M44M25x4-50Accessories(sold separately)CablesCBL-M44M9x4-50DB44male to DB9male serial cable,50cmCBL-M44M25x4-50M44to4x DB25male serial cable,50cmCBL-F9M9-150DB9female to DB9male serial cable,1.5mCBL-F9M9-20DB9female to DB9male serial cable,20cm©Moxa Inc.All rights reserved.Updated Oct12,2021.This document and any portion thereof may not be reproduced or used in any manner whatsoever without the express written permission of Moxa Inc.Product specifications subject to change without notice.Visit our website for the most up-to-date product information.。

NI PXI定时与同步模块说明书

CONTENTSPXI Timing and Synchronization Modules Detailed View of PXIe-6674TKey FeaturesNI-Sync Application Programming Interface (API) Platform-Based Approach to Test and Measurement PXI InstrumentationHardware ServicesPXI Timing and Synchronization Modules PXIe-6674T, PXIe-6672, PXI-6683 and PXI-6683H•Generate high-stability PXI system reference clocks and high-resolution sample clocks •Minimize skew through access to PXI-star and PXIe-Dstar chassis trigger lines •Import and export system reference clocks for synchronization between multiple chassis orexternal devices •Achieve synchronization over large distance through GPS, IEEE 1588,IRIG-B or PPS•Develop advanced timing and sync applications with NI-Sync and NI-TClk softwarePowerful, Reliable Timing and SynchronizationNI’s PXI timing and synchronization modules enable a higher level of synchronization on the PXI platform through high-stability clocks, high-precision triggering and advanced signal routing. Implementing timing and synchronization hardware can vastly improve the accuracy of measurements, provide advanced triggering schemes, and allow synchronization of multiple devices for extremely high-channel-count applications. NI’s portfolio includes both signal-based and time-based solutions to deliver the advantages of synchronization to numerous applications.Table 1. NI offers various PXI modules to meet a range of timing and synchronization requirements.*Accuracy within one year of calibration adjustment within 0 ºC and 55 ºC operating temperature rangeDetailed View of PXIe-6674TSlot Compatibility PXI Timing or Peripheral Slot PXI or PXIe Hybrid Peripheral Slot PXIe System TimingSlot PXIe System TimingSlot Oscillator Accuracy*TCXO / 3.5 ppm TCXO / 3.5 ppm TCXO / 3.5 ppm OCXO / 80 ppb DDS Clock Generation Range Not available Not available DC to 105 MHz 0.3 Hz to 1 GHzDDS Clock Generation Resolution Not availableNot available0.075 Hz2.84 µHzPXI 10MHz Backplane Clock Override ● ● ● Clock Import Capability ● ● ● Clock Export Capability● ● ● ● Time-Based Synchronization (GPS, IEEE 1588, IRIG-B, PPS)● ● PXI Trigger Access (PXI_TRIG) ● ● ● ● PXI-Star Trigger Access (PXI_STAR) ●● ● PXIe-Dstar Trigger Access (PXI_DSTARA/B/C)● Front Panel Physical Connectors SMB, RJ45SMB, RJ45SMB SMA PFI Lines on Front Panel3366Key FeaturesHigh-Stability, High-Accuracy Onboard ClockApplications requiring highly reliable and consistent clock signals require a highly stable oscillator to avoid clock inaccuracies. For an NI PXI Express chassis, the oscillator is accurate to 25 parts per million (ppm). Inserting an NI PXI timing and synchronization module into the system timing slot of the chassis enables the user to replace this backplane system reference clock using the higher accuracy oscillator of the module. The PXIe-6672 and PXI-6683 modules contain a temperature-compensated crystal oscillator (TCXO) which can achieve accuracies better than 4 ppm. The PXIe-6674T features an oven-controlled crystal oscillator (OCXO) with an accuracy of 80 parts-per-billion (ppb). Note that the PXI-6683H contains the same oscillator as the PXI-6683, but due to its hybrid connectivity is not able to override the backplane clock.Figure 1.By referencing the OCXO on the PXIe-6674T, the 10 MHz backplane clock of a PXI chassis achieves muchlower phase noise and thus more clock stability.PXI modular instruments with phased-lock loop circuits, such as high-speed digitizers and waveform generators, can take advantage of the high-precision clock of timing and synchronization modules. When locking to a high-accuracy reference clock, the instrument inherits the accuracy of the clock, achieving sample clock resolutions as low as 0.5 Hz with an OCXO-based module.Skew Reduction with Star and Differential Star LinesDue to the variation in signal path lengths between slots in a PXI chassis, skew may be introduced when sending clocks or triggers to multiple slot destinations over the PXI trigger bus. To address this, all NI PXI chassis also include trace-length-matched star trigger lines accessible from a timing and synchronization module in the system timing slot. Star trigger lines can reduce skew to a maximum of 1 ns. Additionally, PXI Express chassis include differential star trigger lines capable of minimizing slot-to-slot skew to under 150 ps.Figure 2.While every slot of the PXI backplane may access the PXI trigger bus, the star trigger lines and differential star trigger lines are only accessible through the system timing slot.Time-Based Synchronization with GPS, IEEE 1588, IRIG-B or PPSThe NI PXI-6683 and PXI-6683H timing and synchronization modules synchronize PXI and PXI Express systems through time-based technology or protocols. Time-based modules can generate triggers and clock signals at programmable future times and timestamp input events with the synchronized system time including that of real-time systems. For PXI Express systems requiring time-based synchronization with backplane clock discipline or star trigger access, the PXI-6683H can be combined with the PXIe- 6674T or PXIe-6672 to provide a full-featured synchronization solution.Advanced Routing of Clocks and TriggersUsing a PXI timing and synchronization module provides the capability of advanced routing of clock and trigger signals. Through the combination of system timing slot access and FPGA-based routing, many more source-to-destination routes become possible, allowing more flexible designs and efficient use of system resources.Table 2. The PXIe-6674T timing and synchronization module features a wide vaiety of source-to-destination routes bycombining the power of the PXI Express architecture with the signal-routing capabilities of the onboard FPGA.● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●●●●●●●NI-Sync Application Programming Interface (API)The NI-Sync driver allows configuration of system timing and synchronization through LabVIEW, C, or .NET. This includes signal-based synchronization, such as sharing triggers and clocks to be used directly, or time-based synchronization, using time protocols such as IEEE-1588, IRIG, or GPS for non-tethered systems. NI-Sync is designed for use with other NI drivers, such as NI-DAQmx, for advanced timing, high channel count, distributed or multiple-instrument applications.DestinationS o u r c ePlatform-Based Approach to Test and MeasurementWhat Is PXI?Powered by software, PXI is a rugged PC-based platform for measurement and automation systems. PXI combines PCI electrical-bus features with the modular, Eurocard packaging of CompactPCI and then adds specialized synchronization buses and key software features. PXI is both a high-performance and low-cost deployment platform for applications such as manufacturing test, military and aerospace, machine monitoring, automotive, and industrial test. Developed in 1997 and launched in 1998, PXI is an open industry standard governed by the PXI Systems Alliance (PXISA), a group of more than 70 companies chartered to promote the PXI standard, ensure interoperability, and maintain the PXI specification.Integrating the Latest Commercial TechnologyBy leveraging the latest commercial technology for our products, we can continually deliver high-performance and high-quality products to our users at a competitive price. The latest PCI Express Gen 3 switches deliver higher data throughput, the latest Intel multicore processors facilitate faster and more efficient parallel (multisite) testing, the latest FPGAs from Xilinx help to push signal processing algorithms to the edge to accelerate measurements, and the latest data converters from TI and ADI continuallyincrease the measurement range and performance of our instrumentation.PXI InstrumentationNI offers more than 600 different PXI modules ranging from DC to mmWave. Because PXI is an open industry standard, nearly 1,500 products are available from more than 70 different instrument vendors. With standard processing and control functions designated to a controller, PXI instruments need to contain only the actual instrumentation circuitry, which provides effective performance in a small footprint. Combined with a chassis and controller, PXI systems feature high-throughput data movement using PCI Express bus interfaces and sub-nanosecond synchronization with integrated timing and triggering.OscilloscopesSample at speeds up to 12.5 GS/s with 5 GHz of analog bandwidth, featuring numerous triggering modes and deep onboard memoryDigital InstrumentsPerform characterization and production test of semiconductor devices with timing sets and per channel pin parametric measurement unit (PPMU)Frequency Counters Perform counter timer tasks such as event counting and encoder position, period, pulse, and frequency measurementsPower Supplies & Loads Supply programmable DC power, with some modules including isolated channels, output disconnect functionality, and remote senseSwitches (Matrix & MUX) Feature a variety of relay types and row/column configurations to simplify wiring in automated test systemsGPIB, Serial, & Ethernet Integrate non-PXI instruments into a PXI system through various instrument control interfaces Digital MultimetersPerform voltage (up to 1000 V), current (up to 3A), resistance, inductance, capacitance, and frequency/period measurements, as well as diode testsWaveform Generators Generate standard functions including sine, square, triangle, and ramp as well as user-defined, arbitrary waveformsSource Measure Units Combine high-precision source and measure capability with high channel density, deterministic hardware sequencing, and SourceAdapt transient optimizationFlexRIO Custom Instruments & Processing Provide high-performance I/O and powerful FPGAs for applications that require more than standard instruments can offerVector Signal Transceivers Combine a vector signal generator and vector signal analyzer with FPGA-based, real-time signal processing and controlData Acquisition Modules Provide a mix of analog I/O, digital I/O, counter/timer, and trigger functionality for measuring electricalor physical phenomena©2019 National Instruments. All rights reserved. LabVIEW, National Instruments, NI, NI TestStand, and are trademarks of National Instruments. Other product and company names listed are trademarks or trade names of their respective companies. The contents of this Site could contain technical inaccuracies, typographical errors or out-of-date information. Information may be updated or changed at any time, without notice. Visit /manuals for the latest information. Hardware ServicesAll NI hardware includes a one-year warranty for basic repair coverage, and calibration in adherence to NI specifications prior to shipment. PXI Systems also include basic assembly and a functional test. NI offers additional entitlements to improve uptime and lower maintenance costs with service programs for hardware. Learn more at /services/hardware .Program Duration 3 or 5 years3 or 5 years Length of service programExtended Repair Coverage●●NI restores your device’s functionality and includes firmware updates and factory calibration.SystemConfiguration,Assembly, and Test 1 ● ●NI technicians assemble, install software in, and test your system per your custom configuration prior to shipment.Advanced Replacement 2 ●NI stocks replacement hardware that can be shipped immediately if a repair is needed.System Return MaterialAuthorization (RMA)1 ●NI accepts the delivery of fully assembled systems when performing repair services.Calibration Plan (Optional) Standard Expedited 3NI performs the requested level of calibration at the specified calibration interval for the duration of the service program.1This option is only available for PXI, CompactRIO, and CompactDAQ systems.2This option is not available for all products in all countries. Contact your local NI sales engineer to confirm availability. 3Expedited calibration only includes traceable levels.PremiumPlus Service ProgramNI can customize the offerings listed above, or offer additional entitlements such as on-site calibration, custom sparing, and life-cycle services through a PremiumPlus Service Program. Contact your NI sales representative to learn more.Technical SupportEvery NI system includes a 30-day trial for phone and e-mail support from NI engineers, which can be extended through a Software Service Program (SSP) membership. NI has more than 400 support engineers available around the globe to provide local support in more than 30 languages. Additionally, take advantage of NI’s award winning online resources and communities .。

FDA指导原则-Guidance for industry-Rheumatoid Arthritis-Developing Drug Products for Treatment

1350 Piccard Drive, Rockville, MD 20850-4307
DSMICA E-mail: dsmica@; DSMICA Fax: 301-443-8818
(Tel) Manufacturers Assistance: 800-638-2041 or 301-443-6597
or
Office of Communication, Outreach, and Development, HFM-40
Center for Biologics Evaluation and Research, Food and Drug Administration
1401 Rockville Pike, Suite 200N, Rockville, MD 20852-1448
I.
INTRODUCTION
The purpose of this guidance is to outline the FDA’s current thinking on the principles of clinical development relevant to dose-selection and assessment of efficacy and safety to support the approval of drug products for the treatment of patients with rheumatoid arthritis (RA). It also addresses additional considerations for drug products developed as drug-device combination products. This guidance does not address nonclinical development, development of drug products for juvenile idiopathic arthritis, or development of biosimilar products. This guidance revises the guidance for industry Clinical Development Programs for Drugs, Devices, and Biological Products for the Treatment of Rheumatoid Arthritis (RA), published in February 1999.2 After it has been finalized, this guidance will replace the February 1999 guidance and will reflect the current thinking of the FDA on RA drug product development. The FDA’s current thinking has been influenced by clinical development programs conducted for RA since the 1999 guidance published, and by changes in the standard of care for RA because of availability of many effective treatments. The revisions include: Dose(s) and dosing regimen(s) selection throughout the clinical development program Expectations for establishing efficacy in RA based on signs and symptoms and physical function domains

FPGA的英文文献及翻译

Building Programmable Automation Controllers with LabVIEW FPGAOverviewProgrammable Automation Controllers(PACs)are gaining acceptance within the industrial control market as the ideal solution for applications that require highly integratedanalog and digital I/O,floating-point processing,and seamless connectivity to multiple processing nodes.National Instruments offers a variety of PAC solutions powered by onecommon software development environment,NI LabVIEW.With LabVIEW,you can buildcustom I/O interfaces for industrial applications using add-on software,such as the NI LabVIEW FPGA Module.With the LabVIEW FPGA Module and reconfigurable I/O(RIO)hardware,National Instruments delivers an intuitive,accessible solution for incorporating the flexibility andcustomizability of FPGA technology into industrial PAC systems.You can define the logicembedded in FPGA chips across the family of RIO hardware targets without knowing low-level hardware description languages(HDLs)or board-level hardware design details, as wellas quickly define hardware for ultrahigh-speed control,customized timing and synchronization,low-level signal processing,and custom I/O with analog,digital,and counters within a single device.You also can integrate your custom NI RIO hardware withimage acquisition and analysis,motion control,and industrial protocols,such as CAN andRS232,to rapidly prototype and implement a complete PAC system.Table of Contents1.IntroductionNI RIO2.Hardware for PACsBuilding PACs with LabVIEW and bVIEW FPGA ModuleFPGA Development4.FlowUsing NI SoftMotion to Create5.Custom Motion ControllersApplications6.Conclusion7.IntroductionYou can use graphical programming in LabVIEW and the LabVIEW FPGA Module to configure the FPGA(field-programmable gate array)on NI RIO devices.RIO technology,themerging of LabVIEW graphical programming with FPGAs on NI RIO hardware, provides aflexible platform for creating sophisticated measurement and control systems that you couldhardware.custom-designed with only create previouslyAn FPGA is a chip that consists of many unconfigured logic gates.Unlike the fixed, vendor-defined functionality of an ASIC(application-specific integrated circuit)chip, you canconfigure and reconfigure the logic on FPGAs for your specific application.FPGAs are usedin applications where either the cost of developing and fabricating an ASIC is prohibitive,orthe hardware must be reconfigured after being placed into service.The flexible, software-programmable architecture of FPGAs offer benefits such as high-performance execution ofcustom algorithms,precise timing and synchronization,rapid decision making,and simultaneous execution of parallel tasks.Today,FPGAs appear in such devices as instruments,consumer electronics,automobiles,aircraft,copy machines,and application-specific computer hardware.While FPGAs are often used in industrial control products,FPGA functionality has not previously been made accessible to industrial control engineers. Defining FPGAs has historically required expertise using HDL programming or complexdesign tools used more by hardware design engineers than by control engineers.With the LabVIEW FPGA Module and NI RIO hardware,you now can use LabVIEW, ahigh-level graphical development environment designed specifically for measurement andcontrol applications,to create PACs that have the customization,flexibility,and high-performance of FPGAs.Because the LabVIEW FPGA Module configures custom circuitry inhardware,your system can process and generate synchronized analog and digital signalsrapidly and deterministically.Figure1illustrates many of the NI RIO devices that you canconfigure using the LabVIEW FPGA Module.bVIEW FPGA VI Block Diagram and RIO Hardware PlatformsNI RIO Hardware for PACsHistorically,programming FPGAs has been limited to engineers who have in-depth knowledge of VHDL or other low-level design tools,which require overcoming a very steeplearning curve.With the LabVIEW FPGA Module,NI has opened FPGA technology to abroader set of engineers who can now define FPGA logic using LabVIEW graphical development.Measurement and control engineers can focus primarily on their test and controlapplication,where their expertise lies,rather than the low-level semantics of transferring logicinto the cells of the chip.The LabVIEW FPGA Module model works because of the tightintegration between the LabVIEW FPGA Module and the commercial off-the-shelf (COTS)hardware architecture of the FPGA and surrounding I/O components.National Instruments PACs provide modular,off-the-shelf platforms for your industrialcontrol applications.With the implementation of RIO technology on PCI,PXI,and CompactVision System platforms and the introduction of RIO-based CompactRIO,engineers nowhave the benefits of a COTS platform with the high-performance,flexibility,and customization benefits of FPGAs at their disposal to build PACs.National Instruments PCIand PXI R Series plug-in devices provide analog and digital data acquisition and control forhigh-performance,user-configurable timing and synchronization,as well as onboard decisionmaking on a single ing these off-the-shelf devices,you can extend your NI PXI orPCI industrial control system to include high-speed discrete and analog control, customsensor interfaces,and precise timing and control.NI CompactRIO,a platform centered on RIO technology,provides a small,industrially rugged,modular PAC platform that gives you high-performance I/O and unprecedentedflexibility in system timing.You can use NI CompactRIO to build an embedded system forapplications such as in-vehicle data acquisition,mobile NVH testing,and embedded machinecontrol systems.The rugged NI CompactRIO system is industrially rated and certified, and itis designed for greater than50g of shock at a temperature range of-40to70°C.NI Compact Vision System is a rugged machine vision package that withstands the harshenvironments common in robotics,automated test,and industrial inspection systems. NICVS-145x devices offer unprecedented I/O capabilities and network connectivity for distributed machine vision applications.NI CVS-145x systems use IEEE1394 (FireWire)technology,compatible with more than40cameras with a wide range of functionality, performance,and price.NI CVS-1455and NI CVS-1456devices contain configurable FPGAs so you can implement custom counters,timing,or motor control in yourvision application.Building PACs with LabVIEW and the LabVIEW FPGA ModuleWith LabVIEW and the LabVIEW FPGA Module,you add significant flexibility and customization to your industrial control hardware.Because many PACs are already programmed using LabVIEW,programming FPGAs with LabVIEW is easy because it usesthe same LabVIEW development environment.When you target the FPGA on an NI RIOdevice,LabVIEW displays only the functions that can be implemented in the FPGA, furthereasing the use of LabVIEW to program FPGAs.The LabVIEW FPGA Module Functionspalette includes typical LabVIEW structures and functions,such as While Loops,For Loops,Case Structures,and Sequence Structures as well as a dedicated set of LabVIEW FPGA-specific functions for math,signal generation and analysis,linear and nonlinear control,comparison logic,array and cluster manipulation,occurrences,analog and digital I/O, andtiming.You can use a combination of these functions to define logic and embed intelligencedevice.RIO NI your ontoFigure2shows an FPGA application that implements a PID control algorithm on the NIRIO hardware and a host application on a Windows machine or an RT target that communicates with the NI RIO hardware.This application reads from analog input0 (AI0),performs the PID calculation,and outputs the resulting data on analog output0(AO0). Whilethe FPGA clock runs at40MHz the loop in this example runs much slower because eachcomponent takes longer than one-clock cycle to execute.Analog control loops can run on anFPGA at a rate of about200kHz.You can specify the clock rate at compile time.This example shows only one PID loop;however,creating additional functionality on the NI RIOdevice is merely a matter of adding another While Loop.Unlike traditional PCFPGAs are parallel processors.Adding additional loops to your application does not affect theperformance of your PID loop.Figure2.PID Control Using an Embedded LabVIEW FPGA VI with Corresponding LabVIEW Host VI.FPGA Development FlowAfter you create the LabVIEW FPGA VI,you compile the code to run on the NI RIO hardware.Depending on the complexity of your code and the specifications of your development system,compile time for an FPGA VI can range from minutes to several hours.To maximize development productivity,with the R Series RIO devices you can use a bit-accurate emulation mode so you can verify the logic of your design before initiating thecompile process.When you target the FPGA Device Emulator,LabVIEW accesses I/O fromthe device and executes the VI logic on the Windows development computer.In this mode,you can use the same debugging tools available in LabVIEW for Windows,such as executionhighlighting,probes,and breakpoints.Once the LabVIEW FPGA code is compiled,you create a LabVIEW host VI to integrateyour NI RIO hardware into the rest of your PAC system.Figure3illustrates the developmentprocess for creating an FPGA application.The host VI uses controls and indicators on theFPGA VI front panel to transfer data between the FPGA on the RIO device and the hostprocessing engine.These front panel objects are represented as data registers within theFPGA.The host computer can be either a PC or PXI controller running Windows or a PC,PXI controller,Compact Vision System,or CompactRIO controller running a real-time operating system(RTOS).In the above example,we exchange the set point,PID gains, looprate,AI0,and AO0data with the LabVIEW host VI.bVIEW FPGA Development FlowThe NI RIO device driver includes a set of functions to develop a communication interface to the FPGA.The first step in building a host VI is to open a reference to the FPGAVI and RIO device.The Open FPGA VI Reference function,as seen in Figure2,also downloads and runs the compiled FPGA code during execution.After opening the reference,you read and write to the control and indicator registers on the FPGA using theRead/WriteControl function.Once you wire the FPGA reference into this function,you can simply selectwhich controls and indicators you want to read and write to.You can enclose the FPGARead/Write function within a While Loop to continuously read and write to the FPGA. Finally,the last function within the LabVIEW host VI in Figure2is the Close FPGA VIReference function.The Close FPGA VI Reference function stops the FPGA VI and closesthe reference to the device.Now you can download other compiled FPGA VIs to the device tochange or modify its functionality.The LabVIEW host VI can also be used to perform floating-point calculations,data logging,networking,and any calculations that do not fit within the FPGA fabric.For addeddeterminism and reliability,you can run your host application on an RTOS with the LabVIEW Real-Time bVIEW Real-Time systems provide deterministic processing engines for functions performed synchronously or asynchronously to the FPGA.For example,floating-point arithmetic,including FFTs,PID calculations,and custom controlalgorithms,are often performed in the LabVIEW Real-Time environment.Relevant data canbe stored on a LabVIEW Real-Time system or transferred to a Windows host computeroff-line analysis,data logging,or user interface displays.The architecture for this configuration is shown in Figure4.Each NI PAC platform that offers RIO hardware can runLabVIEW Real-Time VIs.plete PAC Architecture Using LabVIEW FPGA,LabVIEW Real-Time and Host PC Within each R Series and CompactRIO device,there is flash memory available to store acompiled LabVIEW FPGA VI and run the application immediately upon power up of thedevice.In this configuration,as long as the FPGA has power,it runs the FPGA VI, even if thehost computer crashes or is powered down.This is ideal for programming safety power downand power up sequences when unexpected events occur.Using NI SoftMotion to Create Custom Motion ControllersThe NI SoftMotion Development Module for LabVIEW provides VIs and functions to help you build custom motion controllers as part of NI PAC hardware platforms that caninclude NI RIO devices,DAQ devices,and Compact FieldPoint.NI SoftMotion provides allof the functions that typically reside on a motion controller DSP.With it,you can handle pathplanning,trajectory generation,and position and velocity loop control in the NI LabVIEWenvironment and then deploy the code on LabVIEW Real-Time or LabVIEWFPGA-basedtarget hardware.NI SoftMotion includes functions for trajectory generator and spline engine and examples with complete source code for supervisory control,position,and velocity controlloop using the PID algorithm.Supervisory control and the trajectory generator run on a LabVIEW Real-Time target and run at millisecond loop rates.The spline engine and thecontrol loop can run either on a LabVIEW Real-Time target at millisecond loop rates or on aLabVIEW FPGA target at microsecond loop rates.ApplicationsBecause the LabVIEW FPGA Module can configure low-level hardware design of FPGAs and use the FPGAs within in a modular system,it is ideal for industrial control applications requiring custom hardware.These custom applications can include a custom mixof analog,digital,and counter/timer I/O,analog control up to125kHz,digital control up to20MHz,and interfacing to custom digital protocols for the following:Batch control?Discrete control?Motion control?In-vehicle data acquisition?Machine condition monitoring?Rapid control prototyping(RCP)?Industrial control and acquisition?Distributed data acquisition and control?Mobile/portable noise,vibration,and harshness(NVH)analysis?ConclusionThe LabVIEW FPGA Module brings the flexibility,performance,and customization ofFPGAs to PAC ing NI RIO devices and LabVIEW graphical programming,youcan build flexible and custom hardware using the COTS hardware often required in industrialcontrol applications.Because you are using LabVIEW,a programming language already usedin many industrial control applications,to define your NI RIO hardware,there is nolearn VHDL or other low-level hardware design tools to create custom hardware. Using theLabVIEW FPGA Module and NI RIO hardware as part of your NI PAC adds significantflexibility and functionality for applications requiring ultrahigh-speed control, interfaces tocounters.and digital,analog,of mix I/O custom a or protocols,digital custom使用（现场可编程门阵列）模块开发可编程自动化控FPGALabVIEW制器综述工业控制上的应用要求高度集成的模拟和数字输入输出、浮点运算和多重处理节点的无缝连接。

3GPP TS 36.331 V13.2.0 (2016-06)

3GPP TS 36.331 V13.2.0 (2016-06)Technical Specification3rd Generation Partnership Project;Technical Specification Group Radio Access Network;Evolved Universal Terrestrial Radio Access (E-UTRA);Radio Resource Control (RRC);Protocol specification(Release 13)The present document has been developed within the 3rd Generation Partnership Project (3GPP TM) and may be further elaborated for the purposes of 3GPP. The present document has not been subject to any approval process by the 3GPP Organizational Partners and shall not be implemented.This Specification is provided for future development work within 3GPP only. The Organizational Partners accept no liability for any use of this Specification. Specifications and reports for implementation of the 3GPP TM system should be obtained via the 3GPP Organizational Partners' Publications Offices.KeywordsUMTS, radio3GPPPostal address3GPP support office address650 Route des Lucioles - Sophia AntipolisValbonne - FRANCETel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16InternetCopyright NotificationNo part may be reproduced except as authorized by written permission.The copyright and the foregoing restriction extend to reproduction in all media.© 2016, 3GPP Organizational Partners (ARIB, ATIS, CCSA, ETSI, TSDSI, TTA, TTC).All rights reserved.UMTS™ is a Trade Mark of ETSI registered for the benefit of its members3GPP™ is a Trade Mark of ETSI registered for the benefit of its Members and of the 3GPP Organizational PartnersLTE™ is a Trade Mark of ETSI currently being registered for the benefit of its Members and of the 3GPP Organizational Partners GSM® and the GSM logo are registered and owned by the GSM AssociationBluetooth® is a Trade Mark of the Bluetooth SIG registered for the benefit of its membersContentsForeword (18)1Scope (19)2References (19)3Definitions, symbols and abbreviations (22)3.1Definitions (22)3.2Abbreviations (24)4General (27)4.1Introduction (27)4.2Architecture (28)4.2.1UE states and state transitions including inter RAT (28)4.2.2Signalling radio bearers (29)4.3Services (30)4.3.1Services provided to upper layers (30)4.3.2Services expected from lower layers (30)4.4Functions (30)5Procedures (32)5.1General (32)5.1.1Introduction (32)5.1.2General requirements (32)5.2System information (33)5.2.1Introduction (33)5.2.1.1General (33)5.2.1.2Scheduling (34)5.2.1.2a Scheduling for NB-IoT (34)5.2.1.3System information validity and notification of changes (35)5.2.1.4Indication of ETWS notification (36)5.2.1.5Indication of CMAS notification (37)5.2.1.6Notification of EAB parameters change (37)5.2.1.7Access Barring parameters change in NB-IoT (37)5.2.2System information acquisition (38)5.2.2.1General (38)5.2.2.2Initiation (38)5.2.2.3System information required by the UE (38)5.2.2.4System information acquisition by the UE (39)5.2.2.5Essential system information missing (42)5.2.2.6Actions upon reception of the MasterInformationBlock message (42)5.2.2.7Actions upon reception of the SystemInformationBlockType1 message (42)5.2.2.8Actions upon reception of SystemInformation messages (44)5.2.2.9Actions upon reception of SystemInformationBlockType2 (44)5.2.2.10Actions upon reception of SystemInformationBlockType3 (45)5.2.2.11Actions upon reception of SystemInformationBlockType4 (45)5.2.2.12Actions upon reception of SystemInformationBlockType5 (45)5.2.2.13Actions upon reception of SystemInformationBlockType6 (45)5.2.2.14Actions upon reception of SystemInformationBlockType7 (45)5.2.2.15Actions upon reception of SystemInformationBlockType8 (45)5.2.2.16Actions upon reception of SystemInformationBlockType9 (46)5.2.2.17Actions upon reception of SystemInformationBlockType10 (46)5.2.2.18Actions upon reception of SystemInformationBlockType11 (46)5.2.2.19Actions upon reception of SystemInformationBlockType12 (47)5.2.2.20Actions upon reception of SystemInformationBlockType13 (48)5.2.2.21Actions upon reception of SystemInformationBlockType14 (48)5.2.2.22Actions upon reception of SystemInformationBlockType15 (48)5.2.2.23Actions upon reception of SystemInformationBlockType16 (48)5.2.2.24Actions upon reception of SystemInformationBlockType17 (48)5.2.2.25Actions upon reception of SystemInformationBlockType18 (48)5.2.2.26Actions upon reception of SystemInformationBlockType19 (49)5.2.3Acquisition of an SI message (49)5.2.3a Acquisition of an SI message by BL UE or UE in CE or a NB-IoT UE (50)5.3Connection control (50)5.3.1Introduction (50)5.3.1.1RRC connection control (50)5.3.1.2Security (52)5.3.1.2a RN security (53)5.3.1.3Connected mode mobility (53)5.3.1.4Connection control in NB-IoT (54)5.3.2Paging (55)5.3.2.1General (55)5.3.2.2Initiation (55)5.3.2.3Reception of the Paging message by the UE (55)5.3.3RRC connection establishment (56)5.3.3.1General (56)5.3.3.1a Conditions for establishing RRC Connection for sidelink communication/ discovery (58)5.3.3.2Initiation (59)5.3.3.3Actions related to transmission of RRCConnectionRequest message (63)5.3.3.3a Actions related to transmission of RRCConnectionResumeRequest message (64)5.3.3.4Reception of the RRCConnectionSetup by the UE (64)5.3.3.4a Reception of the RRCConnectionResume by the UE (66)5.3.3.5Cell re-selection while T300, T302, T303, T305, T306, or T308 is running (68)5.3.3.6T300 expiry (68)5.3.3.7T302, T303, T305, T306, or T308 expiry or stop (69)5.3.3.8Reception of the RRCConnectionReject by the UE (70)5.3.3.9Abortion of RRC connection establishment (71)5.3.3.10Handling of SSAC related parameters (71)5.3.3.11Access barring check (72)5.3.3.12EAB check (73)5.3.3.13Access barring check for ACDC (73)5.3.3.14Access Barring check for NB-IoT (74)5.3.4Initial security activation (75)5.3.4.1General (75)5.3.4.2Initiation (76)5.3.4.3Reception of the SecurityModeCommand by the UE (76)5.3.5RRC connection reconfiguration (77)5.3.5.1General (77)5.3.5.2Initiation (77)5.3.5.3Reception of an RRCConnectionReconfiguration not including the mobilityControlInfo by theUE (77)5.3.5.4Reception of an RRCConnectionReconfiguration including the mobilityControlInfo by the UE(handover) (79)5.3.5.5Reconfiguration failure (83)5.3.5.6T304 expiry (handover failure) (83)5.3.5.7Void (84)5.3.5.7a T307 expiry (SCG change failure) (84)5.3.5.8Radio Configuration involving full configuration option (84)5.3.6Counter check (86)5.3.6.1General (86)5.3.6.2Initiation (86)5.3.6.3Reception of the CounterCheck message by the UE (86)5.3.7RRC connection re-establishment (87)5.3.7.1General (87)5.3.7.2Initiation (87)5.3.7.3Actions following cell selection while T311 is running (88)5.3.7.4Actions related to transmission of RRCConnectionReestablishmentRequest message (89)5.3.7.5Reception of the RRCConnectionReestablishment by the UE (89)5.3.7.6T311 expiry (91)5.3.7.7T301 expiry or selected cell no longer suitable (91)5.3.7.8Reception of RRCConnectionReestablishmentReject by the UE (91)5.3.8RRC connection release (92)5.3.8.1General (92)5.3.8.2Initiation (92)5.3.8.3Reception of the RRCConnectionRelease by the UE (92)5.3.8.4T320 expiry (93)5.3.9RRC connection release requested by upper layers (93)5.3.9.1General (93)5.3.9.2Initiation (93)5.3.10Radio resource configuration (93)5.3.10.0General (93)5.3.10.1SRB addition/ modification (94)5.3.10.2DRB release (95)5.3.10.3DRB addition/ modification (95)5.3.10.3a1DC specific DRB addition or reconfiguration (96)5.3.10.3a2LWA specific DRB addition or reconfiguration (98)5.3.10.3a3LWIP specific DRB addition or reconfiguration (98)5.3.10.3a SCell release (99)5.3.10.3b SCell addition/ modification (99)5.3.10.3c PSCell addition or modification (99)5.3.10.4MAC main reconfiguration (99)5.3.10.5Semi-persistent scheduling reconfiguration (100)5.3.10.6Physical channel reconfiguration (100)5.3.10.7Radio Link Failure Timers and Constants reconfiguration (101)5.3.10.8Time domain measurement resource restriction for serving cell (101)5.3.10.9Other configuration (102)5.3.10.10SCG reconfiguration (103)5.3.10.11SCG dedicated resource configuration (104)5.3.10.12Reconfiguration SCG or split DRB by drb-ToAddModList (105)5.3.10.13Neighbour cell information reconfiguration (105)5.3.10.14Void (105)5.3.10.15Sidelink dedicated configuration (105)5.3.10.16T370 expiry (106)5.3.11Radio link failure related actions (107)5.3.11.1Detection of physical layer problems in RRC_CONNECTED (107)5.3.11.2Recovery of physical layer problems (107)5.3.11.3Detection of radio link failure (107)5.3.12UE actions upon leaving RRC_CONNECTED (109)5.3.13UE actions upon PUCCH/ SRS release request (110)5.3.14Proximity indication (110)5.3.14.1General (110)5.3.14.2Initiation (111)5.3.14.3Actions related to transmission of ProximityIndication message (111)5.3.15Void (111)5.4Inter-RAT mobility (111)5.4.1Introduction (111)5.4.2Handover to E-UTRA (112)5.4.2.1General (112)5.4.2.2Initiation (112)5.4.2.3Reception of the RRCConnectionReconfiguration by the UE (112)5.4.2.4Reconfiguration failure (114)5.4.2.5T304 expiry (handover to E-UTRA failure) (114)5.4.3Mobility from E-UTRA (114)5.4.3.1General (114)5.4.3.2Initiation (115)5.4.3.3Reception of the MobilityFromEUTRACommand by the UE (115)5.4.3.4Successful completion of the mobility from E-UTRA (116)5.4.3.5Mobility from E-UTRA failure (117)5.4.4Handover from E-UTRA preparation request (CDMA2000) (117)5.4.4.1General (117)5.4.4.2Initiation (118)5.4.4.3Reception of the HandoverFromEUTRAPreparationRequest by the UE (118)5.4.5UL handover preparation transfer (CDMA2000) (118)5.4.5.1General (118)5.4.5.2Initiation (118)5.4.5.3Actions related to transmission of the ULHandoverPreparationTransfer message (119)5.4.5.4Failure to deliver the ULHandoverPreparationTransfer message (119)5.4.6Inter-RAT cell change order to E-UTRAN (119)5.4.6.1General (119)5.4.6.2Initiation (119)5.4.6.3UE fails to complete an inter-RAT cell change order (119)5.5Measurements (120)5.5.1Introduction (120)5.5.2Measurement configuration (121)5.5.2.1General (121)5.5.2.2Measurement identity removal (122)5.5.2.2a Measurement identity autonomous removal (122)5.5.2.3Measurement identity addition/ modification (123)5.5.2.4Measurement object removal (124)5.5.2.5Measurement object addition/ modification (124)5.5.2.6Reporting configuration removal (126)5.5.2.7Reporting configuration addition/ modification (127)5.5.2.8Quantity configuration (127)5.5.2.9Measurement gap configuration (127)5.5.2.10Discovery signals measurement timing configuration (128)5.5.2.11RSSI measurement timing configuration (128)5.5.3Performing measurements (128)5.5.3.1General (128)5.5.3.2Layer 3 filtering (131)5.5.4Measurement report triggering (131)5.5.4.1General (131)5.5.4.2Event A1 (Serving becomes better than threshold) (135)5.5.4.3Event A2 (Serving becomes worse than threshold) (136)5.5.4.4Event A3 (Neighbour becomes offset better than PCell/ PSCell) (136)5.5.4.5Event A4 (Neighbour becomes better than threshold) (137)5.5.4.6Event A5 (PCell/ PSCell becomes worse than threshold1 and neighbour becomes better thanthreshold2) (138)5.5.4.6a Event A6 (Neighbour becomes offset better than SCell) (139)5.5.4.7Event B1 (Inter RAT neighbour becomes better than threshold) (139)5.5.4.8Event B2 (PCell becomes worse than threshold1 and inter RAT neighbour becomes better thanthreshold2) (140)5.5.4.9Event C1 (CSI-RS resource becomes better than threshold) (141)5.5.4.10Event C2 (CSI-RS resource becomes offset better than reference CSI-RS resource) (141)5.5.4.11Event W1 (WLAN becomes better than a threshold) (142)5.5.4.12Event W2 (All WLAN inside WLAN mobility set becomes worse than threshold1 and a WLANoutside WLAN mobility set becomes better than threshold2) (142)5.5.4.13Event W3 (All WLAN inside WLAN mobility set becomes worse than a threshold) (143)5.5.5Measurement reporting (144)5.5.6Measurement related actions (148)5.5.6.1Actions upon handover and re-establishment (148)5.5.6.2Speed dependant scaling of measurement related parameters (149)5.5.7Inter-frequency RSTD measurement indication (149)5.5.7.1General (149)5.5.7.2Initiation (150)5.5.7.3Actions related to transmission of InterFreqRSTDMeasurementIndication message (150)5.6Other (150)5.6.0General (150)5.6.1DL information transfer (151)5.6.1.1General (151)5.6.1.2Initiation (151)5.6.1.3Reception of the DLInformationTransfer by the UE (151)5.6.2UL information transfer (151)5.6.2.1General (151)5.6.2.2Initiation (151)5.6.2.3Actions related to transmission of ULInformationTransfer message (152)5.6.2.4Failure to deliver ULInformationTransfer message (152)5.6.3UE capability transfer (152)5.6.3.1General (152)5.6.3.2Initiation (153)5.6.3.3Reception of the UECapabilityEnquiry by the UE (153)5.6.4CSFB to 1x Parameter transfer (157)5.6.4.1General (157)5.6.4.2Initiation (157)5.6.4.3Actions related to transmission of CSFBParametersRequestCDMA2000 message (157)5.6.4.4Reception of the CSFBParametersResponseCDMA2000 message (157)5.6.5UE Information (158)5.6.5.1General (158)5.6.5.2Initiation (158)5.6.5.3Reception of the UEInformationRequest message (158)5.6.6 Logged Measurement Configuration (159)5.6.6.1General (159)5.6.6.2Initiation (160)5.6.6.3Reception of the LoggedMeasurementConfiguration by the UE (160)5.6.6.4T330 expiry (160)5.6.7 Release of Logged Measurement Configuration (160)5.6.7.1General (160)5.6.7.2Initiation (160)5.6.8 Measurements logging (161)5.6.8.1General (161)5.6.8.2Initiation (161)5.6.9In-device coexistence indication (163)5.6.9.1General (163)5.6.9.2Initiation (164)5.6.9.3Actions related to transmission of InDeviceCoexIndication message (164)5.6.10UE Assistance Information (165)5.6.10.1General (165)5.6.10.2Initiation (166)5.6.10.3Actions related to transmission of UEAssistanceInformation message (166)5.6.11 Mobility history information (166)5.6.11.1General (166)5.6.11.2Initiation (166)5.6.12RAN-assisted WLAN interworking (167)5.6.12.1General (167)5.6.12.2Dedicated WLAN offload configuration (167)5.6.12.3WLAN offload RAN evaluation (167)5.6.12.4T350 expiry or stop (167)5.6.12.5Cell selection/ re-selection while T350 is running (168)5.6.13SCG failure information (168)5.6.13.1General (168)5.6.13.2Initiation (168)5.6.13.3Actions related to transmission of SCGFailureInformation message (168)5.6.14LTE-WLAN Aggregation (169)5.6.14.1Introduction (169)5.6.14.2Reception of LWA configuration (169)5.6.14.3Release of LWA configuration (170)5.6.15WLAN connection management (170)5.6.15.1Introduction (170)5.6.15.2WLAN connection status reporting (170)5.6.15.2.1General (170)5.6.15.2.2Initiation (171)5.6.15.2.3Actions related to transmission of WLANConnectionStatusReport message (171)5.6.15.3T351 Expiry (WLAN connection attempt timeout) (171)5.6.15.4WLAN status monitoring (171)5.6.16RAN controlled LTE-WLAN interworking (172)5.6.16.1General (172)5.6.16.2WLAN traffic steering command (172)5.6.17LTE-WLAN aggregation with IPsec tunnel (173)5.6.17.1General (173)5.7Generic error handling (174)5.7.1General (174)5.7.2ASN.1 violation or encoding error (174)5.7.3Field set to a not comprehended value (174)5.7.4Mandatory field missing (174)5.7.5Not comprehended field (176)5.8MBMS (176)5.8.1Introduction (176)5.8.1.1General (176)5.8.1.2Scheduling (176)5.8.1.3MCCH information validity and notification of changes (176)5.8.2MCCH information acquisition (178)5.8.2.1General (178)5.8.2.2Initiation (178)5.8.2.3MCCH information acquisition by the UE (178)5.8.2.4Actions upon reception of the MBSFNAreaConfiguration message (178)5.8.2.5Actions upon reception of the MBMSCountingRequest message (179)5.8.3MBMS PTM radio bearer configuration (179)5.8.3.1General (179)5.8.3.2Initiation (179)5.8.3.3MRB establishment (179)5.8.3.4MRB release (179)5.8.4MBMS Counting Procedure (179)5.8.4.1General (179)5.8.4.2Initiation (180)5.8.4.3Reception of the MBMSCountingRequest message by the UE (180)5.8.5MBMS interest indication (181)5.8.5.1General (181)5.8.5.2Initiation (181)5.8.5.3Determine MBMS frequencies of interest (182)5.8.5.4Actions related to transmission of MBMSInterestIndication message (183)5.8a SC-PTM (183)5.8a.1Introduction (183)5.8a.1.1General (183)5.8a.1.2SC-MCCH scheduling (183)5.8a.1.3SC-MCCH information validity and notification of changes (183)5.8a.1.4Procedures (184)5.8a.2SC-MCCH information acquisition (184)5.8a.2.1General (184)5.8a.2.2Initiation (184)5.8a.2.3SC-MCCH information acquisition by the UE (184)5.8a.2.4Actions upon reception of the SCPTMConfiguration message (185)5.8a.3SC-PTM radio bearer configuration (185)5.8a.3.1General (185)5.8a.3.2Initiation (185)5.8a.3.3SC-MRB establishment (185)5.8a.3.4SC-MRB release (185)5.9RN procedures (186)5.9.1RN reconfiguration (186)5.9.1.1General (186)5.9.1.2Initiation (186)5.9.1.3Reception of the RNReconfiguration by the RN (186)5.10Sidelink (186)5.10.1Introduction (186)5.10.1a Conditions for sidelink communication operation (187)5.10.2Sidelink UE information (188)5.10.2.1General (188)5.10.2.2Initiation (189)5.10.2.3Actions related to transmission of SidelinkUEInformation message (193)5.10.3Sidelink communication monitoring (195)5.10.6Sidelink discovery announcement (198)5.10.6a Sidelink discovery announcement pool selection (201)5.10.6b Sidelink discovery announcement reference carrier selection (201)5.10.7Sidelink synchronisation information transmission (202)5.10.7.1General (202)5.10.7.2Initiation (203)5.10.7.3Transmission of SLSS (204)5.10.7.4Transmission of MasterInformationBlock-SL message (205)5.10.7.5Void (206)5.10.8Sidelink synchronisation reference (206)5.10.8.1General (206)5.10.8.2Selection and reselection of synchronisation reference UE (SyncRef UE) (206)5.10.9Sidelink common control information (207)5.10.9.1General (207)5.10.9.2Actions related to reception of MasterInformationBlock-SL message (207)5.10.10Sidelink relay UE operation (207)5.10.10.1General (207)5.10.10.2AS-conditions for relay related sidelink communication transmission by sidelink relay UE (207)5.10.10.3AS-conditions for relay PS related sidelink discovery transmission by sidelink relay UE (208)5.10.10.4Sidelink relay UE threshold conditions (208)5.10.11Sidelink remote UE operation (208)5.10.11.1General (208)5.10.11.2AS-conditions for relay related sidelink communication transmission by sidelink remote UE (208)5.10.11.3AS-conditions for relay PS related sidelink discovery transmission by sidelink remote UE (209)5.10.11.4Selection and reselection of sidelink relay UE (209)5.10.11.5Sidelink remote UE threshold conditions (210)6Protocol data units, formats and parameters (tabular & ASN.1) (210)6.1General (210)6.2RRC messages (212)6.2.1General message structure (212)–EUTRA-RRC-Definitions (212)–BCCH-BCH-Message (212)–BCCH-DL-SCH-Message (212)–BCCH-DL-SCH-Message-BR (213)–MCCH-Message (213)–PCCH-Message (213)–DL-CCCH-Message (214)–DL-DCCH-Message (214)–UL-CCCH-Message (214)–UL-DCCH-Message (215)–SC-MCCH-Message (215)6.2.2Message definitions (216)–CounterCheck (216)–CounterCheckResponse (217)–CSFBParametersRequestCDMA2000 (217)–CSFBParametersResponseCDMA2000 (218)–DLInformationTransfer (218)–HandoverFromEUTRAPreparationRequest (CDMA2000) (219)–InDeviceCoexIndication (220)–InterFreqRSTDMeasurementIndication (222)–LoggedMeasurementConfiguration (223)–MasterInformationBlock (225)–MBMSCountingRequest (226)–MBMSCountingResponse (226)–MBMSInterestIndication (227)–MBSFNAreaConfiguration (228)–MeasurementReport (228)–MobilityFromEUTRACommand (229)–Paging (232)–ProximityIndication (233)–RNReconfiguration (234)–RNReconfigurationComplete (234)–RRCConnectionReconfiguration (235)–RRCConnectionReconfigurationComplete (240)–RRCConnectionReestablishment (241)–RRCConnectionReestablishmentComplete (241)–RRCConnectionReestablishmentReject (242)–RRCConnectionReestablishmentRequest (243)–RRCConnectionReject (243)–RRCConnectionRelease (244)–RRCConnectionResume (248)–RRCConnectionResumeComplete (249)–RRCConnectionResumeRequest (250)–RRCConnectionRequest (250)–RRCConnectionSetup (251)–RRCConnectionSetupComplete (252)–SCGFailureInformation (253)–SCPTMConfiguration (254)–SecurityModeCommand (255)–SecurityModeComplete (255)–SecurityModeFailure (256)–SidelinkUEInformation (256)–SystemInformation (258)–SystemInformationBlockType1 (259)–UEAssistanceInformation (264)–UECapabilityEnquiry (265)–UECapabilityInformation (266)–UEInformationRequest (267)–UEInformationResponse (267)–ULHandoverPreparationTransfer (CDMA2000) (273)–ULInformationTransfer (274)–WLANConnectionStatusReport (274)6.3RRC information elements (275)6.3.1System information blocks (275)–SystemInformationBlockType2 (275)–SystemInformationBlockType3 (279)–SystemInformationBlockType4 (282)–SystemInformationBlockType5 (283)–SystemInformationBlockType6 (287)–SystemInformationBlockType7 (289)–SystemInformationBlockType8 (290)–SystemInformationBlockType9 (295)–SystemInformationBlockType10 (295)–SystemInformationBlockType11 (296)–SystemInformationBlockType12 (297)–SystemInformationBlockType13 (297)–SystemInformationBlockType14 (298)–SystemInformationBlockType15 (298)–SystemInformationBlockType16 (299)–SystemInformationBlockType17 (300)–SystemInformationBlockType18 (301)–SystemInformationBlockType19 (301)–SystemInformationBlockType20 (304)6.3.2Radio resource control information elements (304)–AntennaInfo (304)–AntennaInfoUL (306)–CQI-ReportConfig (307)–CQI-ReportPeriodicProcExtId (314)–CrossCarrierSchedulingConfig (314)–CSI-IM-Config (315)–CSI-IM-ConfigId (315)–CSI-RS-Config (317)–CSI-RS-ConfigEMIMO (318)–CSI-RS-ConfigNZP (319)–CSI-RS-ConfigNZPId (320)–CSI-RS-ConfigZP (321)–CSI-RS-ConfigZPId (321)–DMRS-Config (321)–DRB-Identity (322)–EPDCCH-Config (322)–EIMTA-MainConfig (324)–LogicalChannelConfig (325)–LWA-Configuration (326)–LWIP-Configuration (326)–RCLWI-Configuration (327)–MAC-MainConfig (327)–P-C-AndCBSR (332)–PDCCH-ConfigSCell (333)–PDCP-Config (334)–PDSCH-Config (337)–PDSCH-RE-MappingQCL-ConfigId (339)–PHICH-Config (339)–PhysicalConfigDedicated (339)–P-Max (344)–PRACH-Config (344)–PresenceAntennaPort1 (346)–PUCCH-Config (347)–PUSCH-Config (351)–RACH-ConfigCommon (355)–RACH-ConfigDedicated (357)–RadioResourceConfigCommon (358)–RadioResourceConfigDedicated (362)–RLC-Config (367)–RLF-TimersAndConstants (369)–RN-SubframeConfig (370)–SchedulingRequestConfig (371)–SoundingRS-UL-Config (372)–SPS-Config (375)–TDD-Config (376)–TimeAlignmentTimer (377)–TPC-PDCCH-Config (377)–TunnelConfigLWIP (378)–UplinkPowerControl (379)–WLAN-Id-List (382)–WLAN-MobilityConfig (382)6.3.3Security control information elements (382)–NextHopChainingCount (382)–SecurityAlgorithmConfig (383)–ShortMAC-I (383)6.3.4Mobility control information elements (383)–AdditionalSpectrumEmission (383)–ARFCN-ValueCDMA2000 (383)–ARFCN-ValueEUTRA (384)–ARFCN-ValueGERAN (384)–ARFCN-ValueUTRA (384)–BandclassCDMA2000 (384)–BandIndicatorGERAN (385)–CarrierFreqCDMA2000 (385)–CarrierFreqGERAN (385)–CellIndexList (387)–CellReselectionPriority (387)–CellSelectionInfoCE (387)–CellReselectionSubPriority (388)–CSFB-RegistrationParam1XRTT (388)–CellGlobalIdEUTRA (389)–CellGlobalIdUTRA (389)–CellGlobalIdGERAN (390)–CellGlobalIdCDMA2000 (390)–CellSelectionInfoNFreq (391)–CSG-Identity (391)–FreqBandIndicator (391)–MobilityControlInfo (391)–MobilityParametersCDMA2000 (1xRTT) (393)–MobilityStateParameters (394)–MultiBandInfoList (394)–NS-PmaxList (394)–PhysCellId (395)–PhysCellIdRange (395)–PhysCellIdRangeUTRA-FDDList (395)–PhysCellIdCDMA2000 (396)–PhysCellIdGERAN (396)–PhysCellIdUTRA-FDD (396)–PhysCellIdUTRA-TDD (396)–PLMN-Identity (397)–PLMN-IdentityList3 (397)–PreRegistrationInfoHRPD (397)–Q-QualMin (398)–Q-RxLevMin (398)–Q-OffsetRange (398)–Q-OffsetRangeInterRAT (399)–ReselectionThreshold (399)–ReselectionThresholdQ (399)–SCellIndex (399)–ServCellIndex (400)–SpeedStateScaleFactors (400)–SystemInfoListGERAN (400)–SystemTimeInfoCDMA2000 (401)–TrackingAreaCode (401)–T-Reselection (402)–T-ReselectionEUTRA-CE (402)6.3.5Measurement information elements (402)–AllowedMeasBandwidth (402)–CSI-RSRP-Range (402)–Hysteresis (402)–LocationInfo (403)–MBSFN-RSRQ-Range (403)–MeasConfig (404)–MeasDS-Config (405)–MeasGapConfig (406)–MeasId (407)–MeasIdToAddModList (407)–MeasObjectCDMA2000 (408)–MeasObjectEUTRA (408)–MeasObjectGERAN (412)–MeasObjectId (412)–MeasObjectToAddModList (412)–MeasObjectUTRA (413)–ReportConfigEUTRA (422)–ReportConfigId (425)–ReportConfigInterRAT (425)–ReportConfigToAddModList (428)–ReportInterval (429)–RSRP-Range (429)–RSRQ-Range (430)–RSRQ-Type (430)–RS-SINR-Range (430)–RSSI-Range-r13 (431)–TimeToTrigger (431)–UL-DelayConfig (431)–WLAN-CarrierInfo (431)–WLAN-RSSI-Range (432)–WLAN-Status (432)6.3.6Other information elements (433)–AbsoluteTimeInfo (433)–AreaConfiguration (433)–C-RNTI (433)–DedicatedInfoCDMA2000 (434)–DedicatedInfoNAS (434)–FilterCoefficient (434)–LoggingDuration (434)–LoggingInterval (435)–MeasSubframePattern (435)–MMEC (435)–NeighCellConfig (435)–OtherConfig (436)–RAND-CDMA2000 (1xRTT) (437)–RAT-Type (437)–ResumeIdentity (437)–RRC-TransactionIdentifier (438)–S-TMSI (438)–TraceReference (438)–UE-CapabilityRAT-ContainerList (438)–UE-EUTRA-Capability (439)–UE-RadioPagingInfo (469)–UE-TimersAndConstants (469)–VisitedCellInfoList (470)–WLAN-OffloadConfig (470)6.3.7MBMS information elements (472)–MBMS-NotificationConfig (472)–MBMS-ServiceList (473)–MBSFN-AreaId (473)–MBSFN-AreaInfoList (473)–MBSFN-SubframeConfig (474)–PMCH-InfoList (475)6.3.7a SC-PTM information elements (476)–SC-MTCH-InfoList (476)–SCPTM-NeighbourCellList (478)6.3.8Sidelink information elements (478)–SL-CommConfig (478)–SL-CommResourcePool (479)–SL-CP-Len (480)–SL-DiscConfig (481)–SL-DiscResourcePool (483)–SL-DiscTxPowerInfo (485)–SL-GapConfig (485)。

软考网络项目工程师通用英文单词和缩写翻译

软考网络工程师常用英文单词和缩写翻译DARPA国防高级研究计划局ARPARNET(Internet)阿帕网ICCC国际计算机通信会议CCITT国际电报电话咨询委员会SNA系统网络体系结构(IBM)DNA数字网络体系结构(DEC)CSMA/CD载波监听多路访问/冲突检测(Xerox)下一代INTERNETInternet2第二代INTERNETTCP/IP SNA SPX/IPX AppleTalk 网络协议NII国家信息基础设施(信息高速公路) GII全球信息基础设施MIPSPC的处理能力Petabit10^15BIT/SCu芯片:OC48光缆通信SDH同步数字复用WDH波分复用ADSL不对称数字用户服务线HFE/HFC结构和Cable-modem 机顶盒PCS便携式智能终端CODEC编码解码器ASK(amplitude shift keying) 幅移键控法FSK(frequency shift keying) 频移键控法PSK(phase shift keying)相移键控法NRZ (Non return to zero)不归零制PCM(pulse code modulation) 脉冲代码调制nonlinear encoding非线性编程FDM频分多路复用TDM时分多路复用STDM统计时分多路复用DS064kb/sDS124DS0DS1C48DS0DS296DS0DS3762DS0DS44032DS0CSU(channel service unit) 信道服务部件SONET/SDH同步光纤网络接口LRC纵向冗余校验CRC循环冗余校验ARQ自动重发请求ACK确认NAK不确认preamble前文postamble后文ITU国际电信联合会character-oriented 面向字符bit-oriented面向位SYNC同步字符HDLC面向位的方案SDLC面向位的方案bit-stuffing位插入STP屏蔽双绞线UTP非屏蔽双绞线RG-58A/U标准RG-11用于10BASE5RG-59U75欧0.25INCH CATVRG-62U9欧0.25INCH ARCnet10BASE5IEEE802.3RG-59U0.25inch CATVRG-62U0.25inch ARCnetLED(light emitting diobe) 发光二级管ILD(injection laster diobe) 注入型激光二级管PIN检波器APD检波器intensity modulation亮度调制line of sight可视通路CCITT V.28(EIA RS232C)非平衡型CCITT V.10/X.26(EIA RS423A)新的非平衡型CCITT V.11/X.27(EIA RS422A)新的平衡型TD发送数据RD接收数据XON/XOFF流控制Automatic Repeat Request Protocol自动重发请求Send and wait ARQ:continuous ARQ停等ARQWard Christensen人名Kermit协议circuit switching线路交换packet switching分组交换virtual circuit虚电路ATM(asynchronous transfer mode) 异步传输模式异步时分多路复用packetizer打包器VPI(vritual path identifier)虚路径标识VCI(virtual channel identifier)虚通道标识syntax语法semantics语义timing定时OSI(open system interconnection)session会话synchronization同步activity management活动管理AE应用实体UE用户元素CASE公共应用服务元素SASE特定应用服务元素VT虚拟终端JIM作业传送和操作reverved保留echo回送discard丢弃active users活动用户daytime白天netstat(who is up of NETSTAT)qotd(quote of the day)日期引用chargen(character generator)字符发送器nameserver(domani name server)域名服务器bootps(bootstrap protocol server/client) 引导协议服务器/客户机tftp(trivial file transfer)简单文件传送sunrpc(sun microsystems RPC)SUN公司NTP:network time protocol网络时间协议SNMP(SNMP net monitor)SNMP网络监控器SNMP traps陷井biffunix comsat daemone.g timed daemon syslogsystem logURG紧急字段可用ACK确认字段可用PSH请求急迫操作连接复位SYN同步序号FIN发送方字节流结束Manchester曼彻斯特编码FDDI(fiber distributed data interface) 光纤分布数据接口TTRT目标标记循环时间aggregation of multiple link segments 多重链接分段聚合协议MAN(metropolitan area network plus)CSMA/CD(carrier sense multiple access/collision detection) 载波监听Token bus令牌总线Token ring令牌环SAP服务访问点request indictaion response confirmationLLC PDULLC协议数据单元DSAP address目地服务访问点地址字段SSAP address源服务访问点地址字段XID交换标识SABME置扩充的异步平衡方式DISC断开连接DM断开FRMR帧拒收solt time时间片AUI连接单元接口MAU介质连接接口MDI介质相关接口PMA物理介质接口SFD起始定界符PAD填充字段FCS帧校验序列PLS物理层收发信号slot timeInter Frame Gap帧attempt limit最大重传次数back off limit避免算法参数Jam size阻塞参数max frame size最大帧address size地址collaspsed backone 折叠式主干网基本服务集ESS扩展服务集DFW-MAC分布式基础无线MAC IFS帧间空隙SIFS:短PIFS点协调DIFS分布协调CTS发送清除DQDB(IEEE802.6)分布式队列双总线TDM时分复用TMS多时分交换TSI时间片互换TST网络机构TSSST STS SSTSS TSTST网络机构PSTN公用交换电话网public switched telephone network详细PBX:private branch exchange专用交换网PABX;private automatic branch exchange 自动交换机CBX:computerized branch exchange程控交换SLIP:serial line IP串行IPLCP(link control protocol)链路控制协议NCP:network control protocol网络控制协议BRI基本速率接口PRI群速率接口LAPB:line access protocol balanced链路访问协议平衡registration登录interrupt中断LAP F link access procedure for frame-mode bearer serives 太长了rotate不知道recovery恢复discard丢弃retransmission重传switched access交换访问intergated access集成访问alerting警告progress进展AALATM适配层GFCcell rate decoupling信元率去耦SDH同步数字级PDH准国步数字级GSM:group special mobile 移动通讯NSS网络子系统OMC-R操作维护中心BSS基站子系统基站控制器BTS基站收发信机MS移动站SIM:subscriber identity module标识模块MSC移动交换机HLR归属位置寄存器VLR访问位置寄存器AUC鉴权中心EIR设备识别寄存器OMC-S操作维护中心SC短消息中心WAP无线应用协议WAE无线应用层WSP会话层WTP事务层WTLS安全层WDP传输层MAP移动应用部分WML无线标记语言SSL:secure sockets layer安全套接层PCS个人通信业务PCN个人通信网GEO对地静止轨道NON-GE0(MEO,LEO)不清楚ITU国际电信联盟VSAT:very small aperture -terminal 甚小天线终端LEOS低轨道卫星通信系统repeater中继器bridge网桥router路由器gatewayONsemble stackable 10BASE 可叠加组合型集线器transparent bridge传输桥source routing bridge源路径桥broadcast storm广播风暴encapsulation封装translation bridging转换桥接方式SRT源地址选择透明桥偏移more flag标识ICMPINTERNET控制报文协议SPF:shortest path first最短路径IGP:interior gateway protocol核心网关协议EGP:exterior gateway protocol扩展网关协议RIP:routing information protocol路由信息协议OSPF开放最短径优先协议acquisition request获取请求acquisition confirm获取确认cease中止poll轮询IPX/SPX internetwork packet exchange/sequented packet exchange NOVELLinterpreter解释器redirector重定向器SFT system fault tolerant系统容错ELS entry level solution不认识ODI开放数据链路接口NDIS network device interface specification 网络设备接口...DDCS数据库管理和分布数据库连接服务DCE:distributed computing environment 分布计算环境OSF:open software foundation开放软件基金PWS:peer web serviceWEB服务器OEM原始设备制造商RAS远程访问服务IIS:Internet Information serverINTERNET信息服务WINS:windows internet name system WINDOWS命名服务NTDS:windows NT directory serverNT目录服务TDI传输驱动程序接口schedule++应用程序,预约本COSE:common open software environment 普通开放软件环境RPC远程过程调用SNMP:simple network management protocol 简单网管协议SMI:structer of management information管理信息结构SMT:station management管理站SMTP:simple mail transfer protocol简单邮件传输协议SNA:system network architectureIBM网络SNR:signal noise ratio信噪比SONENT:synchronous optical network 同步光纤网络SPE:synchronous payload envelope 同步PAYLOAD信CMIS/CMIP公共管理信息服务/协议CMISE公共管理信息服务agent代理IMT:inductive modeling technology不知道plaintext明文ciphertext脱密encryption加密decryption解密symmetric key cryptography 对称加密asymmetric key cryptography 不对称加密public key公钥private key私钥DES:data encryption standard数据加密标准IDEA:international data encryption algorithm 国际加密算法PIN:personal identification number个人标识符session key会话层密钥KDC:key distribuetion center密钥分发中心sign签名seal封装certificate证书certificate authority CA证书权威机构OSF开放软件中心AFS:andrew file system分布式文件系统ticket凭证authenticatior身份认证timestamp时间标记reply attack检测重放攻击realm域PKI公钥基础设施certificate hierarchy证书层次结构across certificate交叉证书security domain安全领域cerfificate revoke list(CRL)证书层次结构LDAP:light weight directory access protocol 协议access matrix访问矩阵ACL:access control list 访问列表reference monitor引用监控器course grained粗粒度访问控制medium grained中粒度访问控制fine grained细粒度访问控制CORBA面向对象的分布系统应用MQ报文队列VPN虚拟专网IPSEC:IP security安全IPSA:security association安全??encopulation security payload 封装安全负载AH:authentication header鉴别报头IKE:Internet key exchange交换rogue programs捣乱程序IPSP:IP security protocol安全IKMP:internet key managemetn protocol 协议IESGInternet工程领导小组SHA安全散列算法MAC:message authentication code代码CBC密码块链接SSL安全套接层协议cerfificate verify证书检验报文PEM私用强化邮件PGP:pretty good privacy 好的private保密authenticated已认证SEPP安全电子付费协议SET安全电子交易middleware中间件GSS-API通用安全服务SNP安全网络编程BWD:browser web database浏览WEBplugin插入件basic authentication scheme不知道digest authentication scheme摘要认证方法open group:the open group research institute 研究所DCE:distributed computing environment分布式计算机环境SLP:secure local proxy安全局部代理SDG:secure domain proxy安全域代理OMG:object management group目标管理组CORBS:common object request broker architecture 不清楚authentication鉴别access control访问控制data confidnetiality保密data integrity数据完整性non-reputation防止否认enciphermant加密机制digital signature mechanisms数据完整性authentication mechanisms路由控制机制notarization mechanisms公证trusted function可信security labels安全标记event dectection事件检测security audit trail安全审计跟踪security recovery安全恢复TCSEC:trusted computer system evaluation criteria标准TCSEC TNI:trusted network interpretation of the TCSEC 标准TCSEC TDI:trusted database interpretation of the TCSEC 标准ITSEC:information technology security evaluation。

NVIDIA ConnectX-7 商品说明书

Accelerate Software-Defined Networking Provide Security from Edge to CoreNVIDIA ASAP2 technology accelerates software-defined networking, delivering line-rate performance with no CPU penalty.Hardware engines in ConnectX-7 offload and accelerate security, with in-line encryption/decryption of TLS, IPsec, and MACsec.Enhance Storage Performance Enable Precision TimingConnectX-7 enables high-performance storage and data access with RoCE and GPUDirect Storage and accelerates NVMe-oF over both RoCE and TCP.ConnectX-7 provides extremely accurate time synchronization for data-center applications and timing-sensitive infrastructures.NVIDIA CONNECTX-7 400G ETHERNETSMART ACCELERATION FOR CLOUD, DATA-CENTER AND EDGEACCELERATED NETWORKING AND SECURITY FOR THE MOST ADVANCED CLOUD AND AI WORKLOADSThe NVIDIA® ConnectX®-7 SmartNIC is optimized to deliver accelerated networking for modern cloud, artificial intelligence, and traditional enterprise workloads. ConnectX-7 provides a broad set of software-defined, hardware accelerated networking, storage, and security capabilities which enable organizations to modernize and secure their IT infrastructures.Extending the tradition of NVIDIA’s industry leading innovation for networking, ConnectX-7, is available in 1, 2, or 4-port configurations and delivers up to 400Gb/s of bandwidth. With features such as NVIDIA ASAP2 - Accelerated Switching and Packet Processing®, advanced RoCE, NVIDIA GPUDirect® Storage, and in-line hardware acceleration for TLS/IPsec/MACsec encryption/decryption, ConnectX-7 empowers agile and high-performance solutions from edge to core data centers to clouds, all while enhancing network security and reducing the total cost of ownership.Available in PCIe card and OCP3.0 form factors, ConnectX-7 empowers solutions for cloud, hyperscale, and enterprise networking.PRODUCT SPECIFICATIONSMaximum TotalBandwidth400GbESupported EthernetSpeeds10/25/40/50/100/200/400GbE Number ofNetwork Ports1/2/4Network InterfaceTechnologiesNRZ (10/25G) / PAM4(50/100G)Host Interface PCIe Gen5.0 x16/ x32Cards Form Factors PCIe FHHL/ HHHL,OCP3.0 SFF Network Interfaces SFP56, QSFP56,QSFP56-DD,QSFP112, SFP112NVIDIA CONNECTX-7 | DATASHEET | APR21Network Interface>Up to 4 network ports supporting NRZ, PAM4 (50G and 100G), in various ports configurations:>1 x 10/25/40/50/100/200/400GbE>2 x 10/25/40/50/100/200/400GbE>4 x 10/25/40/50/100/200GbE>Up to 400Gb/s total bandwidthHost Interface>32 lanes of PCIe Gen 5.0, compatible with PCIe Gen 2/3/4>Integrated PCI switch>NVIDIA Multi-Host™ (up to 8 hosts)and NVIDIA Socket Direct™>MSI/MSI-X mechanisms>Advanced PCIe capabilities Networking>RoCE, Zero Touch RoCE>ASAP² - Accelerated Switch and Packet>Processing® for SDN and VNF acceleration >Single Root I/O Virtualization (SR-IOV)>VirtIO acceleration>Overlay network acceleration:VXLAN, GENEVE, NVGRE>Programmable flexible parser:user-defined classification>Connection tracking (L4 firewall)>Flow mirroring, sampling and statistics>Header rewrite>Hierarchical QoS>Stateless TCP offloadsVNF Acceleration>Hardware offload programmable pipeline:>Packet classification on network layersL2 to L4 and tunneled traffic such as GTPand VXLAN>Packet dispatching to multiple cores>Multi-threaded API for concurrent updateof offloaded rules>ASAP2 accelerations/actions: counters,QoS, NAT, aging, mirroring, sampling,flow tag>Hairpin flow for full hardware offload>Highly-scalable number of classificationsand actions>Application access to hardware statistics>Application access to crypto offloadsCyber Security>IInline hardware IPsec encryptionand decryption>AES-GCM 128/256-bit key>IPsec over RoCE>Inline hardware TLS encryptionand decryption>AES-GCM 128/256-bit key>Inline hardware MACsec encryption anddecryption>AES-GCM 128/256-bit key>AES-GCM-XPN 128/256-bit key>Data-at-rest AES-XTS encryptionand decryption>AES-XTS 256/512-bit key>Platform security>Secure boot with hardware root-of-trust>Secure firmware update>On-board flash encryptionAdvanced Timing andSynchronization>Advanced PTP>IEEE 1588v2 (any profile)>Meets G.8273.2 Class C standard>PTP hardware clock (PHC) (UTC format)>12 nanosecond accuracy>Line-rate hardware timestamp(UTC format)>SyncE>Meets G.8262.1 (eEEC)>Configurable PPS In and configurablePPS Out>Time-triggered scheduling>PTP-based packet pacing>Time-based SDN acceleration (ASAP2)Storage Accelerations>NVMe™ over Fabrics (NVMe-oF) storagetarget offloads>NVMe-oF™ over TCP/RoCE acceleration>Storage protocols: iSER, NFSoRDMA, SMBDirect, NVMe-oF™, and moreHPC / AI>All-to-All engine>NVIDIA GPUDirect>NVIDIA GPUDirect StorageManagement and Control>SMBus 2.0>Network Controller SidebandInterface (NC-SI)>NC-SI, MCTP over SMBus and MCTPover PCIe - Baseboard ManagementController interface>PLDM for Monitor and Control DSP0248>PLDM for Firmware Update DSP026>I2C interface for device controland configuration>General Purpose I/O pins>SPI interface to flash>JTAG IEEE 1149.1 and>IEEE 1149.6Remote Boot>Remote boot over Ethernet>Remote boot over iSCSI>UEFI support for x86 and Arm servers>PXE bootForm Factors and Options>PCIe HHHL/FHHL>OCP 3.0 SFFFEATURESTo learn more about the NVIDIA ConnectX SmartNICs visit /en-us/networking/ethernet-adapters/© 2021 NVIDIA Corporation. All rights reserved. NVIDIA, the NVIDIA logo, ConnectX, ConnectX-7, GPUDirect, Multi-Host, Socket Direct, and ASAP2 - Accelerated Switch and Packet Processing are trademarks and/or registered trademarks of NVIDIA Corporation in the U.S. and other countries. Other company and product names may be trademarks of the respective companies with which they are associated. MAY21.。

通信优化英语词汇

DDN Digital Data Network 数字数据网
DDPM Dual Duplexer Module for DDRM BTS 双双工单元模块
DDPU Dual-Duplexer Unit for DTRU BTS 双双工单元
DDRM Double Transceivers Digital and Radio Frequency Module 双密度数字射频收发信机模块
CBCCH Cell Broadcast Control Channel 小区广播控制信道
CBQ Cell Bar Qualify 小区禁止限制
CBSM Cell Broadcast Short Message 小区广播短消息
CC Country Code 国家码
CC Calling Control 呼叫控制
BM Basic Module 基本模块
BP Burst Pulse 突发脉冲
BQ Bad Quality 质量差
BS Base Station 基站
BS1 Abis Interface Abis接口
BSC Base Station Controller 基站控制器
BSIC Base Station Identity Code 基站识别码
DLCEPI Data Link Connection End Point Identifier 数据链路连接端点标识
DLCI Digital Link Connection Identity 数据链路连接标识
DNS Domain Name Server 域名服务器
DPC Destination (Signaling) Point Code 目的信令点编码

有关众包的英语作文

有关众包的英语作文SummaryCrowdsourcing is an emerging model of distributed problem solving, and is also widely studied and practiced to support software engineering. This paper reviews the application of crowdsourcing in software engineering, firstly reviews the definition of crowdsourcing, and draws the definition and classification of crowdsourcing software engineering. Then, it further analyzes the software engineering domains, tasks, and applications of crowdsourcing, and summarizes the industrial crowdsourcing practices and corresponding case studies in software engineering. Finally, we reveal the trends, open issues, and challenges of future research in crowdsourced software engineering.Software crowdsourcing connotation and operation process"Crowdsourcing" was proposed by Howe in 2006. Crowdsourcing is a distributed problem-solving model that leverages swarm intelligence, and Crowdsourcing Software Engineering (CSE) is derived from crowdsourcing.Software crowdsourcingCrowdsourced software engineering refers to a model in which an undefined, potentially large-scale online worker undertakes external software engineering tasks openly, as shown in the figure, dividing the field of crowdsourced software engineering. Crowdsourcing works by recruiting a global online workforce for various types of software engineering tasks, such as requirements extraction, design, coding, and testing. This new model reduces time-to-market by increasing parallelism and reducing cost and defect rates through flexible development capabilities.Domain division of crowdsourced software engineeringSoftware crowdsourcing operation processCrowdsourced software engineering has many potential advantages over traditional software development methods. Crowdsourcing can help software development organizations integrate flexible external human resources to reduce internal employment costs and speed up the development process by utilizing a distributed production model, as shown in the main execution process for software crowdsourcing .The main execution process of software crowdsourcing The software crowdsourcing operation process follows Simon's problem-solving model, which consists of two phases: the decision phase andthe implementation phase. The decision-making phase includes three typical phases: definition, design, and selection. While the implementation phase consists of an implementation phase followed by a review phase.Definition: The problem is defined, and the requester should demonstrate motivation for adopting CSE. Analyze potential issues such as cost, efficiency and scalability, intellectual property, quality of group work, etc.Design: The design phase is concerned with the development of alternative solutions. This stage may require research into potential options. For example: the granularity of tasks, crowd incentives, scale design, etc.Selection: During the selection phase, alternatives are evaluated. The output of this stage is an achievable decision.Implementation: The implementation phase is the phase where the decision is finally executed. Both CSE researchers and practitioners need to tackle a range of problems to implement crowdsourcing campaigns. For example, what intermediary platform should be used in order to get the job done? Next, how to manage tasks and workers?Review: The final review phase evaluates the results of the implementation.The above process model can provide guidance for CSE researchers and practitioners to achieve CSE. Several questions behind each stage remain open questions, pointing to important research questions.Crowdsourcing Applications in Software EngineeringCrowdsourced applications of software engineering are presented in subsections according to software development lifecycle activities related to software engineering. It is mainly divided into the following stages: software requirements, software design, software coding, software testing and verification, software development and maintenance.Crowdsourcing of Software Requirements AnalysisRequirements analysis is a critical step that affects a software project. Traditional stakeholder analysis tools require experts to manually extract stakeholder information.To reduce the cost of relying on experts to engage with stakeholders, Lim et al. integrated support for identifying stakeholders and prioritizing their needs, a large-scale requirements acquisition method based on social network analysis and collaborative filtering techniques.Hosseini et al. focus on using crowdsourcing to obtain demand. They summarize the main features of crowdsourcing and crowdsourcing in crowdsourcing requirements engineering by reviewing the existing literature to reveal the relationship between these features and the quality of elicited requirements. Wang et al. also utilize crowdsourcing to obtain demand and propose a framework for participant recruitment based on spatiotemporal availability. Theoretical analysis and simulation experiments demonstrate the feasibility of the framework.Lay people are used to process requirements documents. Extracting requirements from large natural language text sources is a difficult task when performed manually. However, these data are often used as ground truth for evaluation. This limits the generalization of the assessment to automatic requirements extraction methods. Breaux and Schaub conducted three experiments involving hiring untrained crowd workers, manually extracting requirements from privacy policy documents. The experimental results show that with the help of the task decomposition workflow, the coverage of manual requirements extraction is increased by 16% and the cost is reduced by 60%.Group stakeholders are not only the source of requirements, but can help with requirements prioritization and release planning. To support crowdsourcing requirements engineering activities, Adepetu et al. propose a conceptual crowdsourcing platform called CrowdRequire. The platform employs a competitive model that pits groups of people against each other to submit requirements specification solutions to customer-defined tasks,discussing the platform's business model, market strategy and potential challenges such as quality assurance, intellectual property, and more.Crowdsourcing of software designIn the existing commercial crowdsourcing market, there are many platforms that support software interface design, such as DesignCrowd and Crowdsping. However, few studies report the performance of software design using crowdsourcing.Huang et al. use crowds to draw mobile application wireframes and design examples on the Internet. Other scholars have proposed a crowdsourcing system called "Phantom" to help designers prototype interactive systems in real time based on sketches and functional descriptions. Experimental results show that Phantom can achieve more than 90% accuracy on user intent, and only needs a few seconds of response time.Currently, few crowdsourcing platforms support software architecture design, among which Topcoder is one of the most widely used platforms. However, industry crowdsourcing platforms such as Topcoder have limitations in evolving designs from solutions from multiple designers. Latoza et al. let designers make preliminary designs and refinements based on solutions from others. Their research demonstrates the usefulness of recombination in crowdsourced software design. Based on their findings, some recommendations for improving software design competitions are also highlighted.Nebeling et al. also propose improved software design based on data and functionality, a contribution from the crowd. However, these designs are specific website components within the domain of web engineering. Two preliminary experiments were conducted to demonstrate the performance of the method. Crowd motivation, quality assurance, safety and intellectual property issues were also widely discussed.Crowdsourcing of software codingSoftware coding using crowdsourcing focuses on three sub-areas: crowdsourcing programming environments, program optimization, and integrated development environment (IDE) enhancements.1) Group programming environment: Crowdsourced intermediaries play a key role in managing and coordinating group workers to complete the tasks of requesters. Much research has focused on providing systems that support population-based coding tasks. Goldman proposes role-specific interfaces for coordinating collaborative crowd coding efforts. By building a real-time web-based IDE collabode, the authors aim to implement emerging highly collaborative programming models such as group programming.2) Project optimization: Crowdsourcing can also be used for compilation optimization and project integration. In software crowdsourcing, a crowdsourced adaptive compiler for JavaScript code optimization is provided. Based on application performance data collected from web clients, a compiler flag recommendation system is built in the cloud. This system is used to instruct the compiler to optimize for a certain platform. Three optimized implementations are experimented with javascript code releases for eight platforms. One of the best optimizations showed an average five-fold increase in execution speed.3) IDE enhancements: The use of community knowledge to support coding activities in integrated development environments has been extensively studied. Several tools and methods have been proposed to help developers with coding and debugging.HelpMeou is a social recommender system that aids debugging by crowdsourcing suggestions. The system has a database for coding bug fixes built by crowdsourced developers. To collect fixes, the system automatically tracks changes to the code over time and records the actions that made the buggy code bug-free.Bluefix is an online tool that deals with interpreting and understanding compiler error messages for beginners. The tool helps students fix compile-timeerrors faster, with bluefix suggesting 19.52% more accurate than helpMeout.Example over Flow is a code search system that leverages community knowledge on Q&A sites to suggest high-quality embeddable code.Seahawk is an Eclipse plugin with some similar goals to Example Overflow. It attempts to leverage popular knowledge from Q&A sites such as Stackover Flow to provide documentation and programming support.Wordmatch and Snipmatch are two search tools that help developers integrate crowdsourced code snippets. WordMatch provides an end-user programming environment that allows users (with no programming experience) to generate direct answers to search queries.Bruch proposed the concept of IDE2.0 in 2012 (based on the concept of Web2.0). Bruch shows how group knowledge can help improve multiple features such as API documentation, code completion, error detection, and code search.Using swarm knowledge to find common examples from the web has similarities to the work of automatically fetching actual test cases from web-based systems. As with the possibility of combining genetic improvement and social recommendation, this similarity also points to the possibility of a hybrid version that could draw information from a combination of populations and networks for testing purposes.Crowdsourcing of software testingCrowdsourcing of software testing is often referred to as "crowdsourced testing" or "crowdsourced testing". Compared with traditional software testing, crowdsourced software testing not only has the advantage of recruiting professional testers, but also has the advantage of end-user support for the testing task.1) Usability testing: Traditional usability testing is labor-intensive, costly and time-consuming. Recruiting an online temporary group workforce could be one way to ameliorate these issues by leveraging a large potential user base andoffering end-users long-term incentives for lower labor rates.In 2013, Nebeling et al. proposed a toolkit implementation framework call ed Crowdsourcing Research on Crowdsourcing Website Usability Testing. To identify outliers in crowdsourced usability testing results, Gomide et al. in 2014 proposed a method for automatic hesitation detection using deterministic automata. The idea is to capture the user's biofeedback through the mouse's movements and skin sensors to reveal their hesitant behavior, which is highly instructive for filtering out unconfirmed usability test results.2) Performance testing: Due to differences in user behavior and execution environments, software performance in real-world environments is difficult to test. Masson et al. proposed a method that uses crowds to measure the actual performance of software products. Research has shown that the method is useful in identifying performance issues and assisting development teams in decision making.3) GUI Testing: Automated GUI test case generation is very difficult, and manual GUI testing is too slow for many applications. Vliegendhartetal company first proposed the graphical user interface testing of multimedia applications. Crowd testers were recruited from Amazon Mechanical Turk. They were asked to A/B test the user interface via a remote virtual machine. Experimental results show that it takes less than three days and $50 to complete two functionalized GUI testing tasks (100 assigned to each task).4) Test case generation: Chen et al. propose a puzzle-based automated testing (PAT) environment for decomposing target mutation and constraint solving problems into human-solvable games. Experimental results on two open source projects show that the coverage is improved by 7.0% and 5.8% compared to the coverage of two state-of-the-art test case generation methods.5) The oracle conundrum: Pastore et al. investigate crowdsourcing to alleviate the oracle conundrum, where they crowdsource automatically generated test assertions to both Aqualized groups of workers (with programming skills) and unqualified groups of workers on Amazon MechanicalTurk. Workers were asked to judge the correctness of the assertions and to further correct erroneous assertions. The experimental results suggest that crowdsourcing is a feasible way to alleviate the prophet A conundrum, although this approach requires skilled workers to provide well-designed and documented tasks.In addition, crowdsourcing is also applied to general software evaluation and more specific quality of experience evaluation.Crowdsourcing of software maintenanceSoftware development and maintenance is one of the first areas to benefit from crowdsourcing applications. To improve scalability, Bacon et al. propose a market-based software evolution mechanism. The goal of this mechanism is not to guarantee absolute "correctness" of software, but to economically fix bugs that users care about most. The proposed mechanism allows users to bid on bug fixes (or new features) and rewards reporters, testers, and developers who respond to bugs.Software documentation plays a vital role in program understanding. In crowdsourcing, a reuse method based on object inheritance is proposed, and the feasibility of the document reuse method is confirmed, which improves the document quality and coverage [6]. Moreover, document crowdsourcing, localization crowdsourcing, etc. also greatly improve the maintainability of the software.Most existing crowdsourcing software engineering methods employ a single batch model, applying crowdsourcing to solve a well-defined single task. See the waterfall model used by existing platforms such as Topcoder, which enables rapid development of practical methodologies for massive crowdsourced development work. But this phenomenon may be temporary, and as it matures, crowdsourced software engineering may become adaptive and iterative to better model the underlying software engineering processes it supports. A recent study shows that iterative reorganization can help improve crowdsourced software design. In fact, multi-crowdsourcing softwareengineering is a natural iterative process in which each group responds to and influences the outcomes of tasks performed by other groups.In this review, the crowdsourced software development models, major commercial platforms for software engineering and corresponding case studies, and crowdsourced applications of software engineering research are summarized, providing insights into crowdsourced software engineering applications in the software development life cycle. A more fine-grained view of the domain, and summarizes the challenges, development trends, open issues, and future research directions of crowdsourced software engineering. A comprehensive review of research on crowdsourcing software engineering activities can provide broad creative and design value for crowdsourcing software engineering activities, and provide guidance for the realization and improvement of crowdsourcing software engineering frameworks by reusing existing crowdsourcing knowledge Opinion.。

内部时钟的工作原理和流程

内部时钟的工作原理和流程The internal clock of a device or system is a crucial component that helps to synchronize and coordinate various operations, ensuring smooth and efficient functioning. 内部时钟是设备或系统的关键组件，它有助于同步和协调各种操作，确保平稳高效的运行。

The working principle of an internal clock involves the generation and distribution of timing signals to different parts of the system. 内部时钟的工作原理涉及到产生和分发计时信号给系统的不同部分。

This process is essential for ensuring that different processes and components within the system are synchronized and operate in harmony. 这个过程对于确保系统内部的不同流程和组件能够同步运行非常重要。

The internal clock operates based on a crystal oscillator that generates precise oscillations at a specific frequency. 内部时钟基于晶体振荡器工作，它以特定频率产生精密的振荡。

These oscillations serve as the fundamental timing reference for the system, governing the execution of instructions and the coordination of various operations. 这些振荡作为系统的基本计时参考，管理着指令的执行和各种操作的协调。

黑格尔十句经典名言英文

黑格尔十句经典名言的英文表述1Hegel, a renowned philosopher, has left us with numerous insightful and thought-provoking quotes. Here are ten of his classic sayings and their explanations."The only thing we learn from history is that we learn nothing from history." This statement emphasizes the repetitive nature of human behavior and our failure to truly absorb the lessons of the past. It suggests that despite having access to historical knowledge, we often make the same mistakes."Truth is the whole." It implies that truth cannot be fragmented or partial; it encompasses all aspects and connections. Only by considering the entire context can we approach the truth."Spirit is the self, and the self is spirit." This reflects the idea that the human spirit and the individual self are inseparable and interrelated."Nothing great in the world has been accomplished without passion." It highlights the significance of passion as a driving force for achieving greatness."Freedom is the recognition of necessity." It means that true freedom comes from understanding and accepting the inevitable constraints and conditions."The owl of Minerva spreads its wings only with the falling of the dusk." This suggests that wisdom and understanding often come too late, after events have occurred."History is not the soil in which happiness grows. The periods of happiness are the blank pages of history." It indicates that happiness is not a constant in the course of history."Reason has cunning in history." This implies that there is an underlying rationality and purpose in historical developments, even if it may not be immediately apparent."To be independent of public opinion is the first formal condition of achieving anything great." It emphasizes the need for individuals to have their own convictions and not be swayed by popular opinion."Beauty is the manifestation of secret natural laws, which otherwise would have remained hidden from us." It suggests that beauty reveals hidden truths and patterns in nature.These quotes by Hegel offer profound insights into various aspects of human existence, philosophy, and history, inviting us to reflect and think deeply.2Hegel, one of the most influential philosophers in history, has left us with numerous profound and thought-provoking quotes that have had a significant impact on the field of philosophy. Here are ten of his classicsayings and their implications for later philosophical studies."Nothing great in the world has been accomplished without passion." This statement emphasizes the crucial role of passion in achieving great feats, suggesting that without it, significant accomplishments are unlikely. It has inspired countless individuals to pursue their dreams with enthusiasm."History teaches us that people and governments have never learned anything from history." This poignant observation highlights the tendency of humanity to repeat mistakes, raising questions about our capacity for true learning and growth."The owl of Minerva spreads its wings only with the falling of the dusk." This metaphor implies that wisdom and understanding often come only at the end of an era or process, challenging us to reflect on the timing of knowledge acquisition."Truth is in the whole." This assertion promotes the idea of looking at things in their entirety rather than in isolation, which has been a driving force behind the development of holistic philosophy. It encourages us to consider multiple perspectives and interconnected factors when seeking the truth."Reason is the sovereign of the world." This proclamation places reason at the highest position, suggesting that rationality should guide our actions and decisions."Moral ity is not the doctrine of how we may make ourselves happybut of how we may make ourselves worthy of happiness." This perspective on morality shifts the focus from immediate gratification to the development of character and virtue, having profound implications for the study of moral philosophy."The only thing we learn from history is that we learn nothing from history." This paradoxical statement forces us to confront our inability to effectively apply past lessons to the present."To be independent of public opinion is the first formal condition of achieving anything great." It emphasizes the need for individuals to have the courage to follow their own convictions, regardless of popular sentiment."Spirit is the only reality." This statement emphasizes the significance of the intangible aspects of human existence and thought.These quotes by Hegel continue to shape and inspire philosophical discourse, encouraging us to think deeply about various aspects of life, knowledge, and morality.3Hegel, a renowned philosopher, has left us with numerous thought-provoking and insightful quotes. Here are ten of his classic sayings and my personal understanding and reflections on them."The history of the world is not the theatre of happiness. Periods of happiness are blank pages in it." This statement implies that progress oftencomes through challenges and difficulties rather than constant contentment. It reminds us that hardships have the potential to drive us forward and shape history."Nothing great in the world has ever been accomplished without passion." Passion is the driving force that enables us to pursue our goals with determination and overcome obstacles along the way."Truth is the whole." It emphasizes the importance of considering all aspects of a matter to arrive at a comprehensive understanding."To be independent of public opinion is the first formal condition of achieving anything great." This encourages us to have the courage to follow our own beliefs and not be swayed by the majority."The only thing we learn from history is that we learn nothing from history." This paradoxical statement makes us question the repetitive nature of human actions and the challenges of truly learning from the past."One cannot think well, love well, sleep well, if one has not dined well." It highlights the significance of basic needs being met for a fulfilling life."The state is the actuality of the ethical idea." It underlines the role and importance of the state in upholding ethical standards."The bud disappears when the blossom breaks through, and we might say that the former is refuted by the latter; in the same way when the fruit comes, the blossom may be explained to be a false form of the plant'sexistence, for the fruit appears as its true nature in place of the blossom." This shows the process of development and transformation."Wisdom is only found in truth." It emphasizes that true wisdom stems from a pursuit and understanding of truth.These quotes by Hegel offer profound insights into various aspects of life and thought, inspiring us to think deeply and strive for wisdom and progress.4Hegel, a renowned philosopher, left behind a plethora of thought-provoking and insightful quotes. Here are ten of his classic sayings and their English expressions:"The only thing that we learn from history is that we learn nothing from history." This statement reflects Hegel's profound understanding of human nature and the repetitive patterns in history. It can be contrasted with similar viewpoints from other philosophers like Marx, who emphasized the role of economic factors in shaping historical events."Nothing great in the world has been accomplished without passion." This quote highlights the significance of passion in achieving greatness. It shares a common thread with Plato's emphasis on the pursuit of truth and beauty with intense dedication."Truth is in the whole." This assertion underlines the need for a comprehensive and holistic perspective to understand the truth. It differsfrom Descartes' approach of seeking certainty through individual reasoning."History is a rational process." Hegel's belief in the rationality of history can be compared to Confucius' idea of the natural order and moral progress in society."Freedom is the recognition of necessity." This statement challenges the common notion of freedom and invites deeper reflection. It contrasts with the liberal concept of unrestricted individual autonomy."Reason is the sovereign of the world." This proclamation emphasizes the power of reason in shaping the world. It can be juxtaposed with Aristotle's focus on practical wisdom and virtuous action."The owl of Minerva spreads its wings only with the falling of the dusk." This metaphorical expression implies that wisdom comes only after events have occurred. It contrasts with the Stoic belief in the ability to anticipate and prepare for all circumstances."The state is the actuality of the ethical idea." Hegel's view on the state's significance can be contrasted with Locke's emphasis on individual rights and limited government."The history of the world is none other than the progress of the consciousness of freedom." This perspective on historical development can be compared to Hobbes' view of the state as a means to ensure order and security.In comparing Hegel's quotes with those of other philosophers, we gaina richer understanding of the diverse and complex nature of philosophical thought.5Hegel, a profound philosopher, has left us with numerous insightful and thought-provoking quotes. Here are ten of his classic sayings and their significance in contemporary society."The only thing that we learn from history is that we learn nothing from history." This statement highlights the repetitive nature of human mistakes and urges us to truly reflect on past events to avoid similar errors in the present. It serves as a reminder that we should not merely observe history but actively draw wisdom from it to shape a better future."Nothing great in the world has ever been accomplished without passion." Passion is the driving force behind achieving greatness. In today's competitive world, it is essential to have a burning passion to pursue one's goals and overcome obstacles."The truth is in the whole." This emphasizes the importance of looking at situations holistically rather than in isolation. It has significant implications for problem-solving and decision-making in various fields."The owl of Minerva spreads its wings only with the falling of the dusk." It implies that wisdom often comes too late, but still holds value for future endeavors."Reason is the sovereign of the world." This underlines the role ofrationality in guiding human actions and shaping social structures."The history of the world is none other than the progress of the consciousness of freedom." It reflects on the evolution of human society towards greater freedom and equality."The state is the actuality of the ethical idea." This statement offers valuable insights into modern state governance, emphasizing the importance of ethical principles in shaping a just and prosperous society."Spirit is the substance and the truth; it is the unity of the subjective and the objective." Understanding the unity of spirit helps us to achieve a balanced perspective in our lives."To be independent of public opinion is the first formal condition of achieving anything great." It encourages individuals to have the courage to follow their own convictions and not be swayed by popular opinion.These quotes by Hegel continue to inspire and guide us, providing valuable perspectives for contemporary life and thought.。

Mercury NanoSWITCH产品介绍说明书

Mercury Systems is a leading commercial provider of secure sensor and safety-critical processing subsystems. Optimized for customer and mission success, Mercury’s solutions power a wide variety of criticaldefense and intelligence programs.An IGMP snooping feature enables the network to operate at peak efficiency by limiting the IP multicast traffic to the ports that request it, while 802.1Q VLAN support quickly segregates network traffic. VLANs provide an additional layer of security by separating sensitive data from other network workgroups.Workload EfficiencyWith numerous Quality of Service (QoS) features, the NanoSWITCH ensures traffic is prioritized to deliver superior performance for real-time applications. These features include system management, voice, video, and bandwidth-intensive file uploads and downloads. Additional capabilities, such as IEEE 802.1p priority tagging, DSCP , and eight hardware traffic class queues maintain quality for real-time applications.Proven with VICTORYNanoSWITCH is the only field implemented VICTORY (Vehicular Integration for C4ISR/EW Interoperability) CTS compliant switch –a software configuration that provides a common data-bus centric approach which eliminates redundancy and reduces SWAP inArmy ground vehicles. The NanoSWITCH also meets multiple military standards including: MIL-STD-1275E, MIL-STD-704F, MIL-STD-461F,and MIL-STD-810G.D A T A S HE E Tw w w .t m s .m r c y .c o mACQUIRE ACQUIRE 100101010001101011110101100DIGITIZE ACQUIRE 100101010001101011110101100DIGITIZE PROCESS STORAGE EXPLOIT DISSEMINATEACQUIRE 100101010001101011110101100DIGITIZE PROCESS STORAGE EXPLOIT ACQUIRE 100101010001101011110101100DIGITIZE PROCESS ACQUIRE 100101010001101011110101100DIGITIZE PROCESS STORAGE The NanoSWITCH brings enterprise level layer 2/3 switching into harsh environments found in military ground, air and sea vehicles and offshore oil platforms.Reliable and CompactWeighing less than 3.6lbs, the Themis NanoSWITCH™ delivers multi-layer GigE Ethernet switch capabilities with an embedded x86 PC in a compact form-factor. Its multi-layer performance and cost-competitive pricing makes it an attractive choice for a multitude of field applications including:•Vehicle network switching •Distributed architecture vehicle controller•VICTORY compliant switch, router, timing, and control •WAN – LAN interconnectivity and firewall•Shared processing and peripheral communications Featuring sealed MIL connectors, the NanoSWITCH meets IP67 standards (water, dust, salt fog) and has an operating temperature range of -40°C to 71°C.Precision ControlThe NanoSWITCH’s 10x or 16x external GigE Ethernet ports operate at rates of 10, 100, and 1000 Mbps. It supports sophisticated IPv4 and IPv6 routing such as tunneling, IP Multicast, VLANs, IETF, IEEE, and DSL Forum standards. A full management suite and Command Line Interface (CLI) is included to simplify switch control and routing operations.•Vehicle Integration for C4ISR/EW Interoperability (VICTORY) implementedRugged Small Form-Factor 10/16 Port GigE Ethernet switchNanoSWITCH ™MIL Specification Compliance• MIL-STD-1275E - Ground vehicle power • MIL-STD-704F - Aircraft power (with no hold up)• MIL-STD-461F - EMC Army ground, Navy ground • MIL-STD-810G - EnvironmentalMIL-STD-810G Environmental Compliance• IP67 environmentally sealed (water, dust, salt fog)• Sealed MIL connectors • Altitude: 15,000ft • Immersion: 1m • Dust, salt, fog• Storage temperature: -50°C to 105°C • Operating temperature: -40ºC to 71ºC • Shock: 50g, 25ms half sine, all directions• Vibration: 5G RMS 8Hz to 2KHz, composite wheeled, cargo jet, helicopter profilesIEEE CmplianceE• 802.1D bridging and spanning tree • 802.1p QOS/COS • 802.1Q VLAN tagging • 802.1w rapid spanning tree • 802.1s spanning tree protocol • 802.1AB link layer discovery protocol • 802.3ad link aggregation with LACP • 802.3x flow control • 802.3ab 1000BASE-T • 802.3z GigE EthernetManagement MIBS• Fully MIB managed device • RFC 1213 - MIB-II • Ether-like MIB• SNMP-FRAMEWORK-MIB • RFC 1493 - BRIDGE-MIB • IF-MIB • RMON-MIBVetronics SBC PC• Embedded x86 SBC• AMD Fusion APU, 615MHz single core with Radeon HD 6250 GPU • 64KB L1, 512KB L2, 1GB DRAM • 64GB SSD• Trusted Platform Module (TPM)• External GB-GRAM/DAGR/Polaris compliant GPS Port with selectable RS232/RS422/RS485• 1x Internal GigE port into Switch (17th port) and 1x External GigE • VGA video output • 2x RS-232 ports • 2x USB 2.0 ports• Replaceable long-life RTC battery or external power • Linux Ubuntu installed as standardLayer 2/3 Feature Set• 16K L2 forwarding entries • 802.1w rapid spanning tree • 802.1s spanning tree protocol • 802.3ad link aggregation/LACP • 4-16 LAGs• 802.1Q VLANs (256-4K VLANs)• 802.1AB link layer discovery protocol • Port mirroring • Jumbo frames (10KB)• 802.3x PAUSE • Static MAC addresses • IGMPv1, 2, 3 snooping • MLDv1, 2 snoopingNetwork Management• 10/100/1000 management ports • RS-232 serial console port • Syslog • RADIUS • Tacacs • AAA• Simple Network Time Protocol (SNTP)• WEB management • File download via HTTP • SNMP v1/2/3Security Features• 802.1X Port-based Network Access Control (PNAC)• MD5 encryption• Port security-MAC-based filtering • Management access control • NAP full support • TPM for SBCQuality of Service (QOS)• Priority levels 8 hardware queues• Scheduling priority queuing and Weighted Round-Robin (WRR)• Shaping per port and per queue • Rate limiting for different packet types• Class of service:Port based, 802.1p VLAN priority or IPv4/v6 IP DSCPPower• 28V nominal isolated power input to MIL-STD-1275E • +/- 250V transient, 100V surge, 12V starting surge capable • Voltage ripple filtering • 34W maximum (22-31W Typical)•Status LED blanking control。

英文合同份数条款

英文合同份数条款An English Contract: Clause on Number of CopiesThe number of copies is an essential aspect of any contract. It ensures that all parties involved possess the same document for reference and enforcement purposes. In this article, we will delve into the significance of the clause on the number of copies in an English contract.The clause on the number of copies serves to clarify the exact quantity of copies that will be issued and distributed among the parties involved. This provision helps avoid any misunderstanding or confusion regarding the distribution and possession of the contract.First and foremost, the clause stipulates that the contract shall be executed in multiple counterparts, each of which will be considered an original. This means that even if the contract is signed by the parties in separate locations or on different dates, each counterpart will have the same legal effect. Thus, each party will possess an identical version of the agreement.Furthermore, the clause will specify the exact number of counterparts that will be executed. It is common practice to arrange for two counterparts, one for each party. However, depending on the complexity and importance of the contract, the parties may agree on executing more than two counterparts. This ensures that each party has sufficient copies for their records and ease of reference.Additionally, the clause will outline the method of delivery and timing for distributing the counterparts to the respective parties. It is crucial to establish a clear process for delivering the executed copies to prevent any delay or dispute. The clause may require that the parties exchange fully executed counterparts either in person or through a reliable delivery service within a specified timeframe. This provision ensures that all parties receive the copies promptly and without any ambiguity.Moreover, the clause may address the situation in which one party fails to deliver their counterpart within the agreed timeframe. In such cases, the clause can specify theremedies available to the other party. For instance, it may grant the non-defaulting party the right to withhold performance or terminate the contract if the counterpart is not received within a certain period. This provision protects the interests of the party awaiting the counterpart and maintains the efficiency and integrity of the contractual relationship.Furthermore, the clause may address the issue of electronic copies or scanned copies of the contract. With advancements in technology, it has become common to exchange contracts through email or other electronic means. The clause can determine whether electronic copies hold the same legal weight as the physical counterparts. It may require that the parties exchange original, physical copies despite any electronic transmission for security and reliability reasons. Alternatively, the clause may stipulate that electronic copies are considered valid and enforceable, thus reducing the need for physical delivery.In conclusion, the clause on the number of copies in an English contract is a vital provision that ensures clarity, consistency, and enforceability. By specifying the quantity of counterparts to be executed, the method of delivery, and the treatment of electronic copies, this clause guarantees that all parties possess identical versions of the contract. Moreover, it provides remedies for the failure to deliver counterparts within the agreed timeframe. Adhering to this clause safeguards the interests of all parties involved and maintains the integrity of the contractual relationship.。

分布式天线协同感知的定时捕获

分布式天线协同感知的定时捕获卿朝进;魏金成;夏凌;何子述;唐友喜【期刊名称】《计算机工程与应用》【年(卷),期】2013(000)018【摘要】为提高定时捕获的正确捕获概率并降低漏检概率，提出一种基于分布式天线协同感知的定时捕获方法。

该方法针对线形小区的平坦瑞利衰落信道场景，利用两根分布式接收天线接收来自单天线移动台的发射信号；根据中心处理器处的协同感知，确保各分布式接收天线的预定虚警概率，并为门限检测推导协同处理门限；各天线根据门限检测进行分布式天线系统的最大似然定时捕获。

仿真结果表明，无论移动台处于线形小区的哪个位置，提出方法在不增加预定虚警概率的情况下，均能改善各分布式天线的正确捕获概率和漏检概率。

%To increase the probability of correct acquisition and decrease the missed detection probability, a timing acquisition method with the cooperative sensing of distributed receive antennas is proposed. In the flat Rayleigh channels of linear cell, two distributed receive antennas are employed to receive the signal transmitted from the Mobile Station(MS)with a single antenna. This paper exploits the false alarm probability at the central processor to guarantee the false alarm probability at each distributed antenna. Based on the exploited probability of false alarm at the central processor, a cooperative detection threshold of each antenna is derived for threshold detection. According to the threshold detection, a Maximum-Likelihood(ML)-based timing acquisition method is proposed for Distributed AntennaSystems(DAS). Without increasing the pre-defined probability of false alarm, the analysis and simulation results show that the correct acquisition probability and the missed detection probability for each distrib-uted antenna can be improved with the proposed method wherever the MS is located.【总页数】4页(P11-14)【作者】卿朝进;魏金成;夏凌;何子述;唐友喜【作者单位】西华大学电气信息学院，成都 610039; 电子科技大学电子工程学院，成都 611731; 电子科技大学通信抗干扰技术国家重点实验室，成都 611731;西华大学电气信息学院,成都,610039;西华大学电气信息学院,成都,610039;电子科技大学电子工程学院,成都,611731;电子科技大学通信抗干扰技术国家重点实验室,成都,611731【正文语种】中文【中图分类】TN914【相关文献】1.线形小区中分布式天线协同的定时捕获改进方法* [J], 卿朝进;夏凌;张近;何子述;唐友喜2.基于OFDM定时捕获的分布式天线位置设计 [J], 卿朝进;夏天;唐友喜;查光明3.基于分布式天线协同的OFDM粗定时同步方法 [J], 卿朝进;唐友喜;查光明4.分布式天线协同校验的定时捕获方法 [J], 卿朝进;魏金成;何子述;唐友喜5.线形小区中基于定时捕获阶段的最优天线位置设计 [J], 卿朝进;夏天;张近;夏凌因版权原因，仅展示原文概要，查看原文内容请购买。

分布式仿真系统耦合器通信故障的检测与恢复

分布式仿真系统耦合器通信故障的检测与恢复杨岩岩;黄海于【摘要】文中针对高速列车系统动力学数字化仿真平台在系统动力学仿真过程中耦合器和执行机之间数据发送量大、交换频繁而导致的通信中断、通信阻塞、信息丢包等现象，设计并实现了耦合器通信故障的检测和恢复。

分布式仿真系统因网络通信故障停止后，该设计通过多次请求、定时检测、信息重传等机制实现了仿真系统停止后接着仿真停止前的状态继续仿真计算，并对仿真系统停止后的仿真状态和仿真结果数据具有一定的保存能力，从而保证分布式仿真系统稳定、可靠的运行。

%Aiming at the phenomenon of communicationinterruption,communication blocking,information packet loss caused by big data transmission,frequent change between the coupler and execute machine in system dynamics simulation process in the high speed train coupling system dynamics digital simulation platform,designed and realized the coupler communication fault detection and recovery. Dis-tributed simulation system is topped due to the network communication fault,the design through the repeated requests,timing detection, information retransmission mechanism to realize the simulation system is continue to simulation then the state that in front of the simula-tion stop state,and the state of the simulation and the simulation results after the stop of the simulation system have certain ability to save data,so as to ensure the running of distributed simulation system is stable and reliable.【期刊名称】《计算机技术与发展》【年(卷),期】2013(000)010【总页数】4页(P204-207)【关键词】分布式计算;网络通信;网络故障;耦合器;执行机【作者】杨岩岩;黄海于【作者单位】西南交通大学信息科学与技术学院,四川成都,610031;西南交通大学信息科学与技术学院,四川成都,610031【正文语种】中文【中图分类】TP390 引言随着计算机软硬件技术的发展，计算机仿真技术广泛应用到各个科研和开发领域，但由于仿真任务的计算量越来越大和对仿真技术的高效性、精确性、可靠性等要求越来越高，也使得分布式仿真［1］成为当前仿真领域热门的研究方向之一。