实验七 数字电路综合设计

实验七：数字电路综合设计
一、实验内容：
1、可变模值计数器的设计，可变模值分别为3、5、6、8的计数器。

2、计数器同译码器混合设计：
本设计的内部描述了两个电路模块，前面一个是8421BCD编码的“二—十进制计数器”，它的输出又接到一个“8421BCD到7段数码译码器”。

二、实验结果如下
程序一如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt_variabl_3568 is
port(clk,nclr,en:in std_logic;
sel:in std_logic_vector(1 downto 0);
qout:out std_logic_vector(2 downto 0));
end cnt_variabl_3568;
architecture a of cnt_variabl_3568 is
signal count:std_logic_vector (2 downto 0);
begin
process(clk,nclr,sel)
begin
if nclr='0' then
count<="000";
elsif (clk'event and clk='1') then
if en='1'then
if sel=0 then
if count>=2 then count<="000";
else count<=count+1;
end if;
elsif sel=1 then
if count>=4 then count<="000";
else count<=count+1;
end if;
elsif sel=2 then
if count>=5 then count<="000";
else count<=count+1;
end if;
elsif sel=3 then
if count>=7 then count<="000";
else count<=count+1;
end if;
end if;
end if;
end if;
end process;
qout<=count;
end a;
结果如下图：
程序二如下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count_bcd is port
(CLK,CAI,CD:in std_logic;
CAO:out std_logic;
q:out std_logic_vector(3 downto 0);
bcd:out std_logic_vector(6 downto 0)); end count_bcd;
architecture behave of count_bcd is
signal count:std_logic_vector(3 downto 0);
signal dout:std_logic_vector(6 downto 0);
begin
p1_jishu:process(CLK,CD,CAI)
begin
if(CD='1')then
count<="0000";
elsif(CLK'event and CLK='1') then
if(CAI='1') then
if(count="1001") then
count<="0000";
else
count<=count+1;
end if;
end if;
end if;
end process;
CAO<='1' when(count=9 and CAI='1') else '0';
pr_yima:process(count)
begin
case count is
when"0000"=>dout<="1111110"; when"0001"=>dout<="0110000"; when"0010"=>dout<="1101101"; when"0011"=>dout<="1111001"; when"0100"=>dout<="0110011"; when"0101"=>dout<="1011011"; when"0110"=>dout<="1011111"; when"0111"=>dout<="1110000"; when"1000"=>dout<="1111111"; when"1001"=>dout<="1111011"; when others=>dout<="1111011"; end case;
end process;
q<=count;
bcd<=dout;
end behave;。