STAPL The Standard Template Adaptive Parallel Library
DS26502LN+;DS26502L+;中文规格书,Datasheet资料
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6.1 6.2 6.3 6.4 6.5 6.6 6.7
PINOUT...........................................................................................................................23 HARDWARE CONTROLLER INTERFACE....................................................................26
APPLICATIONS
BITS Timing Rate Conversion
ORDERING INFORMATION
PART DS26502L DS26502LN TEMP RANGE 0°C to +70°C -40°C to +85°C PIN-PACKAGE 64 LQFP 64 LQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, clicf 125
/
REV: 042208
DS26502 T1/E1/J1/64KCC BITS Element
TABLE OF CONTENTS
AB现场模块1732 ArmourBlock User Manual
User Manual1732E ArmorBlock Dual-Port EtherNet/IP 4-Point Analog Input and Output ModulesCatalog Numbers 1732E-IF4M12R, 1732E-OF4M12RImportant User InformationSolid-state equipment has operational characteristics differing from those of electromechanical equipment. SafetyGuidelines for the Application, Installation and Maintenance of Solid State Controls (publication SGI-1.1 available from your local Rockwell Automation sales office or online at /literature/) describes some important differences between solid-state equipment and hard-wired electromechanical devices. Because of this difference, and also because of the wide variety of uses for solid-state equipment, all persons responsible for applying this equipment must satisfy themselves that each intended application of this equipment is acceptable.In no event will Rockwell Automation, Inc. be responsible or liable for indirect or consequential damages resulting from the use or application of this equipment.The examples and diagrams in this manual are included solely for illustrative purposes. Because of the many variables and requirements associated with any particular installation, Rockwell Automation, Inc. cannot assume responsibility or liability for actual use based on the examples and diagrams.No patent liability is assumed by Rockwell Automation, Inc. with respect to use of information, circuits, equipment, or software described in this manual.Reproduction of the contents of this manual, in whole or in part, without written permission of Rockwell Automation, Inc., is prohibited.Throughout this manual, when necessary, we use notes to make you aware of safety considerations.Allen-Bradley, Rockwell Software, Rockwell Automation, and T echConnect are trademarks of Rockwell Automation, Inc.T rademarks not belonging to Rockwell Automation are property of their respective companies.WARNING: Identifies information about practices or circumstances that can cause an explosion in a hazardous environment, which may lead to personal injury or death, property damage, or economic loss.ATTENTION: Identifies information about practices or circumstances that can lead to personal injury or death,property damage, or economic loss. Attentions help you identify a hazard, avoid a hazard, and recognize the consequenceSHOCK HAZARD: Labels may be on or inside the equipment, for example, a drive or motor, to alert people thatdangerous voltage may be present.BURN HAZARD: Labels may be on or inside the equipment, for example, a drive or motor, to alert people that surfaces may reach dangerous temperatures.IMPORTANT Identifies information that is critical for successful application and understanding of the product.Preface Read this preface to familiarize yourself with the rest of the manual. It provides information concerning:•who should use this manual•the purpose of this manual•related documentation•conventions used in this manualWho Should Use this Manual Use this manual if you are responsible for designing, installing, programming, or troubleshooting control systems that use 1732E ArmorBlock Dual Port EtherNet/IP Dual-Port 4-Point Analog Input and Output Modules.Purpose of this Manual This manual is a reference guide for the 1732E-IF4M12R, 1732E-OF4M12Rmodules. It describes the procedures you use to install, wire, configure,troubleshoot, and use your module.Related DocumentationThe following documents contain additional information concerning RockwellAutomation products. T o obtain a copy, contact your local Rockwell Automationoffice or distributor.Common Techniques Used in this Manual The following conventions are used throughout this manual:•Bulleted lists such as this one provide information, not procedural steps.•Numbered lists provide sequential steps or hierarchical information.•Italic type is used for emphasis.Resource Description1732E ArmorBlock™ Dual-Port EtherNet/IP 4-Point Analog Modules 1732E-WD003Information on wiring the ArmorBlock Dual-Port EtherNet/IP 4-Point Analog Modules (1732E-IF4M12R, 1732E-OF4M12R, 1732E-IT4IM12R,1732E-IR4IM12R).1732E ArmorBlock Dual-Port EtherNet/IP 4-Point Analog Inputand Output Installation Instructions, publication 1732E-IN006Information on installing the ArmorBlock EtherNet/IP module.EtherNet/IP Embedded Switch Technology Application Guide, publication ENET-AP005A manual on how to install, configure and maintain linear and Device-level Ring (DLR) networks using Rockwell Automation EtherNet/IP devices with embedded switch technology.EtherNet/IP Modules in Logix5000 Control Systems User Manual, publication ENET-UM001A manual on how to use EtherNet/IP modules with Logix5000 controllers and communicate with various devices on the Ethernet network.Getting Results with RSLogix5000™, publication 9399-RLD300GR Information on how to install and navigate RSLogix 5000. The guide includes troubleshooting information and tips on how to use RSLogix 5000 effectively.Allen-Bradley Industrial Automation Glossary, AG-7.1 A glossary of industrial automation terms and abbreviations.Notes:Table of Contents PrefaceWho Should Use this Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Common Techniques Used in this Manual. . . . . . . . . . . . . . . . . . . . . . . . . . iii Chapter 1Overview of the 1732E ArmorBlock Analog Input and Output Modules Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Physical Features of Your Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Types of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Hardware/Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Input and Output Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Alarms/Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Process Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Clamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Overrange and Underrange Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chapter Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chapter 2Install Your ArmorBlock Module Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Install the Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Set the Network Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Mount the Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Wire the Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chapter 3Configure Your Analog Input and Output Modules with RSLogix5000 Software Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Set Up the Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Create the Example Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Configure Your I/O Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 RSLogix5000 Configuration Software . . . . . . . . . . . . . . . . . . . . . . . . . 16 Overview of the Configuration Process through RSLogix 5000. . . . . . . 16 Add a New Bridge and Module to Your RSLogix5000 Project . . . . . . . 16 Add the Local EtherNet/IP Bridge to the I/O Configuration . . . . 17 Add the I/O module as a child of the 1756-EN2T module . . . . . . . 18 Download the Program to Your Controller . . . . . . . . . . . . . . . . . . . . . . . . 21 Edit Your 1732E-IF4M12R Configuration. . . . . . . . . . . . . . . . . . . . . . . . . 21 General Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table of ContentsConnection Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Configuration Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Alarm Configuration Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Internet Protocol Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Calibration Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Edit Your 1732E-OF4M12R Configuration. . . . . . . . . . . . . . . . . . . . . . . . 30General Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Connection Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Configuration Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Limits Configuration Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Fault/Program Action Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Internet Protocol Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Calibration Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Status and Monitoring Tabs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Chapter Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Chapter 4Configurable Features for the Analog Input and Output Modules Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Configurable Features for the 1732E-IF4M12R Input Module. . . . . . . 45 Input Types and Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Digital Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 High Engineering/Low Engineering. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Real-time Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Process Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Configurable Features for the 1732E-OF4M12R Output Module. . . . 48 Output Types and Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 High Engineering/Low Engineering. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Fault Mode and Program Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Clamping/Limiting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Data Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Chapter Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Chapter 5Calibrate Your Modules Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Difference of Calibrating an Input Module and an Output Module. . . 57Calibrate in Program or Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Calibrate the Input Module (1732E-IF4M12R). . . . . . . . . . . . . . . . . . . . . 58Calibrate the Output Module (1732E-OF4M12R). . . . . . . . . . . . . . . . . . 62Current Meter Calibrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Voltage Meter Calibrations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Chapter Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Table of ContentsChapter 6Troubleshoot the Modules Interpret Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Check for Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Appendix ASpecifications General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Certifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Appendix B1732E ArmorBlock Embedded Web Server Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Browser Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Access the Home Page of the Web Server. . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Log On to the Web Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Navigate the 1732E ArmorBlock I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Access Diagnostic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Access Configuration Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Appendix CModule Tag Definitions Module Tags for 1732E-IF4M12R . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Module Tags for 1732E-OF4M12R . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Access the Module Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 IndexTable of ContentsChapter 1Overview of the 1732E ArmorBlock Analog Input and Output ModulesOverview This chapter provides an introduction to the features and functionalities of the1732E ArmorBlock Analog Input and Output Modules, 1732E-IF4M12R and 1732E-OF4M12R. It includes the following sections:Module Features ArmorBlock analog I/O modules are interface modules that convert analogsignals to digital values for inputs and convert digital values to analog signals for outputs. Controllers can then use these signals for control purposes.By using the producer/consumer network model, ArmorBlock analog I/O modules produce information when needed.Some of the module features are as follows:•multiple preset ranges of voltage or current inputs/outputs•process alarms and limits•overrange and underrange detection•digital filter for 1732E-IF4M12RFor more information about module features, see Configurable Features for the Analog Input and Output Modules on page 43.You must use RSLogix 5000 to configure these features. For a more detailed how-to-configure guide, read the chapter, Configure Y our Analog Input and Output Modules with RSLogix 5000 Software on page 13.TopicPage Module Features1Physical Features of Your Modules2Types of Modules3Hardware/Software Compatibility3Input and Output Types3Alarms/Limits3Digital Filters 5Chapter 1 Overview of the 1732E ArmorBlock Analog Input and Output ModulesPhysical Features of Your Modules The modules have the following components:•Node address switches•Connectors (two EtherNet/IP D-code M12 connectors, two micro-style Power in/out connectors, four I/O M12 connectors)•Status indicators (Link, I/O, Module, Network, and Auxiliary power status indicators)•Functional earth groundPhysical Features of 1732E-IF4M12R and 1732E-OF4M12R Modules(1)Functional Earth grounds the I/O block’s EtherNet/IP communication circuitry which is designed to mitigate theeffect of noise on the network. The device requires a solid earth ground connection, either through a metal screw to a grounded metal panel or through a wire.45871Node address switchesM12 connector(1)Overview of the 1732E ArmorBlock Analog Input and Output Modules Chapter 1Types of Modules The Analog Input and Output modules are as follows.Hardware/Software Compatibility The module and the applications described in this manual are compatible withthe following firmware versions and software releases.Input and Output Types The 1732E-IF4M12R module supports four input channels, while the1732E-OF4M12R supports four output channels. Each of the four input/output channels can be configured as either current or voltage input/output, with current mode as default configuration.You can select from a series of operational ranges for each channel. The range designates the minimum and maximum signals that are detectable by the module.T o use an input or output as a current or voltage device, you must:•wire the input/output connector for the correct input type (see page 10)•configure the input/output as current or voltage via RSLogix 5000 (see page 25 and page 35)Alarms/Limits The modules are capable of generating the following alarms:•process alarms (low, low-low, high, high-high) for 1732E-IF4M12R •clamp/limits alarm for 1732E-OF4M12R Catalog NumberDescription Network Connector Power Connector 1732E-IF4M12R24V DC power, 4-Point Analog Input, Dual-Port EtherNet/IP Module Dual D-code M12Dual 4-pin micro1732E-OF4M12R 24V DC power, 4-Point Analog Output, Dual-Port EtherNet/IP Module ProductFirmware Version / Software Release 1732E-IF4M12R and 1732E-OF4M12RFirmware rev. 1.1 or later 1756-EN2T, 1756-EN2TR, 1756-EN3TR3.x version when using RSLogix 5000 v20 or later RSLogix 5000 software20 or later RSLinx software 2.56 or laterInput/Output Ranges for 1732E-IF4M12R and 1732E-OF4M12RModuleInput/Output range 1732E-IF4M12R0…20 mA 4…20 mA 0…10 V -10…10 V 0…5 V -5…5 V1732E-OF4M12RChapter 1 Overview of the 1732E ArmorBlock Analog Input and Output ModulesProcess AlarmsThe following level alarms are available for the for 1732E-IF4M12R module:•Low•Low-Low•High•High-HighWhen the channel input goes below a low alarm or above a high alarm, a bit is setin the data table. All Alarm Status bits can be read individually or by reading theChannel Status Byte (see page48).You can configure each channel alarm individually. See Alarm Configuration Tabon page26 to learn how to configure the alarms.ClampingClamping limits the output from the analog module to remain within a rangeconfigured by the controller, even when the controller commands an outputoutside that range. This safety feature sets a high clamp and a low clamp.Once clamps are determined for a module, any data received from the controllerthat exceeds those clamps sets an appropriate limit alarm and transitions theoutput to that limit but not beyond the requested value.Clamping alarms can be disabled or latched on a per channel basis.T o learn how to set clamp limits, see Limits Configuration Tab on page36.Overrange and Underrange DetectionThis feature detects when the input module is operating beyond limits set by theinput range. For example, if you are using the 1732E-IF4M12R module in the0V…10V input range and the module voltage increases to 11V, the overrangedetects this condition.The table shows the input ranges of the input module and the lowest/highestsignal available in each range before the module detects an underrange/overrangecondition.Lowest and Highest Signal for Overrange and Underrange DetectionAvailable Range Lowest Signal in Range Highest Signal in Range0…20 mA0 mA20 mA4…20 mA 4 mA20 mA0…10 V0 V10 VOverview of the 1732E ArmorBlock Analog Input and Output Modules Chapter 1Digital Filters The 1732E-IF4M12R module also supports a digital filter to smooth input datanoise transients on each input channel. This value specifies the time constant for a digital first order lowpass filter on the input. It is specified in units ofmilliseconds. A value of 0 disables the filter.T o learn more about digital filter, see page 44.Chapter Summary In this chapter, you were introduced to the features of the ArmorBlock AnalogInput and Output modules.-10…10 V-10 V 10 V 0…5 V0 V 5 V -5…5 V -5 V 5 VLowest and Highest Signal for Overrange and Underrange DetectionAvailable RangeLowest Signal in Range Highest Signal in RangeChapter 1 Overview of the 1732E ArmorBlock Analog Input and Output Modules Notes:Chapter 2Install Your ArmorBlock ModuleOverview This chapter shows you how to install and wire the 1732E ArmorBlock Dual Port4-Point EtherNet/IP Analog Input and Output modules. The only tools you require are a flat or Phillips head screwdriver and drill. This chapter includes the following topics:Install the Module T o install the module:•Set the network address•Mount the module•Connect the I/O, Network, and Auxiliary cables to the module.Set the Network AddressThe I/O block ships with the rotary switches set to 999 and DHCP enabled. T o change the network address, you can do one of the following:•adjust the node address switches on the front of the module.•use a Dynamic Host Configuration Protocol (DHCP) server, such as Rockwell Automation BootP/DHCP.•retrieve the IP address from nonvolatile memory.The I/O block reads the switches first to determine if the switches are set to a valid number. T o set the network address:1.Remove power.2.Remove the switch dust caps.3.Rotate the three (3) switches on the front of the module using a small blade screwdriver.4.Line up the small notch on the switch with the number setting you wish to use.Valid settings range from 001…254.TopicsPage Install the Module7Set the Network Address7Mount the Module9Wire the Module 10Chapter 2 Install Your ArmorBlock Module5.Replace switch dust caps. Make sure not to over tighten.6.Reapply power.7.Record IP address on product label found on the side of enclosure.Set Network Address When the switches are set to a valid number, the I/O block’s IP address is 192.168.1.xxx, where xxx represents the number set on the switches. The I/O block’s subnet mask is 255.255.255.0 and default gateway address is set to 192.168.1.1. When the I/O block uses the network address set on the switches, the I/O block does not have a host name assigned to it or use any Domain Name Server.If the switches are set to an invalid number (for example, 000 or a value greater than 254 excluding 888), the I/O block checks to see if DHCP is enabled. If DHCP is enabled, the I/O block asks for an address from a DHCP server. The DHCP server also assigns other T ransport Control Protocol (TCP) parameters. (The modules are shipped with the network switches set to 999.)If DHCP is not enabled, the I/O block uses the IP address (along with other TCP configurable parameters) stored in nonvolatile work Address Switch value 001The module IP address cannot be the same as the gateway address. If the address switches are set to 001, the module IP address becomes 192.168.1.1, which is the same as the default gateway address. In this case, the module gateway address will be set to 0.0.0.0. Default Factory Configuration The switch value 888 resets the module to default factory configuration on power up. The module will not operate properly when powered up with this setting. The switches must be set to a different (and valid) value and then power cycled after a reset.While in reset state, the module LED flashes red and the network LED goes off.Example shows network switches set at 163, which sets the module IP address to 192.168.1.163.44233Note: You need to remove the protective switch dust caps before you can adjust the address settings.Install Your ArmorBlock Module Chapter 2Mount the Module Two sets of mounting holes are used to mount the module directly to a panel ormachine. Mounting holes accommodate #6 (M3) pan head screws. The torque specification is 0.68Nm (6 lb-in.).T o mount the module on a wall or panel, use the screw holes provided in the module. Refer to the drilling dimensions illustration to guide you in mounting the module.Mounting DimensionsInstall the mounting base as follows:y out the required points as shown above in the drilling dimensiondrawing.2.Drill the necessary holes for #6 (M3) pan head screws.3.Mount the module using #6 (M3) screws.Functional Earththrough a wire.Chapter 2 Install Your ArmorBlock ModuleMount the Module in High Vibration Areas If you mount the module in an area that is subject to shock or vibration, we recommend you use a flat and a lock washer to mount the module. Mount the flat and the lock washer as shown in the mounting illustration. T orque the mounting screws to 0.68 Nm (6 lb-in.).High Vibration Area Mounting Wire the ModuleThe 1732E-IF4M12R, 1732E-OF4M12R ArmorBlock EtherNet/IP modules have 5-pin micro-style M12 I/O connectors. We provide caps to cover the unused connectors on your module. Connect the quick-disconnect cord sets you selected for your module to the appropriate ports.I/O Connectors (1)Micro-style M12 5-Pin Input Female Connector – 1732E-IF4M12R Micro-style M12 5-Pin Input Female Connector – 1732E-OF4M12R(1)Only 4 of the 5 pins are active. The center pin (5) is internally tied to signal ground to minimize external noise pickup.(View into connector)Pin 1 Current Input +Pin 2 Current Common Pin 3 Voltage Input +Pin 4 Voltage Common Pin 5 No Connect(View into connector)Pin 1Current Output +Pin 2Current Common Pin 3Voltage Output +Pin 4Voltage Common Pin 5No ConnectInstall Your ArmorBlock Module Chapter 2Ethernet ConnectorD-Code Micro Network Female ConnectorPower ConnectorsAttach the mini-style 4-pin connector to the mini-style 4-pin receptacle as shown below.Micro-style 4-Pin Input Male ReceptacleThe power required by the module is based on a 4-pin micro-style connector system. Power can be daisy chained through the module either left to right or right to left. The standard configuration is with Module/Auxiliary power entering the module on the left connector.IMPORTANT Use the 1585D–M4DC–H: Polyamide small body unshielded matingconnectors for the D-Code M12 female network connector.Note that the distance between the center of each Ethernet connectoris 16.2 mm (see Mounting Dimensions on page 9).Rockwell Automation recommends the use of suitable cable based onthis measurement. Some of the recommended cables are 1585D-M4TBJM-x and 1585D-M4TBDM-x for daisychains.IMPORTANTUse two twisted pair CAT5E UTP or STP cables.(View into connector 1)Pin 1M12_Tx+Pin 2 M12_Rx+Pin 3 M12_Tx-Pin 4 M12_Rx-Pin 5 Connector shell shield GNDD-Code M12 PinWire Color Signal 8-way Modular RJ45 Pin 1White-orange TX+12White-green RX+33Orange TX-24Green RX-6(View into receptacle)Pin 1 Auxiliary power+Pin 2 Module power+Pin 3 Module power-Pin 4 Auxiliary power-Male Input。
A pre-Selection Routing Scheme for Virtual Circuit Networks
1
Introduction
2
Review ofrks can be classified into two basic categories: datagram networks and virtual circuit networks [1]. In datagram networks, data packets are routed individually, and may take different paths towards the destination. In virtual circuit (VC) networks, data packets are routed in order along a fixed path between the source node and the destination node. The most well-known form of a VC network is Asynchronous Transfer Mode (ATM). ATM networks offer an increased capacity to handle a wide variety of applications such as data, voice, and video with quality of service (QoS) requirements. In VC networks, the routing problem consists of selecting the best path among all the available candidate paths between the source and destination nodes. When a source node requests a VC to a destination node, the source node uses its current view of the network state and its routing algorithm to select an entire path to the destination node that appears to be capable of supporting the requested QoS. The chosen path is encoded in a connection setup message. The VC setup message is then sent over the selected path to reserve the necessary resources
IEEE Std 1164_1993
IEEE Std 1164-1993 IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)SponsorDesign Automation Technical Committeeof theIEEE Computer SocietyApproved March 18, 1993IEEE Standards BoardAbstract: This standard is embodied in the Std_logic_1164 package declaration and the semantics of the Std_logic_1164 body. An annex is provided to suggest ways in which one might use this package.Keywords: Std_logic_1164, VHDL model interoperabilityIEEE Standards documents are developed within the Technical Committees of the IEEE Societies and the Standards Coordinating Committees of the IEEE Standards Board. Members of the committees serve voluntarily and without compensation. They are not necessarily members of the Institute. The standards developed within IEEE represent a consensus of the broad expertise on the subject within the Institute as well as those activities outside of IEEE that have expressed an interest in partici-pating in the development of the standard.Use of an IEEE Standard is wholly voluntary. The existence of an IEEE Standard does not imply that there are no other ways to produce, test, measure, purchase, mar-ket, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, the viewpoint expressed at the time a standard is approved and issued is subject to change brought about through developments in the state of the art and com-ments received from users of the standard. Every IEEE Standard is subjected to review at least every Þve years for revision or reafÞrmation. When a document is more than Þve years old and has not been reafÞrmed, it is reasonable to conclude that its contents, although still of some value, do not wholly reßect the present state of the art. Users are cautioned to check to determine that they have the latest edition of any IEEE Standard.Comments for revision of IEEE Standards are welcome from any interested party, regardless of membership afÞliation with IEEE. Suggestions for changes in docu-ments should be in the form of a proposed change of text, together with appropriate supporting comments.Interpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate to speciÞc applications. When the need for interpretations is brought to the attention of IEEE, the Institute will initiate action to prepare appro-priate responses. Since IEEE Standards represent a consensus of all concerned inter-ests, it is important to ensure that any interpretation has also received the concurrence of a balance of interests. For this reason IEEE and the members of its technical com-mittees are not able to provide an instant response to interpretation requests except in those cases where the matter has previously received formal consideration.Comments on standards and requests for interpretations should be addressed to:Secretary, IEEE Standards Board445 Hoes LaneP.O. Box 1331Piscataway, NJ 08855-1331USAIntroduction[This introduction is not a part of IEEE Std 1164-1993, IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164).]This package provides a standard datatype system for the declaration of ports and signals used in modeling digital components in VHDL. Use of this package with its deÞned logic values and operators is intended to provide a mechanism for writing VHDL component models that have well-deÞned behavior when connected to other models adhering to this standard.Development of the Std_logic_1164 package:The work of this committee is the culmination of efforts by several groups with the same goals working over a period of over three years. The EIA (Electronic Industries Association) and the VDEG (VHDL Design Exchange Group) have been working on the problem of interoperable VHDL component models since the standardization of VHDL by the IEEE in 1987. The work at the EIA has been guided by John Wilner, Jack Kinn, and Len Finegold in their efforts to produce a speciÞcation for procuring interoperable VHDL compo-nent models. The work at the VDEG was guided by Moe Shahdad, Ghulam Nurie, and its last chair, Victor Berman, who merged this group with the IEEE Model Standards Group in order to promote a uniÞed stan-dard. The VDEG group has since disbanded. At present there is agreement by the IEEE P1164 and EIA 567 groups on this standard.Between 1989 and this date, many individuals made valuable contributions to the development of this stan-dard. At the time of approval of the standard, the members of the working group were:William Billowitch,ChairDavid Ackley Andrew Guyler Zainalabedin NavabiGordon Adshead William A. Hanna Sivaram NayuduShishir Agarwal John Hillawi Wolfgang W. NebelDavid G. Agnew Robert Hillman Lawrence J. OÕConnellJames R. Armstrong Frederick Hinchliffe Jan PukiteDaniel S. Barclay John Hines Eric John PurslowVictor Berman Elchanan Herzog SrinivasRaghvendraThomas H. Borgstrom Andreas Hohl Paul RamondettaMark Brown Andy Huang Deborah L. RooneyWalter H. Buckhardt Gongwen Huang Jacques RouillardScott Calhoun Mitsuaki Ishikawa Ashraf M. SalemDavid M. Cantwell Takashi Kambe Larry F. SaundersSteven Carlson Stanley J. Krolikoski Paul ScheidtHarold W. Carter Stephen Kun Kenneth E. ScottMoon Jung Chung Howard K. Lane Moe ShadadDavid Coelho Rick Lazansky Lee A. ShombertTedd Corman Jean Lebrun David W. SmithAllen Dewey Oz Levia Alec G. StanculescuMichael Dukes Alfred Lowenstein Balsha R. StanisicLen Finegold Joseph F.P. Luhukay Jose A. TorresJacques P. Flandrois Don MacMillen Joseph G. TrontAlain Fonkoua F.Eric Marschner Cary UsseryGeoffrey Frank William S. McKinney Radha VaidyanathanGary Gaugler Paul J. Menchini James H. VellengaAlfred S. Gilman Jean Mermet Ranganadha VemuriEmil Girczyc Gerald T. Michael Karen E. WatkinsRita Glover Gabe Moretti Ronald WaxmanBrent Gregory Wolfgang Mueller Francis WiestBrian GrifÞn John WinklerLawrence T. Groves Alex ZamÞrescuiiiivThe following persons were on the balloting committee that approved this document for submission to the IEEE Standards Board:When the IEEE Standards Board approved this standard on March 18, 1993, it had the following member-ship:Marco W. Migliaro, Chair Donald C. Loughry, Vice ChairAndrew G. Salem, SecretaryDennis BodsonDonald N. Heirman T. Don Michael*Paul L. BorrillBen C. Johnson John L. Rankine Clyde CampWalter J. Karplus Wallace S. Read Donald C. FleckensteinIvor N. Knight Ronald H. Reimer Jay Forster*Joseph KoepÞnger*Gary S. Robinson David F. FranklinIrving Kolodny Martin V . Schneider Ramiro GarciaD. N. ÒJimÓ Logothetis Terrance R. Whittemore Thomas L. HannanLawrence V . McCall Donald W. Zipse*Member Emeritus Also included are the following nonvoting IEEE Standards Board liaisons:Satish K. AggarwalJames BeallRichard B. EngelmanDavid E. SoffrinStanley WarshawAdam H. SickerIEEE Standards Project EditorDavid Ackley Andrew Guyler Zainalabedin Navabi Gordon Adshead William A. Hanna Sivaram Nayudu Shishir Agarwal John Hillawi Wolfgang W. Nebel David G. Agnew Robert Hillman Lawrence J. OÕConnell James R. Armstrong Frederick Hinchliffe Jan Pukite Daniel S. Barclay John Hines Eric John Purslow Victor Berman Elchanan Herzog SrinivasRaghvendra Thomas H. Borgstrom Andreas Hohl Paul Ramondetta Mark Brown Andy Huang Deborah L. Rooney Walter H. Buckhardt Gongwen Huang Jacques Rouillard Scott Calhoun Mitsuaki Ishikawa Ashraf M. Salem David M. Cantwell Takashi Kambe Larry F. Saunders Steven Carlson Stanley J. Krolikoski Paul Scheidt Harold W. Carter Stephen Kun Kenneth E. Scott Moon Jung Chung Howard K. Lane Moe Shadad David Coelho Rick Lazansky Lee A. Shombert Tedd Corman Jean Lebrun David W. Smith Allen Dewey Oz Levia Alec G. Stanculescu Michael Dukes Alfred Lowenstein Balsha R. Stanisic Len Finegold Joseph F.P. Luhukay Jose A. Torres Jacques P. Flandrois Don MacMillen Joseph G. Tront Alain Fonkoua F.Eric Marschner Cary Ussery Geoffrey Frank William S. McKinney Radha Vaidyanathan Gary Gaugler Paul J. Menchini James H. Vellenga Alfred S. Gilman Jean Mermet Ranganadha Vemuri Emil Girczyc Gerald T. Michael Karen E. Watkins Rita Glover Gabe Moretti Ronald Waxman Brent Gregory Wolfgang Mueller Francis Wiest Brian GrifÞn John Winkler Lawrence T. Groves Alex ZamÞrescuContentsCLAUSE PAGE 1.Overview (1)1.1Scope (1)1.2Conformance with this standard (1)2.Std_logic_1164 package declaration (2)3.Std_logic_1164 package body (4)Annex A Using the Std_logic_1164 Package (15)A.1Value system (15)A.2Handling strengths (15)A.3Use of the uninitialized value (15)A.4Behavioral modeling for 'U' propagation (16)A.5'U's related to conditional expressions (16)A.6Structural modeling with logical tables (16)A.7X-handling: assignment of XÕs (16)A.8Modeling with donÕt careÕs (16)A.9Resolution function (17)A.10 Using Std_ulogic vs. Std_logic (17)vIEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)1. Overview1.1 ScopeThis standard is embodied in the Std_logic_1164 package declaration and the semantics of the Std_logic_1164 package body along with this clause 1 documentation. The information annex A is a guide to users and is not part of this standard, but suggests ways in which one might use this package.1.2 Conformance with this standardThe following conformance rules shall apply as they pertain to the use and implementation of this standard:a)No modiÞcations shall be made to the package declaration whatsoever.b)The Std_logic_1164 package body represents the formal semantics of the implementation of theStd_logic_1164 package declaration. Implementers of this package body may choose to simply compile the package body as it is; or they may choose to implement the package body in the most efÞcient form available to the user. Users shall not implement a semantic that differs from the formal semantic provided herein.1IEEEStd 1164-1993IEEE ST ANDARD MULTIVALUE LOGIC SYSTEM FOR22. Std_logic_1164 package declaration-- ---------------------------------------------------------------------- -- Title : Std_logic_1164 multivalue logic system -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE model standards group (par 1164) -- Purpose : This packages defines a standard for designers -- : to use in describing the interconnection data types -- : used in VHDL modeling.-- :-- Limitation: The logic system defined in this package may -- : be insufficient for modeling switched transistors,-- : since such a requirement is out of the scope of this -- : effort. Furthermore, mathematics, primitives,-- : timing standards, etc. are considered orthogonal -- : issues in relation to this package and are therefore -- : beyond the scope of this effort.-- : -- Note : No declarations or definitions shall be included in,-- : or excluded from, this package. The "package declaration"-- : defines the types, subtypes, and declarations of -- : Std_logic_1164. The Std_logic_1164 package body shall be -- : considered the formal definition of the semantics of -- : this package. Tool developers may choose to implement -- : the package body in the most efficient manner available -- : to them.-- :-- ---------------------------------------------------------------------- modification history :-- ---------------------------------------------------------------------- version | mod. date:|-- v4.200 | 01/02/92 |-- --------------------------------------------------------------------PACKAGE Std_logic_1164 IS ------------------------------------------------------------------- -- logic state system (unresolved) ------------------------------------------------------------------- TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); ------------------------------------------------------------------- -- unconstrained array of std_ulogic for use with the resolution function ------------------------------------------------------------------- TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; ------------------------------------------------------------------- -- *** industry standard logic type *** ------------------------------------------------------------------- SUBTYPE std_logic IS resolved std_ulogic; ------------------------------------------------------------------- -- unconstrained array of std_logic for use in declaring signal arrays ------------------------------------------------------------------- TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; ------------------------------------------------------------------- -- common subtypes ------------------------------------------------------------------- SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1') SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z') SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1') SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z') ------------------------------------------------------------------- -- overloaded logical operators ------------------------------------------------------------------- FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;IEEE VHDL MODEL INTEROPERABILITY (Std_logic_1164)Std 1164-19933FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;-- FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "not" ( l : std_ulogic ) RETURN UX01; ------------------------------------------------------------------- -- vectorized overloaded logical operators ------------------------------------------------------------------- FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;-- ------------------------------------------------------------------------- Note : The declaration and implementation of the "xnor" function is -- specifically commented until a time at which the VHDL language has been -- officially adopted as containing such a function. At such a point,-- the following comments may be removed along with this notice without -- further "official" balloting of this Std_logic_1164 package. It is -- the intent of this effort to provide such a function once it becomes -- available in the VHDL standard.-- ------------------------------------------------------------------------- FUNCTION "xnor" ( l, r : std_logic_vector ) RETURN std_logic_vector;-- FUNCTION "xnor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector; FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector; ------------------------------------------------------------------- -- conversion functions ------------------------------------------------------------------- FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT; FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic; FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector; FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector; ------------------------------------------------------------------- -- strength strippers and type converters ------------------------------------------------------------------- FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector; FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION To_X01 ( s : std_ulogic ) RETURN X01; FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_X01 ( b : BIT ) RETURN X01; FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector; FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z; FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_X01Z ( b : BIT ) RETURN X01Z; FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector; FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01; FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_UX01 ( b : BIT ) RETURN UX01; ------------------------------------------------------------------- -- edge detection ------------------------------------------------------------------- FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; ------------------------------------------------------------------- -- object contains an unknown ------------------------------------------------------------------- FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN; FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN; FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN; END Std_logic_1164;IEEEStd 1164-1993IEEE ST ANDARD MULTIVALUE LOGIC SYSTEM FOR43. Std_logic_1164 package body-- ------------------------------------------------------------------------ Title : Std_logic_1164 multivalue logic system -- Library : This package shall be compiled into a library -- : symbolically named IEEE.-- : -- Developers: IEEE model standards group (par 1164)-- Purpose : This package defines a standard for designers -- : to use in describing the interconnection data types -- : used in VHDL modeling.-- :-- Limitation: The logic system defined in this package may -- : be insufficient for modeling switched transistors,-- : since such a requirement is out of the scope of this -- : effort. Furthermore, mathematics, primitives,-- : timing standards, etc., are considered orthogonal -- : issues in relation to this package and are therefore -- : beyond the scope of this effort.-- : -- Note : No declarations or definitions shall be included in,-- : or excluded from this package. The "package declaration"-- : defines the types, subtypes and declarations of -- : Std_logic_1164. The Std_logic_1164 package body shall be -- : considered the formal definition of the semantics of -- : this package. Tool developers may choose to implement -- : the package body in the most efficient manner available -- : to them.-- :-- -------------------------------------------------------------------- -- modification history : -- -------------------------------------------------------------------- -- version | mod. date:|-- v4.200 | 01/02/91 | -- --------------------------------------------------------------------PACKAGE BODY Std_logic_1164 IS ------------------------------------------------------------------- -- local types ------------------------------------------------------------------- TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic; TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- CONSTANT resolution_table : stdlogic_table := ( -- --------------------------------------------------------- -- | U X 0 1 Z W L H - | | -- --------------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | );FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS VARIABLE result : std_ulogic := 'Z'; -- weakest state default BEGIN -- the test for a single driver is essential; otherwise, the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. IF (s'LENGTH = 1) THEN RETURN s(s'LOW); ELSE FOR i IN s'RANGE LOOP result := resolution_table(result, s(i)); END LOOP; END IF; RETURN result; END resolved;------------------------------------------------------------------- -- tables for logical operations------------------------------------------------------------------- -- truth table for "and" functionCONSTANT and_table : stdlogic_table := (-- ------------------------------------------------------ | U X 0 1 Z W L H - | | -- ----------------------------------------------------( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | );-- truth table for "or" functionCONSTANT or_table : stdlogic_table := (-- ------------------------------------------------------ | U X 0 1 Z W L H - | | -- ----------------------------------------------------( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - | );-- truth table for "xor" functionCONSTANT xor_table : stdlogic_table := (-- ------------------------------------------------------ | U X 0 1 Z W L H - | | -- ----------------------------------------------------( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | );-- truth table for "not" functionCONSTANT not_table: stdlogic_1d :=-- --------------------------------------------------- | U X 0 1 Z W L H - |-- -------------------------------------------------( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );------------------------------------------------------------------- -- overloaded logical operators ( with optimizing hints )------------------------------------------------------------------- FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 ISBEGINRETURN (and_table(l, r));END "and";FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 ISBEGINRETURN (not_table ( and_table(l, r)));END "nand";FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 ISBEGINRETURN (or_table(l, r));END "or";FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 ISBEGINRETURN (not_table ( or_table( l, r )));END "nor";FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 ISBEGINRETURN (xor_table(l, r));END "xor";。
Statemate仿真参考手册说明书
三自由度机械手毕业设计
摘要机械手是在自动化生产过程中使用的一种具有抓取和移动工件功能的自动化装置,由其控制系统执行预定的程序实现对工件的定位夹持。
完全取代了人力,节省了劳动资源,提高了生产效率。
本设计以实现铣床自动上下料为目的,设计了个水平伸缩距为200mm,垂直伸缩距为200mm具有三个自由度的铣床上下料机械手。
机械手三个自由度分别是机身的旋转,手臂的升降,以及机身的升降。
在设计过程中,确定了铣床上下料机械手的总体方案,并对铣床上下料机械手的总体结构进行了设计,对一些部件进行了参数确定以及对主要的零部件进行了计算和校核。
以单片机为控制手段,设计了机械手的自动控制系统,实现了对铣床上下料机械手的准确控制。
关键词:机械手;三自由度;上下料;单片机AbstractManipulator , an automation equipment with function of grabbing and moving the workpiece ,is used in an automated production process.It perform scheduled program by the control system to realize the function of the positioning of the workpiece clamping. It completely replace the human, saving labor resources, and improve production efficiency.This design is to achieve milling automatic loading and unloading .Design a manipulator with three degrees of freedom and 200mm horizontal stretching distance, 120mm vertical telescopic distance. Three degrees of freedom of the manipulator is body rotation, arm movements, as well as the movements of the body. In the design process, determine the overall scheme of the milling machine loading and unloading manipulator and milling machine loading and unloading manipulator, the overall structure of the design parameters of some components as well as the main components of the calculation and verification. In the means of Single-chip microcomputer for controlling, design the automatic control system of the manipulator and achieve accurate control of the milling machine loading and unloading.Key words: Manipulator; Three Degrees of Freedom; Loading and unloading; single chip microcomputer目录摘要.........................................................................I第1章绪论.............................................................11.1选题背景................................................... (1)1.2设计目的.........................................................11.3国内外研究现状和趋势............................................21.4设计原则.........................................................2第2章设计方案的论证..................................................32.1 机械手的总体设计...............................................32.1.1机械手总体结构的类型....................................32.1.2 设计具体采用方案........................................42.2 机械手腰座结构设计.............................................52.2.1 机械手腰座结构设计要求.................................52.2.2 具体设计采用方案........................................52.3 机械手手臂的结构设计...........................................62.3.1机械手手臂的设计要求....................................62.3.2 设计具体采用方案........................................72.4 设计机械手手部连接方式.........................................72.5 机械手末端执行器(手部)的结构设计...........................82.5.1 机械手末端执行器的设计要求.............................82.5.2 机械手夹持器的运动和驱动方式..........................92.5.3 机械手夹持器的典型结构.................................92.6 机械手的机械传动机构的设计..................................102.6.1 工业机械手传动机构设计应注意的问题...................102.6.2 工业机械手传动机构常用的机构形式.....................102.6.3 设计具体采用方案.......................................122.7 机械手驱动系统的设计.........................................122.7.1 机械手各类驱动系统的特点..............................122.7.2 机械手液压驱动系统.....................................132.7.3机身摆动驱动元件的选取................................132.7.4 设计具体采用方案.......................................142.8 机械手手臂的平衡机构设计.....................................14第3章理论分析和设计计算............................................163.1 液压传动系统设计计算..........................................163.1.1 确定液压传动系统基本方案...............................163.1.2 拟定液压执行元件运动控制回路...........................173.1.3 液压源系统的设计........................................173.1.4 确定液压系统的主要参数.................................173.1.5 计算和选择液压元件......................................243.1.6机械手爪各结构尺寸的计算...................................26 第4章机械手控制系统的设计..........................................284.1 系统总体方案..................................................284.2 各芯片工作原理................................................284.2.1 串口转换芯片............................................284.2.2 单片机...................................................294.2.3 8279芯片...............................................304.2.4 译码器...................................................314.2.5 放大芯片................................................324.3 电路设计..................................................334.3.1 显示电路设计............................................334.3.2 键盘电路设计............................................334.4 复位电路设计..................................................334.5 晶体振荡电路设计.............................................344.6 传感器的选择..................................................34结论.....................................................................36致谢.....................................................................37参考文献................................................................38CONTENTS Abstract (I)Chapter 1 Introduction (1)1.1 background (1)1.2 design purpose (1)1.3 domestic and foreign research present situation and trends (2)1.4 design principles (2)Chapter 2 Design of the demonstration (3)2.1manipulator overall design (3)2.1.1 manipulator overall structure type (3)2.1.2 design adopts the scheme (4)2.2 lumbar base structure design of mechanical hand (5)2.2.1 manipulator lumbar base structure design requirements (5)2.2.2specific design schemes (5)2.3mechanical arm structure design (6)2.3.1 manipulator arm design requirements (6)2.3.2 design adopts the scheme (7)2.4 design of mechanical hand connection mode (7)2.5 the manipulator end-effector structure design (8)2.5.1 manipulator end-effector design requirements (8)2.5.2 manipulator gripper motion and driving method (9)2.5.3 manipulator gripper structure (9)2.6 robot mechanical transmission design (10)2.6.1 industry for transmission mechanism of manipulator design shouldpay attention question (10)2.6.2 industrial machinery hand transmission mechanism commonlyused form of institution (10)2.6.3 design adopts the scheme (12)2.7 mechanical arm drive system design (12)2.7.1 manipulator of various characteristics of the drive system (12)2.7.2 hydraulic drive system for a manipulator (13)2.7.3 Body swing the selection of drive components (13)2.7.4 Design the specific use of the program (14)2.8 mechanical arm balance mechanism design (14)Chapter 3 Theoretical analysis and design calculation (16)3.1 hydraulic system design and calculation (16)3.1.1 the basic scheme of hydrauic transmission system (16)3.1.2 formulation of the hydraulic actuator control circuit (17)3.1.3 hydraulic source system design (17)3.1.4 determine the main parameters of the hydraulic system (17)3.1.5 calculation and selection of hydraulic components (24)3.1.6 Manipulator calculation of the structural dimensions (26)Chapter 4 The robot control system design (28)4.1 Overall scheme (28)4.2 Chip works (28)4.2.1 serial conversion chip (28)4.2.2 MCU (29)4.2.3 8279 chip (30)4.2 .4 decoder (31)4.2.5 amplifier chip (32)4.3 Circuit design (33)4.3.1 show the circuit design (33)4.3.2 The keyboard circuit design (33)4.4 Reset circuit design (33)4.5 crystal oscillation circuit design (34)4.6 sensor selection (34)Conclusion (36)Acknowledgements (37)References (38)第1章绪论1.1选题背景机械手是在自动化生产过程中使用的一种具有抓取和移动工件功能的自动化装置,它是在机械化、自动化生产过程中发展起来的一种新型装置。
Horizon-Suite招标参数
具备大型桌面管理能力,至少支持5,000台以上虚拟桌面的能力
是
Horizon View解决方案可以提供10, 000虚拟桌面的管理能力。
支持预先在域环境是创建计算机帐号
是
防止在域权限管理严格的环境中不能自动创建计算机帐号
桌面连接服务器内置企业级数据库功能,无需购买第三方数据库软件
是
VMwareHorizon View连接服务器的配置数据均存储在微软ADAM数据库中,不需要采购第三方数据库,也不需要额外考虑数据库备份恢复方案
是
VMware ThinApp应用打包时提供权限设置与自定义消息内容设定功能
管理员可集中设定虚拟化应用程序个性化信息存放位置设定
是
VMware ThinApp应用程序打包时,管理员可以设定Sandbox位置。
管理员可直接将需要管理员权限运行的应用程序打包为普通用户权限使用
是
经过VMware ThinApp应用虚拟化后的应用,用户可以普通权限直接运行
在线与离线模式使用统一的管理界面与系统映像
是
VMwareHorizon View提供的在线与离线虚拟桌面使用统一的管理软件与系统映像
单一的管理和操作界面,方便管理,控制台不能超过2个。
是
VMwareHorizon View提供功能高度整合的简易操作平台,控制台只有2个。
提供单一的web控制台,集成桌面管理与Helpdesk管理功能
支持高速的双向音频重定向
是
PcoIP支持音频重定向,可针对 LAN 和 WAN 动态调整音频质量
支持通过非USB重定向的摄像头重定向技术
是
RTAV技术不需要在虚拟桌面安装摄像头驱动,即可重定向摄像头到虚拟桌面
Embedding Motion in Model-Based Stochastic Tracking
algorithms that keep only one configuration state [5], which are therefore sensitive to single failures in the presence of ambiguities or fast or erratic motion. In this paper, we address two important issues related to tracking with a particle filter. The first issue refers to the specific form of the observation likelihood, that relies on the conditional independence of observations given the state sequence. The second one refers to the choice of an appropriate proposal distribution, which, unlike the prior dynamical model, should take into account the new observations. To handle these issues, we propose a new particle filter tracking method based on visual motion. Our method relies on a new graphical model allowing for the natural introduction of implicit or explicit motion information in the likelihood term, and on the exploitation of explicit motion measurements in the proposal distribution. the above issues, our approach, and their benefits, is given in the following paragraphs. The definition of the observation likelihood distribution is perhaps the most important element in visual tracking with a particle filter. This distribution allows for the evaluation of the likelihood of the current observation given the current object state, and relies on the specific object representation. The object representation corresponds to all the information that characterizes the object like the target position, geometry, appearance, color, etc. Parametrized shapes like splines [2] or ellipses [6], and color distributions [5]–[8], are often used as target representation. One drawback of these generic representations is that they can be quite unspecific, which augments the chances of ambiguities. One way to improve the robustness of a tracker consists of combining low-level measurements such as shape and color [6]. The generic conditional form of the likelihood term relies on a standard hypothesis in probabilistic visual tracking, namely the independence of observations given the state sequence [2], [6], [9]–[13]. In this paper, we argue that this assumption can be inaccurate in the case of visual tracking. As a remedy, we propose a new model that assumes that the current observation depends on the current and previous object configurations as well as on the past observation. We show that under this more general assumption, the obtained particle filtering algorithm has similar equations than the algorithm based on the standard hypothesis. To our knowledge, this has not been shown before, and so it represents the first contribution of this article. The new assumption can thus be used to naturally introduce implicit or explicit motion information in the observation likelihood term. The introduction of such data correlation between successive images will turn generic trackers like shape or color histogram trackers into more specifi in Model-Based Stochastic Tracking
staad pro 国际标准
《深度解析staad pro国际标准》01 引言在结构工程领域,staad pro国际标准一直是一个备受关注的话题。
它的重要性不仅在于其在工程设计和分析中的应用,更在于其作为国际标准所具有的权威性和普适性。
本文旨在通过深度解析staad pro国际标准,让读者更清晰地了解其内涵和应用范围。
02 staad pro国际标准的定义staad pro是一种用于结构工程建模和分析的软件,而staad pro国际标准则是针对该软件在国际范围内的应用而制定的一系列规范和要求。
它涵盖了结构工程设计、分析、验算等多个方面,旨在保障工程结构的安全性、稳定性和可靠性。
03 staad pro国际标准的内容staad pro国际标准主要包括以下几个方面的内容:1. 结构荷载标准:对建筑结构所承受的各种静载荷、动载荷和温度荷载进行了详细规定,涵盖了地震、风载等特殊情况下的荷载计算方法。
2. 材料使用标准:对建筑材料的选用和使用进行了规范,包括了混凝土、钢材等材料的力学性能要求和计算方法。
3. 结构设计标准:包括了钢结构、混凝土结构、木结构等不同类型结构的设计要求,以及构件尺寸和构造的规定。
4. 施工和验收标准:针对结构施工和验收过程中的技术要求和质量标准,确保了施工过程的合规性和结构的安全性。
04 staad pro国际标准的应用staad pro国际标准在实际工程中具有广泛的应用。
许多国际性的大型工程项目都要求严格遵守staad pro国际标准,以保证工程的质量和安全。
在结构设计和分析软件staad pro中,也内置了staad pro国际标准的相关内容,方便工程师在使用软件进行设计和分析时能够快速符合标准要求。
05 个人观点和理解对于staad pro国际标准,我个人认为其规定了一系列科学、合理的设计和分析方法,能够有效地保障工程结构的安全性和可靠性。
staad pro国际标准也不断更新和完善,以适应不断变化的工程需求和标准要求。
PVST特性对接替换指导书,华为与思科stp对接
PVST+特性对接替换指导书文档版本02 发布日期 2014-06-06华为技术有限公司版权所有© 华为技术有限公司2014。
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华为技术有限公司地址:深圳市龙岗区坂田华为总部办公楼邮编:518129网址:前言概述本文档针对CISCO PVST+特性,给出了华为VBST与PVST+特性实现差异对比,并提供了在对接或替换场景下的操作步骤。
读者对象本文档主要适用于以下工程师:●网络规划工程师●调测工程师●数据配置工程师●现场维护工程师●网络监控工程师●系统维护工程师符号约定在本文中可能出现下列标志,它们所代表的含义如下。
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目录前言 (ii)1 生成树原理介绍 (1)1.1 Ciscos交换机生成树介绍 (1)1.1.1 PVST (1)1.1.2 PVST+ (1)1.1.3 Rapid-PVST+ (2)1.1.4 MST (3)1.2 Huawei VBST协议介绍 (4)1.2.1 VBST基本概念 (4)1.2.2 VBST应用场景 (6)2 互通性分析 (1)2.1 互通性分析 (1)2.2 PVST/VBST报文类型对比 (2)2.2.1 CISCO PVST (2)2.2.2 Huawei VBST (3)2.3 链路开销算法对比 (4)2.4 MSTP域摘要 (5)2.4.1 原理描述 (5)2.4.2 部署注意事项 (6)2.4.3 部署经验 (6)2.5 互通场景 (7)3 对接替换案例 (8)3.1 方案一:Huawei透传PVST (8)3.1.1 案例:S5700EI替换C3750 (8)3.1.1.1 背景介绍 (8)3.1.1.2 替换步骤 (9)3.1.1.3 注意事项 (10)3.1.1.4 关键配置 (10)3.1.1.5 常见问题与处理 (11)3.2 方案二:VBST对接PVST (17)3.2.1 案例:S12700替换C7600 (17)3.2.1.1 背景介绍 (17)3.2.1.2 替换步骤 (18)3.2.1.3 注意事项 (18)3.2.1.4 关键配置 (19)3.3 方案三:更改CISCO PVST为MST (20)3.3.1 案例1:S9300替换C7600 (20)3.3.1.1 背景介绍 (20)3.3.1.2 替换步骤 (21)3.3.1.3 注意事项 (22)3.3.1.4 关键配置 (22)3.3.1.5 常见问题与处理 (23)3.3.2 案例2:S9300替换C7600 (24)3.3.2.1 背景介绍 (24)3.3.2.2 替换步骤 (25)3.3.2.3 注意事项 (28)3.3.2.4 关键配置 (29)4 替换前后检查 (30)4.1替换前检查原CISCO设备状态 (30)4.2 替换后检查Huawei设备状态 (31)1 生成树原理介绍1.1 Ciscos交换机生成树介绍CISCO交换机所支持的生成树协议类型分别有:PVST(Per VLAN Spanning Tree)、PVST+(Per VLAN Spanning Tree Plus)、Rapid-PVST+(Rapid Per VLAN Spanning Tree Plus)、MISTP(Multi Instance Spanning Tree Protocol)和MST(Multiple Spanning Tree)。
adaptivethreshold 偏移量 -回复
adaptivethreshold 偏移量-回复什么是adaptivethreshold 偏移量?Adaptivethreshold 偏移量(Adaptive Threshold Offset)是一种图像处理中常用的技术,用于将图像分割为二值图像。
图像分割是图像处理的基础步骤之一,它将图像中的目标和背景分离出来,使得图像更容易理解和处理。
在进行图像分割时,常常需要选择一个合适的阈值来确定目标和背景,而adaptivethreshold 偏移量就是用来计算这个阈值的。
为了更好地理解adaptivethreshold 偏移量的作用,首先需要了解adaptivethreshold 分割算法的工作原理。
这一算法是基于自适应阈值的分割方法,它可以根据图像中的像素灰度值的局部特性自动选择阈值,从而实现更好的分割效果。
adaptivethreshold 分割算法根据像素周围的邻域信息来确定每个像素的阈值,这使得它能够在受到光照和噪声等因素影响时仍能有效地进行图像分割。
具体而言,adaptivethreshold 偏移量是用来调整adaptivethreshold 算法中的阈值的。
adaptivethreshold 算法根据图像局部邻域的平均灰度值来计算阈值,而adaptivethreshold 偏移量可以对这个计算结果进行修正。
当我们在使用adaptivethreshold 算法进行图像分割时,可能会遇到一些特殊情况,例如图像中存在很强的光照差异或者噪声干扰较多。
这些情况下,adaptivethreshold 的计算结果可能会偏离我们期望的分割效果,因此我们需要根据实际情况调整阈值。
adaptivethreshold 偏移量可以通过增加或减少adaptivethreshold 算法中的阈值来实现。
当图像中存在较强光照差异时,我们可以增加偏移量来使得阈值增加,从而更好地适应光照变化。
而当图像中存在噪声干扰时,我们可以减少偏移量来使得阈值减小,从而更好地保留目标的细节信息。
3GPP 5G基站(BS)R16版本一致性测试英文原版(3GPP TS 38.141-1)
4.2.2
BS type 1-H.................................................................................................................................................. 26
4.3
Base station classes............................................................................................................................................27
1 Scope.......................................................................................................................................................13
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STAADPRO使用统一规定
STAAD/PRO使用统一规定目次1 总则 (2)1.1 目的 (2)1.2 范围 (2)1.3 引用文件 (2)2 概述 (2)3 基本风压值的修正 (2)4 地震参数相应的选择 (3)5 屈服应力的相应选用 (3)6 荷载规定 (4)6.1 各组荷载定义 (4)6.2 吊车荷载数据 (4)7 结构计算长度系数取 (4)8 钢结构设计荷载组合规定(按AISC) (5)9 地基及基础设计时荷载组合规定(按GB50007) (9)附录A 基本风压值增大系数确定依据 (13)附录B 地震分区系数参考资料 (13)1 总则1.1 目的为使结构专业设计人员在我国化工厂钢结构的计算中,正确地使用STAAD/PRO 软件,特编制本规定。
1.2 范围本规定适用于设备承重钢框架的计算。
1.3 引用文件下列文件中的条款通过本规定的引用而成为本规定的条款。
凡是注日期的引用文件,其随后所有的修改单(不包括勘误的内容)或修订版均不适用本规定。
凡是不注日期的引用文件,其最新版本适用于本规定。
GB50007 建筑地基基础设计规范GB50009 建筑结构荷载规范GB50011 建筑抗震设计规范GB50017 钢结构设计规范UBC (94版) 美国统一建筑法规AISC 美国钢结构设计规范2 概述2.1 原“STAAD/PRO 程序”注对中国的相关规范来讲尚不够完善,因此工程计算时应对UBC 及AISC 有关计算公式(与中国相关规范不同的部分)作相应的修改。
2.2 根据我国新颁的标准规范,本规定对原“STAAD/PRO 使用统一规定”作了相应修改。
主要修改内容如下:a ) 基本风压值的修改;b ) 地震参数相应的选择。
注:原“STAAD/PRO 程序”是按照美国统一建筑法规UBC (94版)及美国钢结构设计规范(AISC )进行编制的,它具有能选出钢材型号;验算构件的强度及稳定性;优化设计等优点,被广泛运用于钢结构的设计。
2.3 对于二层以上(不包括二层)的设备承重钢框架,活荷载注取值按GB50009规定,一般取值为:4kN/m 2。
Standard标准菜单
Standard标准菜单File文件New Scene建立新场景Open Scene打开场景Save Scene存盘场景Save Scene As改名存盘Import导入Export All导出所有Export Selection导出选定物体Create Reference引入场景文件Reference Editor引入场景编辑器Project项目New建立新项目Edit Current编辑当前项目Set指定当前项目Exit退出Edit编辑Undo取消上一次操作Redo恢复上一次操作Repeat重复最后一次操作Keys关键帧Cut Keys裁剪关键帧Copy Keys拷贝关键帧Paste Keys粘贴关键帧Delete Keys删除关键帧Scale Keys缩放关键帧Bake Simulation模拟复制Delete删除Delete by Type根据类型删除History构造历史Channels通道Static Channels静帧通道Motion Paths运动路径Expressions表达式Constraints约束Rigid Bodies刚体Delete All by Type根据类型删除所有History构造历史Channels通道Static Channels静帧通道Motion Paths运动路径Expressions表达式Constraints约束Unused Transforms未用变形Joints连接IK Handles逆向运动控制柄Lattices车削Clusters族Sculpt Objects雕刻物体Wires网格Lights灯光Cameras照相机Image Planes图像板Shading Groups and Materials阴影组和材质Particles粒子Rigid Bodies刚体物体Rigid Constraints刚体约束Select All选择所有Select All by Type根据类型选择所有Joints连接IK Handles逆向运动控制柄Lattices车削Clusters族Sculpt Objects雕刻物体Wires网格Transforms变形Geometry几何体NURBS Geometry NURBS几何体Polygon Geometry多边形几何体Lights灯光Cameras照相机Image Planes图像板Particles粒子Rigid Bodies刚体物体Rigid Constraints刚体约束Quick Select Set快速选择集Layers层New Layers建立新层Rename Layer更改层名称Remove Current Layer移去当前层Layer Editor层编辑器Transfer to Layer转化为层Select All on Layer选择层上所有物体Hide Layer隐藏层Hide All Layers隐藏所有层Show Layer显示层Show All Layers显示所有层Template Layer临时层Untemplate Layer解除临时层Hide Inactive Layers隐藏非活动层Template Inactive Layers临时非活动层Duplicate复制Group成组Ungroup解成组Create Empty Group建立空成组Parent建立父物体Unparent解除父物体Modify修改Transformation Tools变形工具Move Tool移动工具Rotate Tool旋转工具Scale Tool缩放工具Show Manipulator Tool显示手动工具Default Object Manipulator默认调节器Proportional Modi Tool比例修改工具Move Limit Tool移动限制工具Rotate Limit Tool旋转限制工具Scale Limit Tool缩放限制工具Reset Transformations重新设置变形控制Freeze Transformations冻结变形控制Enable Nodes授权动画节点All所有IK solvers逆向运动连接器Constraints约束Expressions表达式Particles粒子Rigid Bodies刚体Snapshots快照Disable Node废弃动画节点Make Live激活构造物Center Pivot置中枢轴点Prefix Hierarchy Names定义前缀Add Attribute增加属性Measure测量Distance Tool距离工具Parameter Tool参数工具Arc Length Tool弧度工具Animated Snapshot动画快照Animated Sweep由动画曲线创建几何体曲面Display显示Geometry几何体Backfaces背面Lattice Points车削点Lattice Shape车削形Local Rotation Axes局部旋转轴Rotate Pivots旋转枢轴点Scale Pivots缩放枢轴点Selection Handles选定句柄NURBS Components NURBS元素CVs CV曲线Edit Points编辑点Hulls可控点Custom定制NURBS Smoothness NURBS曲面光滑处理Hull物体外壳Rough边框质量Medium中等质量Fine精细质量Custom定制Polygon Components多边形元素Custom Polygon Display定制多边形显示Fast Interaction快速交错显示Camera/Light Manipulator照相机/灯光操作器Sound声音Joint Size关节尺寸IK Handle Size IK把手尺寸Window窗口General Editors通用编辑器Set Editor系统设置编辑器Attribute Spread Sheet属性编辑器Tool Settings工具设置Filter Action Editor滤镜动作编辑器Channel Control通道控制信息Connection Editor连接编辑器Performance Settings性能设置Script Editor Script编辑器Command Shell命令窗口Plug-in Manager滤镜管理器Rendering Editors渲染编辑器Rendering Flags渲染标记Hardware Render Buffer硬件渲染缓冲区Render View渲染视图Shading Groups Editor阴影组编辑器Texture View质地视图Shading Group Attributes阴影组属性Animation Editors动画编辑器Graph Editor图形编辑器Dope SheetBlend Shape融合形Device Editor设备编辑器Dynamic Relationships动态关系Attribute Editor属性编辑器Outliner框架Hypergraph超图形Multilister多功能渲染控制Expression Editor表达式编辑器Recent Commands当前命令Playblast播放预览View Arangement视图安排Four四分3 Top Split上三分3 Left Split左三分3 Right Split右三分3 Bottom Split底部三分2 Stacked二叠分2 Side By Side二平分Single单图Previous Arrangement前次安排Next Arrangement下次安排Saved Layouts保存布局Single Perspective View单透视图Four View四分图Persp/Graph/Hyper透视/图形/超图形Persp/Multi/Render透视/多功能/渲染Persp/Multi/Outliner透视/多功能/轮廓Persp/Multi透视/多功能Persp/Outliner透视/轮廓Persp/Graph透视/图形Persp/Set Editor透视/组编辑器Edit Layouts编辑布局Frame Selected in All Views所有视图选定帧Frame All in All Views所有视图的所有帧Minimize Application最小化应用Raise Application Windows移动窗口向前Options可选项General Preferences一般设置UI Preferences用户界面设置Customize UI定制用户界面Hotkeys快捷键Colors颜色Marking Menus标记菜单Shelves书架Panels面板Save Preferences保存设置Status Line状态栏Shelf书架Feedback Line反馈栏Channel Box通道面板Time Slider时间滑动棒Range Slider范围滑动棒Command Line命令行Help Line帮助行Show Only Viewing Panes仅显示视图面板Show All Panes显示所有面板Modeling建模系统Primitives基本物体Create NURBS创建NURBS物体Sphere球体Cube立方体Cylinder圆柱体Cone圆台(锥)体Plane平面物体Circle圆Create Polygons创建多边形物体Sphere球体Cube立方体Cylinder圆柱体Cone圆台(锥)体Plane平面物体Torus面包圈Create Text创建文本Create Locator创建指示器Construction Plane构造平面Create Camera创建照相机Curves创建曲线CV Curve Tool CV曲线工具EP Curve Tool EP曲线工具Pencil Curve Tool笔曲线工具Add Points Tool加点工具Curve Editing Tool曲线编辑工具Offset Curve曲线移动Offset Curve On Surface曲线在表面移动Project Tangent曲线切线调整Fillet Curve带状曲线Rebuild Curve重建曲线Extend Curve扩展曲线Insert Knot插入节点Attach Curves连接曲线Detach Curves断开曲线Align Curves对齐曲线Open/Close Curves打开/关闭曲线Reserse Curves反转曲线Duplicate Curves复制曲线CV Hardness硬化曲线Fit B-spline适配贝塔曲线Surfaces曲面Bevel斜角Extrude凸出Loft放样Planar曲面Revolve旋转Boundary边界Birail 1 Tool二对一工具Birail 2 Tool二对二工具Birail 3+ Tool二对三工具Circular Fillet圆边斜角Freeform Fillet***形斜角Fillet Blend Tool斜角融合工具Edit Surfaces编辑曲面Intersect Surfaces曲面交叉Project Curve投影曲线Trim Tool修整曲线工具Untrim Surfaces撤消修整Rebuild Surfaces重建曲面Prepare For Stitch准备缝合Stitch Surface Points点缝合曲面Stitch Tool缝合工具NURBS to Polygons NURBS转化为多边形Insert Isoparms添加元素Attach Surfaces曲面结合Detach Surfaces曲面分离Align Surfaces曲面对齐Open/Close Surfaces打开/关闭曲面Reverse Surfaces反转曲面Polygones多边形Create Polygon Tool创建多边形工具Append to Polygon Tool追加多边形Split Polygon Tool分离多边形工具Move Component移动元素Subdivide多边形细化Collapse面转点Edges边界Soften/Harden柔化/硬化Close Border关闭边界Merge Tool合并工具Bevel斜角Delete and Clean删除和清除Facets面Keep Facets Together保留边线Extrude凸出Extract破碎Duplicate复制Triangulate三角分裂Quadrangulate四边形合并Trim Facet Tool面修整工具Normals法向Reverse倒转法向Propagate传播法向Conform统一法向Texture质地Assign Shader to Each Projection指定投影Planar Mapping平面贴图Cylindrical Mapping圆柱体贴图Spherical Mapping球体贴图Delete Mapping删除贴图Cut Texture裁剪纹理Sew Texture斜拉纹理Unite联合Separate分离Smooth光滑Selection Constraints选定限定工具Smart Command Settings改变显示属性Convert Selection转化选定Uninstall Current Settins解除当前设定Animation动画模块Keys关键帧Settings设置关键帧Auto Key自动设置关键帧Spline样条曲线式Linear直线式Clamped夹具式Stepped台阶式Flat平坦式Other其他形式Set Driven Key设置驱动关键帧Set设置Go To Previous前移Go To Next后退Set Key设置帧Hold Current Keys保留当前帧Paths路径Set Path Key设置路径关键帧Attach to Path指定路径Flow Path Object物体跟随路径Skeletons骨骼Joint Tool关节工具IK Handle Tool反向动力学句柄工具IK Spline Handle Tool反向动力学样条曲线句柄工具Insert Joint Tool添加关节工具Reroot Skeleton重新设置根关节Remove Joint去除关节Disconnect Joint解除连接关节Connect Joint连接关节Mirror Joint镜向关节Set Preferred Angle设置参考角Assume Preferred AngleEnable IK Solvers反向动力学解算器有效EIk Handle Snap反向动力学句柄捕捉有效ESelected IK Handles反向动力学句柄有效DSelected IK Handles反向动力学句柄无效Deformations变形Edit Menbership Tool编辑成员工具Prune Membership变形成员Cluster簇变形Lattice旋转变形Sculpt造型变形Wire网格化变形Lattice旋转Sculpt造型Cluster簇Point On Curve线点造型Blend Shape混合变形Blend Shape Edit混合变形编辑Add增加Remove删除Swap交换Wire Tool网格化工具Wire Edit网格编辑Add增加Remove删除Add Holder增加定位曲线Reset重置Wire Dropoff Locator网线定位器Wrinkle Tool褶绉变形工具Edit Lattice编辑旋转Reset Lattice重置旋转Remove Lattice Tweeks恢复旋转Display I-mediate Objects显示中间物体Hide Intermediate Objects隐藏中间物体Skinning皮肤Bind Skin绑定蒙皮Detach Skin断开蒙皮Preserve Skin Groups保持皮肤组Detach Skeleton分离骨骼Detach Selected Joints分离选定关节Reattach Skeleton重新连接骨骼Reattach Selected Joints重新连接关节Create Flexor创建屈肌Reassign Bone Lattice Joint再指定骨头关节Go to Bind Pose恢复骨头绑定Point关节Aim目标Orient方向Scale缩放Geometry几何体Normal法向RenderingLighting灯光Create Ambient Light创建环境光Create Directional Light创建方向灯Create Point Light创建点光源Create Spot Light创建聚光灯Relationship Panel关系面板Light Linking Tool灯光链接工具Shading 阴影Shading Group Attributes阴影组属性Create Shading Group创建阴影组Lambert朗伯材质Phong Phong材质Blinn布林材质Other其他材质Assign Shading Group指定阴影组InitialParticleSE初始粒子系统InitialShadingGroup初始阴影组Shading Group Tool阴影组工具Texture Placement Tool纹理位移工具Render渲染Render into New Window渲染至新窗口Redo Previous Render重复上次渲染Test Resolution测试分辨率Camera Panel照相机面板Render Globals一般渲染Batch Render批渲染Cancel Batch Render取消批渲染Show Batch Render显示批渲染Dynamics动力学系统Settings设置Initial State初始状态Set For Current当前设置Set For All Dynamic设置总体动力学特性Rigid Body Solver刚体解算器Dynamics Controller动力学控制器Particle Collision Events粒子爆炸Particle Caching粒子缓冲Run-up and Cache执行缓冲Cache Current Frame缓冲当前帧Set Selected Particles设置选定粒子Dynamics On动力学开Dynamics Off动力学关Set All Particles设置所有粒子Particles All On When Run执行时粒子系统开Auto Create Rigid Body自动创建刚体Particles粒子Particle Tool粒子工具Create Emitter创建发射器Add Emitter增加发射器Add Collisions增加碰撞Add Goal增加目标Fields场Create Air创建空气动力场Create Drag创建拖动场Create Gravity创建动力场Create Newton创建牛顿场Create Radial创建辐射动力场Create Turbulence创建震荡场Create Uniform创建统一场Create Vortex创建涡流场Add Air增加空气动力场Add Newton增加牛顿场Add Radial增加辐射场Add Turbulence增加震荡场Add Uniform增加统一场Add Vortex增加涡流场Connect连接Connect to Field场连接Connect to Emitter发射器连接Connect to Collision碰撞连接Bodies柔体和刚体Create Active Rigid Body创建正刚体Create Passive Rigid Body创建负刚体Create Constraint创建约束物体Create Soft Body创建柔体Create Springs创建弹簧Set Active Key设置正向正Set Passive Key设置负向正。
变压器英文专业术语
英文名称 Power substation Power station Gas-insulation substation Converter substation High-voltage direct current system Total enclosed combined electric apparatus transformer autotransformer Starting transformer Welding transformer Testing transformer Generator transformer Traction transformer mounted on rolling stock Explosion proof transformer Transformer for mining user Voltage regulating transformer Composite transformer Traction transformer Rectifier transformer Grid transformer Foil transformer Distribution transformer Expoxy resin casting type transformer High-frequency transformer Step-up transformer Booster transformer Dry-type transformer Sealed transformer Split winding transformer Shunt reactor Current-limiting reactor Saturable reactor Starting reactor Smoothing reactor Power capacitor Coupling capacitor Shunt capacitor Arc-suppressing coil Electromagnetic type voltage transformer Current transformer Instrument transformer High-voltage electric apparatus Single-phase transformer Pole-mounted overhead transformer Circuit breaker Disconnector
Design Patterns
2
Design Patterns [1]
• A solution to a problem that occurs repeatedly in a variety of contexts.
• Each pattern has a name.
• Use of each pattern has consequences.
4
Observer Pattern [1]
• Need to separate presentational aspects with the data, i.e. separate views and data. • Classes defining application data and presentation can be reused. • Change in one view automatically reflected in other views. Also, change in the application data is reflected in all views. • Defines one-to-many dependency amongst objects so that when one object changes its state, all its dependents are notified.
iter.CurrentItem() -> Update(this);
}
}
11
Observer Pattern: A Concrete Subject [1]
class ClockTimer : public Subject { public:
ClockTimer(); virtual int GetHour(); virtual int GetMinutes(); virtual int GetSecond(); void Tick ();
ug909-vivado-partial-reconfiguration
Vivado Design Suite User GuidePartial ReconfigurationUG909 (v2014.1) April 2, 2014Revision HistoryThe following table shows the revision history for this document.Date Version Revision04/02/20142014.1Revisions to manual for Vivado Design Suite 2014.1 release:In Design Requirements and Guidelines, page9, changed device support informationto match device support in 2014.1 Vivado release. Also modified device supportinformation throughout document.In Design Criteria, page11, changed text to indicate that dedicated encryptionsupport for partial bitstreams is now available natively for 7series devices.In Automatic Adjustments for Reconfigurable Partition Pblocks, page39 and CreatingReconfigurable Partition Pblocks Manually, page41, described the PblockSNAPPING_MODE property, which automatically resizes Pblocks to ensure noback-to-back violations occur for 7 series designs.Changed command line examples to show that the update_design command willnot accept an NGC file as input.Method 1: Create a Single RM Checkpoint (DCP),page17 presents a process for including an NGC input file into an RM checkpoint(DCP), so the NGC file casn be resolved to its cells.Table of ContentsRevision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Chapter1:IntroductionOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Introduction to Partial Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Chapter2:Vivado Software FlowSoftware Flow Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Partial Reconfiguration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Partial Reconfiguration Constraints and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Software Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Chapter3:Design Considerations and GuidelinesIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Global Clocking Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Partition Pin Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Active Low Resets and Clock Enables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Decoupling Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Reconfigurable Partition Pblock Sizes and Shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Black Boxes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Implementation Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Design Revision Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Simulation and Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Chapter4:Configuring the FPGA DeviceConfiguration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Downloading a Full Bit File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Downloading a Partial Bit File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52System Design for Configuring an FPGA Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Partial Bitstream CRC Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Configuration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Configuration Debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Chapter5:Known Issues and LimitationsKnown Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Known Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Appendix A:Additional Resources and Legal NoticesXilinx Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Chapter1 IntroductionOverviewPartial Reconfiguration allows for the dynamic change of modules within an active design.This flow requires the implementation of multiple configurations which ultimately results in full bitstreams for each configuration, and partial bitstreams for each ReconfigurableModule.The number of configurations required varies by the number of modules that need to be implemented. However, all configurations use the same top-level, or static, placement and routing results. These static results are exported from the initial configuration, andimported by all subsequent configurations using checkpoints.This guide:•Is intended for designers who want to create a partially reconfigurable FPGA design.•Assumes familiarity with FPGA design software, particularly Xilinx® Vivado® Design Suite.•Has been written specifically for Vivado Design Suite Release 2014.1. This release supports Partial Reconfiguration for Virtex®-7, Kintex®-7, Artix®-7, and Zynq®-7000AP SoC devices.•Describes Partial Reconfiguration as implemented in the Vivado toolset.VIDEO:For an overview of the Vivado Partial Reconfiguration solution in 7 series devices, see theVivado Design Suite QuickTake Video: Partial Reconfiguration in Vivado.Introduction to Partial ReconfigurationFPGA technology provides the flexibility of on-site programming and re-programming without going through re-fabrication with a modified design. Partial Reconfiguration (PR) takes this flexibility one step further, allowing the modification of an operating FPGA design by loading a partial configuration file, usually a partial BIT file. After a full BIT fileconfigures the FPGA, partial BIT files can be downloaded to modify reconfigurable regions in the FPGA without compromising the integrity of the applications running on those parts of the device that are not being reconfigured.Figure 1-1 illustrates the premise behind Partial Reconfiguration.As shown, the function implemented in Reconfig Block A is modified by downloading one of several partial BIT files, A1.bit , A2.bit , A3.bit , or A4.bit . The logic in the FPGA design is divided into two different types, reconfigurable logic and static logic. The gray area of the FPGA block represents static logic and the block portion labeled Reconfig Block "A" represents reconfigurable logic. The static logic remains functioning and is unaffected by the loading of a partial BIT file. The reconfigurable logic is replaced by the contents of the partial BIT file.There are many reasons why the ability to time multiplex hardware dynamically on a single FPGA device is advantageous. These include: •Reducing the size of the FPGA device required to implement a given function, with consequent reductions in cost and power consumption•Providing flexibility in the choices of algorithms or protocols available to an application •Enabling new techniques in design security •Improving FPGA fault tolerance •Accelerating configurable computingIn addition to reducing size, weight, power and cost, Partial Reconfiguration enables new types of FPGA designs that are impossible to implement without it.Figure 1-1:Basic Premise of Partial ReconfigurationTerminologyThe following terminology is specific to the Partial Reconfiguration feature and is used throughout this document.Bottom-Up SynthesisBottom-Up Synthesis is synthesis of the design by modules, whether in one project or multiple projects. Bottom-Up Synthesis requires that a separate netlist is written for each Partition, and no optimizations are done across these boundaries, ensuring that each portion of the design is synthesized independently. Top-level logic must be synthesized with black boxes for Partitions.ConfigurationA Configuration is a complete design that has one Reconfigurable Module for each Reconfigurable Partition. There may be many Configurations in a Partial Reconfiguration FPGA project. Each Configuration generates one full BIT file as well as one partial BIT file for each Reconfigurable Module.Configuration FrameConfiguration frames are the smallest addressable segments of the FPGA configuration memory space. Reconfigurable frames are built from discrete numbers of these lowest-level elements. In a 7 series device, the base reconfigurable frames are one element (CLB, BRAM, DSP) wide by one clock region high.Internal Configuration Access Port (ICAP)The Internal Configuration Access Port (ICAP) is essentially an internal version of the SelectMAP interface. For more information, see the 7 Series FPGAs Configuration User Guide (UG470) [Ref1].Partial Reconfiguration (PR)Partial Reconfiguration is modifying a subset of logic in an operating FPGA design by downloading a partial bitstream.PartitionA Partition is a logical section of the design, defined by the user at a hierarchical boundary, to be considered for design reuse. A Partition is either implemented as new or preserved from a previous implementation. A Partition that is preserved maintains not only identical functionality but also identical implementation.Partition PinPartition pins are the logical and physical connection between static logic and reconfigurable logic. Partition pins are automatically created for all Reconfigurable Partition ports.Processor Configuration Access Port (PCAP)The Processor Configuration Access Port (PCAP) is similar to the Internal Configuration Access Port (ICAP) and is the primary port used for configuring a Zynq-7000 device. For more information, see the Zynq-7000 All Programmable Technical Reference Manual (UG585) [Ref2].Reconfigurable FrameReconfigurable frames (in all references other than "configuration frames" in this guide) represent the smallest reconfigurable region within an FPGA device. Bitstream sizes of reconfigurable frames vary depending on the types of logic contained within the frame.Reconfigurable LogicReconfigurable Logic is any logical element that is part of a Reconfigurable Module. These logical elements are modified when a partial BIT file is loaded. Many types of logical components may be reconfigured such as LUTs, flip-flops, BRAM, and DSP blocks.Reconfigurable Module (RM)A Reconfigurable Module (RM) is the netlist or HDL description that is implemented within a Reconfigurable Partition. Multiple Reconfigurable Modules will exist for a Reconfigurable Partition.Reconfigurable Partition (RP)Reconfigurable Partition (RP) is an attribute set on an instantiation that defines the instance as reconfigurable. The Reconfigurable Partition is the level of hierarchy within which different Reconfigurable Modules will be implemented. Tcl commands such asopt_design, place_design and route_design detect the HD.RECONFIGURABLE property on the instance and process it correctly.Static LogicStatic Logic is any logical element that is not part of a Reconfigurable Partition. The logical element is never partially reconfigured and is always active when Reconfigurable Partitions are being reconfigured. Static Logic is also known as Top-level Logic.Static DesignThe Static Design is the part of the design that will not change during partial reconfiguration. The static design includes the top level and all modules not defined as reconfigurable. The Static Design is built with Static Logic and Static Routing.Design ConsiderationsPartial Reconfiguration (PR) is an expert flow within the Vivado Design Suite. Prospective customers must understand the following requirements and expectations before embarking on a PR project.Design Requirements and Guidelines•Partial Reconfiguration requires the use of Vivado 2013.3 or newer.°Partial Reconfiguration is supported in the ISE Design Suite as well. Please consult the Partial Reconfiguration User Guide (UG702)[Ref3] for more information.•Device support: Kintex-7, Virtex-7, and Zynq AP SoC devices, plus the three largest Artix-7 devices.°New devices added in the 2014.1 Vivado Design Suite release:-Virtex-7: 7VH580T, 7VH870T-Artix-7: 7A200T, 7A100T, 7A75T-Zynq AP SoC: 7Z100, 7Z015°The Artix-7 50T and 35T devices are the two 7 series devices that are not yet supported.°UltraScale™ devices are not yet supported.•PR is supported via Tcl or command line only; there is no project support at this time.•Floorplanning is required to define reconfigurable regions, per element type.°For greatest efficiency, and to use the RESET_AFTER_RECONFIG feature, vertically align to frame/clock region boundaries.°Horizontal alignment rules also apply. See Create a Floorplan for the Reconfigurable Region in Chapter2 for more information.•Bottom-up synthesis (to create multiple netlist files) and management of Reconfigurable Module netlist files is the responsibility of the user.°Any synthesis tool may be used. Disable I/O insertion to create Reconfigurable Module netlists.°Vivado Synthesis uses the out-of-context Module Analysis flow for Reconfigurable Module synthesis.•Standard timing constraints are supported, and additional timing budgeting capabilities are available if needed.• A unique set of Design Rule Checks (DRCs) has been established to guide users on a successful path to design completion.• A PR design must consider the initiation of Partial Reconfiguration as well as the delivery of partial BIT files, either within the FPGA or as part of the system design.• A Reconfigurable Partition must contain a super set of all pins to be used by the varying Reconfigurable Modules implemented for the partition. It is expected that this will lead to unused inputs or outputs for some modules, and is designed into the flexibility of the PR solution. The unused inputs will be left dangling inside of the module; drive outputs to a constant if this is an issue for your design.°In the case of a black box RM (no logic) after update_design -black_box has been issued, all partition pin outputs will be undriven. If this black box module will be used to create a bitstream, it is recommended that decoupling logic for this RP remain active while the black box is loaded in the device.Design PerformancePerformance metrics will vary from design to design, and the best results will be seen when if you follow the Hierarchical Design techniques documented in the Hierarchical Design Methodology Guide (UG748) [Ref4], and in Repeatable Results with Design Preservation (WP362) [Ref5]. These documents were created for the ISE Design Suite, but the methodologies contained therein still apply for the Vivado Design Suite.However, the additional restrictions that are required for silicon isolation are expected to have an impact on most designs. The application of Partial Reconfiguration rules, such as routing containment, exclusive placement, and no optimization across reconfigurable module boundaries, will mean that the overall density and performance will be lower for a PR design than for the equivalent flat design. The overall design performance for PR designs will vary from design to design based on factors such as the number of reconfigurable partitions, the number of interface pins to these partitions, and the size and shape of Pblocks.Design Criteria•Some component types can be reconfigured and some cannot.°Reconfigurable resources include CLB, BRAM, and DSP component types as well as routing resources.°Clocks and Clock modifying logic cannot be reconfigured, and therefore must reside in the static region.-Includes BUFG, BUFR, MMCM, PLL, and similar components°The following components cannot be reconfigured, and therefore must reside in the static region:-I/O and I/O related components (ISERDES, OSERDES, IDELAYCTRL, etc.)-Serial transceivers (MGTs) and related components-Individual architecture feature components (such as BSCAN, STARTUP, XADC, etc.) must remain in the static region of the design•Global clocking resources to Reconfigurable Partitions are limited, depending on the device and on the clock regions occupied by these Reconfigurable Partitions.•IP restrictions may occur due to components used to implement the IP. Examples include:°Vivado Debug Hub (BSCAN and BUFG)°IP modules with embedded global buffers or I/O°MIG controller (MMCM)•Reconfigurable Modules must be initialized to ensure a predictable starting condition after reconfiguration. You can do this manually with a local reset, or via dedicated GSR events by selecting the RESET_AFTER_RECONFIG feature.•Decoupling logic is highly recommended to disconnect the reconfigurable region from the static portion of the design during the act of Partial Reconfiguration.°Clock and other inputs to Reconfigurable Modules can be decoupled to prevent spurious writes to memories during reconfiguration. This should be considered if RESET_AFTER_RECONFIG is not used.• A reconfigurable partition must be flooorplanned, so the module must be a block that can be contained by a Pblock and meet timing. If the module is complete, it isrecommended to run this design through a non-PR flow to get an initial evaluation of placement, routing, and timing results. If the design has issues in a non-PR flow, these should be resolved before moving on to the PR flow.•Each module pin on an RP will have a partition pin. This is a routing point that connects static logic to the RP. If a design has too many partition pins for the number of availablerouting resources, routing congestion can occur. Consider the number of external pins on the RP, and pick a module that has a minimum required set of pins.•Virtex-7 SSI devices (7V2000T, 7VX1140T, 7VH870T, 7VH580T) have two fundamental requirements. These requirements are:°Reconfigurable regions must be fully contained within a single SLR. This ensures that the global reset events are properly synchronized across all elements in theReconfigurable Module, and that all Super Long Lines (SLL) are contained within the static portion of the design. SLL are not partially reconfigurable.°If ICAP is used for partial bitstream delivery, it must be one located on the Master SLR, which is SLR1 for these devices. Apply a location constraint on the ICAP to the ICAP_X0Y2 or ICAP_X0Y3 locations only. The bitstream format is such that thestandard daisy chain through the four SLRs is maintained. Do not use an ICAP onany of the other SLRs, even if the reconfigurable region is located there.•Dedicated encryption support for partial bitstreams is available natively for 7series devices.•7 series devices can utilize a per-frame CRC checking mechanism, enabled via write_bitstream, to ensure each frame is valid before loading.Note:This feature will be implemented in a future Vivado release.Partial Reconfiguration is a powerful capability within Xilinx FPGAs, and understanding the capabilities of the silicon and software is instrumental to success with this technology. While trade-offs must be recognized and considered during the development process, the overall result will be a more flexible implementation of your FPGA design.Chapter2 Vivado Software FlowSoftware Flow OverviewThe Vivado® Partial Reconfiguration design flow is similar to a standard design flow, with some notable departures. The implementation software automatically manages thelow-level details to meet silicon requirements. The user must provide guidance to define the design structure and floorplan. The steps for processing a PR design can be summarized as follows:1.Synthesize the static and Reconfigurable Modules separately.2.Create physical constraints (Pblocks) to define the reconfigurable regions.3.Set the HD.RECONFIGURABLE property on each Reconfigurable Partition.4.Implement a complete design (static and one Reconfigurable Module perReconfigurable Partition) in context.5.Save a design checkpoint for the full routed design.6.Remove Reconfigurable Modules from this design and save a static-only designcheckpoint.7.Lock the static placement and routing.8.Add new Reconfigurable Modules to the static design and implement this newconfiguration, saving a checkpoint for the full routed design.9.Repeat Step 8 until all Reconfigurable Modules are implemented.10.Run a verification utility (pr_verify) on all configurations.11.Create bitstreams for each configuration.Partial Reconfiguration CommandsThe PR flows are currently only supported through the non-project batch/Tcl interface (no project based commands). Example scripts are provided in the Vivado Design Suite Tutorial: Partial Reconfiguration (UG947) [Ref6], along with step by step instructions for setting up the flows. See that Tutorial for more information.The following sections describe a few specialized commands and options needed for the PR flows. Examples of how to use these commands to run a PR flow are given. For more information on individual commands, see the Vivado Design Suite Tcl Command Reference Guide (UG835) [Ref7].SynthesisSynthesizing a partially reconfigurable design does not require any special commands, but does require bottom-up synthesis. There are currently no unsupported commands for synthesis, optimization, or implementation.These synthesis tools are supported:•XST•Synplify•Vivado Synthesismodules.This document only covers the Vivado Synthesis flow. For information on the other flows, refer to the XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices (UG687) [Ref8], or the Synopsys Synplify documentation.Synthesizing the Top LevelYou must have a top-level netlist with a black box for each Reconfigurable Module (RM). This requires the top-level synthesis to have module/entity declarations for the partitioned instances, but no logic – the module is empty.The top-level synthesis will infer or instantiate I/O buffers on all top level ports; I/O logic inside of a Reconfigurable Module is not supported. For more information on controlling buffer insertion, refer to the Vivado Design Suite User Guide: Synthesis (UG901) [Ref9].synth_design -flatten_hierarchy rebuilt -top <top_module_name> -part <part>Synthesizing Reconfigurable ModulesBecause each Reconfigurable Module must be instantiated in the same black box in the static design, the different versions must have identical interfaces. The name of the block must be the same in each instance, and all the properties of the interfaces (names, widths, direction) must also be identical. Each configuration of the design will be assembled like a flat design.To synthesize a Reconfigurable Module, all buffer insertion must be turned off. This can be done in Vivado Synthesis using the synth_design command in conjunction with the -mode out_of_context switch:synth_design -mode out_of_context -flatten_hierarchy rebuilt -top<reconfig_module_name> -part <part>The synth_design command synthesizes the design and stores the results in memory. In order to write the results out to a file, use:write_checkpoint <file_name>.dcpIt is recommended to close the design in memory after synthesis, and run implementation separately from synthesis.Reading Design ModulesIf there is currently no design in memory, then a design must be loaded. This can be done in a variety of ways, for either the static design or for Reconfigurable Modules. After configurations have been implemented, checkpoints will be exclusively used to read in placed and routed module databases.Table 2-1:synth_design OptionsCommand Option Description-mode out_of_context Prevents I/O insertion for synthesis and downstream tools. The out_of_context mode will be saved in the checkpoint if write_checkpoint is issued.-flatten_hierarchy rebuilt There are several values allowed for -flatten_hierarchy , but rebuilt is the recommended setting for PR flows.-top This is the module/entity name of the module being synthesized.-partThis is the Xilinx ® part being targeted (for example,xc7k325tffg900-3)Method 1: Read Netlist DesignThis approach should be used when modules have been synthesized by tools other than Vivado Synthesis.read_edif <top>.edf/edn/ngcread_edif <rp1_a>.edf/edn/ngcread_edif <rp2_a>.edf/edn/ngclink_design -top <top_module_name> -part <part>Method 2: Open/Read CheckpointIf the static (top-level) design has synthesis or implementation results stored as a checkpoint, then it can be loaded using the open_checkpoint command. This command reads in the static design checkpoint and opens it in active memory.open_checkpoint <file>If the checkpoint is for a reconfigurable module (i.e., not for static), then the instance name must be specified using read_checkpoint -cell . If the checkpoint is a post-implementation checkpoint, then the additional -strict option must be used as well. This option can also be used with a post-synthesis checkpoint to ensure exact port matching has been achieved. To read in a Reconfigurable Module's checkpoint, the top-level design must already be opened, and must have a black box for the specified cell. Then the following command can be specified:read_checkpoint -cell <cellname > <file> [-strict]Table 2-2:link_design Options Command Option Description -partThis is the Xilinx part being targeted (for example, xc7k325tffg900-3)-top This is the module/entity name of the module being implemented. This switch can be omitted if set_propertytop <top_module_name> [current_fileset] is issued prior to link_design .Table 2-3:read_checkpoint Switches Switch Name Description -cellUsed to specify the full hierarchical name of the Reconfigurable Module.-strict Requires exact ports match for replacing cell, and checks that part, package, and speed grade values are identical. Should be used when restoring implementation data.<file>Specifies the full or relative path to the checkpoint (DCP) to be read in.。
Entrust Adaptive Issuance Instant ID 产品说明说明书
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PSLT - Magento Commerce Pro Cloud (2020V2) 说明书
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Reflection ZFE June 2017 说明书
Evaluating Reflection ZFEJune 2017If you need terminal emulation, but managing software across your desktops is costly...take a look at Reflection ZFE! Reflection ZFE dramatically lowers the cost and effort of implementing changes across your enterprise.Reflection ZFE provides zero-footprint terminal emulation that delivers browser-based HTML5 access to 3270, 5250, VT and UTS host applications without the need to touch the desktop or install and manage Java runtime environments. A centralized administrative location reduces IT costs and desktop management time while efficiently providing and delivering host access to end users.Three reasons you need Reflection ZFEZero-footprint means something. It means lowering IT costs by:1.Forgetting about desktop software management and dependencies.2.Centralizing control of all host access to mainframe applications for both user provisioning and security requirements.3.Gaining insight into end-user host-access using centralized metering and reporting to optimize computing resources.Z ERO -FOOTPRINT SECURE DESKTOP MANAGEMENT Reflection ZFE uses HTML5 to access 3270, 5250, VT and UTS host sessions. You do not need to install or manage Java on your desktops. Communication is protected using HTTPS, SSL/TLS, and SSH security. C ONTROL USER ACCESSYou have a single web-based console and from that central location, you confirm user authentication and grant access to host sessions. A simple URL provides users with quick and secure access to their host sessions.With Active Directory/LDAP integration, you leverage your existing trusted user directory.OPTIMIZE YOUR COMPUTING RESOURCESIdentifying those users who are accessing your host systems, and those who need access, is necessary tooptimize your computing resources and to provide efficient session allocation. With Reflection ZFE you have centralized logging capabilities to monitor, report, andidentify session volumes and provision user access rights.How does it work?Reflection ZFE provides true zero-footprint 3270, 5250, VT, UTS, SSH terminal emulation in a web browser. Thismeans there is no Java runtime required and no software deployed to your desktops.It is a simple solution. Reflection ZFE drives down IT costs. You have eliminated the need to touch the desktop.R EFLECTION ZFE COMPONENTS♦Host Access Management and Security Server The Host Access Management and Security Server (MSS) provides an Administrative Console, a web-based centralized location where you can add, edit, and delete terminal sessions. MSS is part of thebroader Micro Focus story and is compatible with other Micro Focus products. ♦Session ServerThe session server is an NT service or UNIX daemon that provides the engine that runs host sessions.Multiple session servers can serve up tens ofthousands of sessions and provide efficient and rapid access to your host data.♦Web ClientThe web client is the web-based terminal emulatorwhere your users can easily access authorizedsessions from any platform and from any location.The Web client provides macros, keyboard and colormapping, on-screen keyboard, copy/pastefunctionality, host-initiated screen updates, andIND$File file transfer capabilities.B ROWSER AND OPERATING SYSTEM SUPPORTReflection ZFE is a 64-bit product and supports Google Chrome, Mozilla Firefox, and Microsoft Internet Explorer and Edge browsers, as well as these minimum supported platforms:♦Windows 2008 Server♦Solaris 10♦Red Hat Enterprise Linux 6.x♦SUSE Enterprise Linux 11.x♦AIX 6.x♦zLinux (SUSE E11.x and RHEL6.x)S ECURITY CONSIDERATIONSWhen you open up your legacy hosts to users outside the corporate firewall - business partners, remote users, mobile sales personnel, and others - you need to shield your information from known security threats. With Reflection ZFE, you can provide secure web-to-host access to all your users, whether they’re around the corner or around the world. Reflection ZFE, along with the MSS, provides HTTPS connections and a variety of authorization and authentication options.Reflection ZFE supports the TLS and SSH protocols to protect mission-critical data. To secure your passwords and other sensitive data, use the HTTPS protocol, which provides TLS encryption. Supported cipher suites include AES128, 168-bit Triple DES, and other strong ciphers, ensuring confidentiality and integrity of data over the Internet and other insecure networks.Reflection ZFE can be connected securely to the browser, the host, and the management server.Installing Reflection ZFEIf you don’t have our software yet, go to http:///Evals/Evaluate.htm and fill out an evaluation request form. You’ll be sent an e-mail message with instructions to download and install Reflection ZFE.If you have questions about using the download site, see Using the Micro Focus Downloads Web Site (FAQ).The installation wizard walks you through the installation process.G ETTING S TARTEDAfter successfully installing Reflection ZFE, make sure that you are pointing to the Management and Security Server you want to use. MSS uses an activation file to provide product-specific functionality.After installing, you should have the proper activation file in place. However, you can import an activation file from the Micro Focus download location or use an existing Host Access Management Server that has already been installed. Activation file names use this format:activation.<module_name>.jawConfiguring Reflection ZFE as an administratorYou can supply an end user with a browser-based terminal emulation session following these steps:1.Open the Administrative Console.2.Add a new session.3.Configure settings.4.Assign a user to a session.O PEN THE A DMINISTRATIVE C ONSOLEFrom the Micro Focus Reflection ZFE Start menu, open Administrative Console.Log on as administrator, using the password you specified during installation.C REATE A NEW SESSIONClick Add to create a new session in the AdministrativeConsole Session Manager.2If it isn’t already selected, choose Reflection ZFE as the session type, enter a session name, and click Launch to start configuring the Reflection ZFE session for the server listed at the ZFE server address.TIP: You can create a direct link to a specific Reflection ZFE session using the following format:<zfe-session-server:port>/zfe/?name=<session-name>Users can use this link to directly launch a Reflection ZFE web session.CONFIGURE SETTINGS AND MAP KEYSThe Reflection ZFE web client Connection panel is where you configure host settings, map keys and colors, enable hotspots. macro, and file transfer capabilities, as well as provide connection information.Connection settings vary depending on the host type.ASSIGN USERS TO SESSIONSUsing the URL you provide, each user will have access to only the sessions you assign to him. One user can be assigned to multiple sessions.Authentication and authorization is used to validate the identity of a user and the method you want to use to map sessions to individual users or groups of users.You have a list of created and configured sessions, assigned to specific users, and available to them using the URL you provided. The Reflection ZFE web client interface is simple and easy for your users to navigate. Navigating the web clientHow will your users interact with the web client?It really is as simple as clicking a link. The connection URL to the Reflection ZFE web client usually looks something like this:https://:port/zfeAs an administrator you can share the primary Reflection ZFE login URL with your users. This address opens the web client and provides access to the Reflection ZFE sessions assigned to them. Users may have to login if configured as such.THE T OOLBAR AND S ESSION T ABSDisconnecting, closing and opening new sessions, and other functions, such as recording macros, are available from the toolbar.Users can switch between open sessions using the session tabs and interact with the terminal emulator via an on-screen keyboard available from the Quick Keys icon. The Macro icon provides access to all macros associated with the session by the administrator. Depending on user preferences set by the administrator, users can modify display settings, record macros, map colors, and access file transfer capabilities.Simplify Migration and SupportMicro Focus has been developing IT solutions that support emerging technologies for nearly 30 years. As your business continues to evolve, Micro Focus is committed to building solutions that maximize your IT investments andallow your IT organization to be as flexible as possible.3R EFLECTION ZFE IS THE ANSWERMigrating, patching, updates, and desktop configurations can be time consuming and costly. Reflection ZFE and the whole suite of Reflection products can provide a single solution. You can successfully standardize on Micro Focus and Reflection ZFE.F OR M ORE I NFORMATION ON R EFLECTION ZFEFor more information about Reflection ZFE, review the product Help. For further assistance regarding evaluation software and product updates, visit our Technical Support site at /Support/.4。
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STAPL:The Standard Template Adaptive Parallel Library∗Nancy M.Amato Lawrence RauchwergerParasol Lab,Dept.of Computer Science,Texas A&M University{amato,rwerger}@1IntroductionIn sequential computing,standardized libraries are essential for simplifying program development.They allow rou-tine problems to be handled economically and increase the scale of problems that can be addressed.They do so by providing routines,types,and frameworks for common operations(in general programming and in specificfields)so programmers can concentrate on higher level problems.Due to the added complexity of parallel programming,the potential impact of libraries could be even more profound than for sequential computing.Good parallel libraries can insulate less experienced users from much of the complexity of parallelism by providing routines that are easily in-terchangeable with their sequential counterparts,while allowing more sophisticated users sufficient control to achieve higher performance gains.There have been some successful specialized libraries of elementary parallel algorithms [3,4,15].However,designing general,efficient,and portable parallel libraries is a challenge that has not yet been met,mainly due to the difficulty of managing concurrency and the diversity of parallel and distributed architectures.STAPL(the Standard Template Adaptive Parallel Library)[2,12]is a framework for parallel processing consisting of C++library code,design rules for extending that code,and optimization tools.Its goal is to allow the user to work at a high level of abstraction and hide many details specific to parallel programming,while allowing a high degree of portability and performance adaptability across computer systems.STAPL’s core is a library of ISO Standard C++ components with interfaces similar to the(sequential)ISO C++standard library.By providing its facilities within an ISO standard mainstream language,STAPL gives developers of parallel software the benefits of the huge investment in mainstream tools,compilers,and libraries.Conversely,STAPL makes parallel techniques accessible to mainstream programmers by providing a degree of automatic parallelization and by providing its facilities within mainstream development environments and on mainstream hardware.As the price of parallel systems drops within the reach of even modest(in terms of size and programming skills)computing establishments,this could have an important long-term impact.STAPL offers the parallel system programmer a shared object view of the data space.The objects are distributed across the memory hierarchy which can be shared and/or distributed address spaces.Internal STAPL mechanisms assure an automatic translation from one space to another,presenting to the less experienced user aflat,UMA like, unified data space.For more experienced users the local/remote distinction of accesses can be exposed and perfor-mance enhanced.STAPL supports the SPMD model of parallelism with essentially the same consistency model as that of OpenMP.To exploit large systems like the DOE machines and IBM’s BlueGene/L,STAPL allows for(recursive) nested parallelism(as in NESL[4]).STAPL’s ARMI communication library[14]and run-time system are compatible with both message passing(e.g.,MPI)and shared memory systems(e.g.,OpenMP).Because performance of parallel algorithms is sensitive to system architecture(latency,topology,etc.)and to application data(data type,distribution, density,etc.),STAPL is designed to continually adapt to the system and the data at all levels–from selecting the most appropriate algorithmic implementation[17]to balancing communication granularity with latency by self-tuning the message aggregation factor,etc.An important goal of STAPL is to provide an easily extensible base and building blocks for the development of domain specific libraries by specialists in the domain who are not necessarily expert parallel programmers.To ensure its applicability and usability,STAPL is being refined and extended through the concurrent development of domain specific libraries for particle transport computations(computational physics)and protein folding simulation (computational biology).Both applications,like many problems in the physical and life sciences,make heavy use of dynamic linked data structures(e.g.,graphs).Hence,in addition to the usual vector-based operations,STAPL provides built-in support for irregular data structures such as lists,sparse matrices,and graphs.∗This research supported in part by NSF Grants EIA-0103742,ACR-0081510,ACR-0113971,CCR-0113974,ACI-0326350,and by the DOE.STAPL A VTL CHARM++CHAOS++CILK NESL POOMA PSTL SPLIT-C Paradigm S/M S M S S/M S/M S S S Architecture S/D D S/D D S/D S/D S/D S/D S/D Nested Par.yes no no no yes yes no no yes Adaptive yes no no no no no no no no Generic yes yes yes yes no yes yes yes no Irregular yes no yes(limited)yes yes yes no yes yes Data decomp auto/user auto user auto/user user user user auto/user user Data map auto/user auto auto auto/user auto auto user auto/user autoScheduling block,dyn,partial self-sched user-MPI-basedprioritizedexecutionbased ondata decom-positionworkstealingwork anddepthmodelpthreadschedulingTulip RTS userOverlapcomm/compyes no yes no no no no no yesTable1:Related Work.For the paradigm,S and M denote SPMD and MIMD,resp.For the architecture,S and D denote shared memory and distributed,respectively.2Related WorkThere is a relatively large body of work that has similar goals to STAPL.Table1gives an overview of selected projects. We briefly comment on some and attempt to compare them with STAPL.For further work in this area see[18].The Parallel Standard Template Library(PSTL)[11,10]has similar goals to STAPL;it uses parallel iterators in place of STL iterators and provides some parallel algorithms and containers.NESL[4],CILK[7]and SPLIT-C[6]provide the ability to exploit nested parallelism through their language support(all three are extended programming languages with NESL providing a library of algorithms).However,only STAPL is intended to automatically generate recur-sive parallelization without user intervention.Most listed packages(STAPL,Amelia[16],CHAOS++[5]and to a certain extent CHARM++[1])use a C++template mechanism and assure good code reusability.STAPL emphasizes irregular data structures like trees,lists,and graphs,providing parallel operations on such structures.Charm++and CHAOS++also provide support for irregular applications through their chare objects and inspector/executor,respec-tively.POOMA[13],PSTL[11,10],and STAPL borrow from the STL philosophy,i.e.,containers,iterators,and algorithms.STAPL’s RMI-based communication infrastructure is extremelyflexible,supporting overlapping of com-munication/computation,and the simultaneous use of both message passing and shared memory(MPI and OpenMP). Charm++provides similar support through message driven execution and a dynamic object creation mechanism.The split phase assignment(:=)in Split-C also allows for overlapping communication with computation.STAPL is distinguished by its emphasis on dynamic and aggressive adaptive capabilities which are critical for STAPL’s support of irregular applications that rely on dynamic linked data structures.For example,STAPL provides support for both automatic and user specified policies for scheduling,data decomposition and data dependence en-forcement and it is unique in its goal to automatically select the best algorithm from its library options by analyzing the data,architecture and current run-time conditions.3STAPL ArchitectureThe STAPL software infrastructure consists of platform independent and platform dependent components.These are revealed to the programmer at an appropriate level of detail through a hierarchy of abstract interfaces.STAPL components.The platform independent STAPL components include the core parallel library and an abstract interface to the communication library and run-time system.The core library consists of parallel algorithms(pAl-gorithms)and distributed data structures(pContainers).A pContainer is the parallel equivalent of an STL container. Its data is distributed,but it offers the user a shared object view.The pContainer distribution can be specified by the user or computed automatically using methods in STAPL’s optimization library.The shared object view is achieved through an internal object translation method that can map,transparently,any part of an object to the thread to which it belongs.A pAlgorithm is the parallel equivalent of an STL algorithm.To bind pAlgorithms to pContainers we introduce the pRange class which supports random access to distributed pContainer data.Random access is essential to parallel processing–every thread must have independent access to its own data to process it in parallel.Adaptive behavior is supported by providing algorithms with the same interface and functionality,but which perform differently depending on the architecture and data involved.Data dependences in pAlgorithms are encoded by dependence graphs (DDGs)stored in the pRange and are enforced at run-time.The traversal of the DDG,i.e.,the execution schedule, can be selected from a set of STAPL-provided policies(e.g.,wavefront,GSS,etc),or can be provided by the user. Communication and synchronization use the remote method invocation(RMI)communication abstraction that assures mutual exclusion at the destination but hides the lower level implementation(e.g.,MPI,OpenMP).The STAPL run-time system(RTS)is a collection of platform specific components that needs to be adapted when-ever STAPL is ported to a new system.The executor object is responsible for the parallel execution of pAlgorithmswhile respecting the constraints imposed by the pRange’s DDG.Here we detect and translate remote references to a shared object,and translate the generic RMI to MPI,OpenMP,pthreads,or native communication primitives.We tailor the memory management to the specifics of the hardware,e.g.,processor aware allocation,mapping of virtual processor to physical processor,etc.Many low-level optimizations are performed here.The STAPL optimization toolbox provides support for general high-level optimizations,automatic translation of sequential C++STL into parallel STAPL,and for optimizing domain-specific library extensions.It collects infor-mation about types,algorithm and container usage,and memory layout that can be used for the run-time tuning of programs.It interfaces with the core library and the STAPL RTS.STAPL interfaces.We distinguish two main views of STAPL.From the user’s perspective,STAPL has a three layer, hierarchical architecture whose interfaces incrementally expose information about and control of parallelism,data distribution,and platform dependent features.In contrast,the STAPL optimization tools typically access all STAPL components,from platform independent library components to platform dependent components such as the native communication library.For users,STAPL provides three levels of abstraction appropriate to an application developer(level1),a library developer(level),and a run-time system developer(level3).At the highest level,STAPL offers the application developer an STL compatible interface to a generic parallel machine.Parallel programs can be composed by non-expert parallel programmers using building blocks from the core STAPL ers don’t have to(but can)be aware of the distributed nature of the machine.At the intermediate level,STAPL exposes sufficient information to allow a library developer to implement new STAPL-like algorithms and containers,e.g.,to expand the STAPL base or build a domain specific library.This is the lowest level at which the“usual”user of STAPL operates.The shared object view and abstract interface to the machine and RTS result in platform independent portable code.Nevertheless,remote and local accesses may be distinguished, and a new container class must specify the data types it stores to enable RMI to pack/unpack container objects.For new pAlgorithms,the developer must(provide a method to)define a DDG describing the algorithm’s dependences.At the lowest level,the RTS developer has access to the implementation of the communication and synchronization library,the interaction between OS,STAPL thread scheduling,memory management and machine specific features such as topology and memory subsystem organization.4Program Development with STAPLThis section illustrates STAPL’sflexibility and ease of use,and provides performance results for two case studies using STAPL.v0.All experiments were run on a16processor HP V2200with4GB of memory running in dedicated mode. Speedups reported represent the ratio between the sequential algorithm’s running time and its parallel counterpart. 4.1Molecular Dynamics(automatic vs.manual STL to STAPL translation)We used STAPL to parallelize a molecular dynamics code written by Danny Rintoul at Sandia National Lab that makes extensive use of STL algorithms and containers.Both(i)automatic translation and(ii)manual recoding were used to translate the STL program into an equivalent STAPL program.The section of code parallelized with STAPL accounts for40%to49%of the sequential execution time.It uses STL algorithms(e.g.,for each,transform,accumulate)and parallel push back∗operations on vectors.STAPL provides two ways to automatically translate STL code to STAPL code:full translation(the entire code is translated),and partial translation(only user defined sections of the code are translated).In both full and partial translation the user must decide which sections of the STL code are safely parallelizable.Without compiler support,it is not possible to identify data dependencies.For full translation,the only change necessary is to add STAPL header files.For partial translation,the sections to be parallelized are enclosed by the user inserted STAPL preprocessing directives#include<start translation>,and#include<stop translation>(see Figures1and2).For the molecular dynamics code we have used partial translation.Our experimental results,shown in Figure3,indicate that although automatic translation incurs some run-time overhead,it is simpler to use and the performance is very close to hand parallel(less than5%performance deteriora-tion).In both cases,the STAPL code achieved scalable speedups.4.2Generic Particle Transport Solver(Programming in STAPL)Within the framework of our DOE ASCI project we have developed,from scratch,a particle transport library.It is a numerical intensive parallel application written entirely in C++(so far,about25,000lines of code).Its purpose is the development of a general testbed for solving transport problems on regular and arbitrary(irregular)grids.Its central ∗A push back operation appends an element to the end of a container.std::vector<int>v(400,000);int sum=0;...//Execute computation on v std::accumulate(v.begin(),v.end(),sum); ...//Rest of the computationFigure1:Original STL codeFigure2:STL to STAPL code Figure3:Hand parallel MD.algorithmic component is a discrete ordinate parallel sweep across a spatial grid in each direction of particle travel [8,9]which accounts for50%to80%of total execution time.Due to the very large data sizes and the enormous amount of computation the code has to scale up to10,000processors.The primary data structure is the spatial discretization grid,which is provided as input.The primary algorithm is called a solver,which usually consists mainly of grid sweeps.The solver method may also be given.We started with a sequential version of the code written in STL and then transformed it using the pfor each template,which applies a work function to all the elements in a domain.There are three important routines:particle scattering(fully parallel),sweep(partially parallel),and a convergence test(reduction).The pContainer that receives the input data is called the pGrid;it represents a distributed spatial discretization grid and is a pGraph.There is one pRange for each direction of particle travel,all built on the same pGrid,but with different DDGs.The scattering routines are fully parallel.For the partially parallel sweep loop(which performs graph traversals),the DDGs are computed in the application and passed to STAPL.For the scattering routines,the work function is a routine that computes scattering for a single spatial discretization unit(Cell Set).For the sweep,the work function sweeps a Cell Set for a specific direction of particle travel.For the convergence routines,the work function tests convergence for a Cell Set.The work function(sweep)was written by the physics/numerical analysis team unaware of parallelism issues.We just needed to put a wrapper around it(the interface required by STAPL).Experiments were run in the parallel queue(not dedicated)on a SGI Origin2000server with32R10000processors and8GB of physical memory.The input data was a3D mesh with24x24x24nodes.The energy discretization consisted of12energy groups.The angular discretization had228angles.The six parts of the code parallelized with STAPL, their execution profile and speedup are shown in Table4.Speedups are for16processors in the experimental setup described above.Our speedups and efficiencies for up to25processors are shown in Figure4.Code Region%Seq.Speedup Create computational grid10.0014.50 Scattering across group-sets0.05N/A Scattering within a group-set0.4015.94 Sweep86.8614.72 Convergence across group sets0.05N/AConvergence within group sets0.05N/ATotal97.4614.70Figure4:(a)Profile and speedups on16processor SGI Origin2000.(b)Speedup,and(c)parallel efficiency(average)References[1]The CHARM++Programming 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