EDA程序改错题

程序改错题1.已知sel为STD_LOGIC_VECTOR(1 DOWNTO 0)类型的信号，而a、b、c、d、q均为STD_LOGIC 类型的信号，请判断下面给出的CASE语句程序片段：●CASE sel IS●WHEN“00”=>q<=a；●WHEN“01”=>q<=b；●WHEN“10”=>q<=c；●WHEN“11”=>q<=d；●END CASE；●答案：CASE语句缺“WHEN OTHERS”语句。

2.已知data_in1, data_in2为STD_LOGIC_VECTOR(15 DOWNTO 0) 类型的输入端口，data_out为STD_LOGIC_VECTOR(15 DOWNTO 0)类型的输出端口，add_sub为STD_LOGIC类型的输入端口，请判断下面给出的程序片段：●LIBRARY IEEE；●USE IEEE.STD_LOGIC_1164.ALL；●ENTITY add IS● PORT（data_in1, data_in2：IN INTEGER；● data_out：OUT INTEGER）；●END add；●ARCHTECTURE add_arch OF add IS●CONSTANT a:INTEGER<=2；●BEGIN●data_out<=( data_in1+ data_in2) * a；●END addsub_arch；答案：常量声明时赋初值的“<=”符号应改用“:=”符号。

3.已知Q为STD_LOGIC类型的输出端口，请判断下面的程序片段：●ARCHITECTURE test_arch OF test IS●BEGIN●SIGNAL B：STD_LOGIC；●Q<= B；END test_arch答案：信号SIGNAL的声明语句应该放在BEGIN语句之前。

4.已知A和Q均为BIT类型的信号，请判断下面的程序片段：●ARCHITECTURE archtest OF test IS●BEGIN●CASE A IS●WHEN ‘0’=>Q<=‘1’；●WHEN ‘1’=>Q<=‘0’；●END CASE；●END archtest；答案：CASE语句应该存在于进程PROCESS内。

三．判断改错题（3分×6题）（评分标准：给出正确答案1分/题；答案基本正确0.5分/题。

）1．已知A和Q均为BIT类型的信号，请判断下面的程序片断：ARCHITECTURE test OF test ISBEGINCASE A ISWHEN '0' => Q <= '1' ；WHEN '1' => Q <= '0' ；END CASE ；END test ；【参考答案】： CASE语句应该存在于进程PROCESS内。

2．已知start为STD_LOGIC类型的信号，sum是INTEGER类型的信号，请判断下面的程序片断：PROCESS (start)BEGINFOR i IN 1 TO 9 LOOPsum := sum + i ；END LOOP ；END PROCESS ；【参考答案】： sum是信号，其赋值符号应该由“:=”改为“<=”。

3．已知Q为STD_LOGIC类型的输出端口，请判断下面的程序片断：ARCHITECTURE test OF test ISBEGINSIGNAL B ：STD_LOGIC ；Q <= B ；END test ；【参考答案】：信号SIGNAL的申明语句应该放在BEGIN语句之前。

4．已知A和B均为STD_LOGIC类型的信号，请判断下面的语句：A <= '0' ；B <= 'x' ；【参考答案】：不定态符号应该由小写的‘x’改为大写的‘X’。

5．已知A为INTEGER类型的信号，B为STD_LOGIC类型的信号，请判断下面的程序片断：ARCHITECTURE test OF test ISBEGINB <= A ；END test ；【参考答案】： A和B的数据类型不一致，不能相互赋值。

6．已知sel是STD_LOGIC_VECTOR(1 DOWNTO 0)类型信号，而a、b、c、d、q均为STD_LOGIC 类型信号，请判断下面给出的CASE语句：CASE sel ISWHEN “00” => q <= a ；WHEN “01” => q <= b ；WHEN “10” => q <= c ；WHEN “11” => q <= d ；END CASE ；【参考答案】： CASE语句缺“WHEN OTHERS”语句。

四、判断下面程序中是否有错误，若有错误请改正；1、SIGNAL A,EN:STD_LOGIC;PROCESS(A,EN)VARIABLE B:STD_LOGIC;BEGINIF EN=‘1’ THENB<=A;END ;END PROCESS;2、RCHITECTURE ONE OF SAMPLE ISVARIABLE A，B，C：INTEGER；BEGINC<=A+B；END ;五、判断下列程序是否有错误，如有则指出错误所在（10分）程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY zyt12 ISPORT(R,EN,CP: IN bit;Q: BUFFER STD_LOGIC_VECTOR(0 DOWNTO 3);CO: OUT STD_LOGIC);END zyt;ARCHITECTURE c10 OF zyt12BEGINCO<='1' WHEN(EN='1' AND Q="1011") ELSE；'0';PROCESS(R,CP)BEGINIF R='1' THENQ<="0000";ELSIF (CP'EVENT AND CP<='1') THENIF EN='0' THENQ<=Q;ELSIF Q="1011" THENQ<=‘0000’;ELSEQ:=Q+1;END IF;END PROCESS;END one;仔细阅读下列程序，回答问题LIBRARY IEEE; -- 1 USE IEEE.STD_LOGIC_1164.ALL; -- 2ENTITY LED7SEG IS -- 3 PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- 4CLK : IN STD_LOGIC; -- 5 LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); -- 6 END LED7SEG; -- 7 ARCHITECTURE one OF LED7SEG IS -- 8 SIGNAL TMP : STD_LOGIC; -- 9BEGIN -- 10 SYNC : PROCESS(CLK, A) -- 11BEGIN -- 12 IF CLK'EVENT AND CLK = '1' THEN -- 13TMP <= A; -- 14 END IF; -- 15 END PROCESS; -- 16 OUTLED : PROCESS(TMP) -- 17 BEGIN -- 18 CASE TMP IS -- 19WHEN "0000" => LED7S <= "0111111"; -- 20WHEN "0001" => LED7S <= "0000110"; -- 21WHEN "0010" => LED7S <= "1011011"; -- 22WHEN "0011" => LED7S <= "1001111"; -- 23WHEN "0100" => LED7S <= "1100110"; -- 24WHEN "0101" => LED7S <= "1101101"; -- 25WHEN "0110" => LED7S <= "1111101"; -- 26WHEN "0111" => LED7S <= "0000111"; -- 27WHEN "1000" => LED7S <= "1111111"; -- 28WHEN "1001" => LED7S <= "1101111"; -- 29END CASE; -- 30 END PROCESS; -- 31 END one; -- 32 1.在程序中存在两处错误，试指出，并说明理由：第14行 TMP附值错误第29与30行之间，缺少WHEN OTHERS语句2.修改相应行的程序：错误1 行号：9程序改为：TMP : STD_LOGIC_VECTOR(3 DOWNTO 0);错误2 行号： 29 程序改为：该语句后添加 WHEN OTHERS => LED7S <= "00000001、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4B ISPORT (CLK，RST，ENA: IN STD_LOGIC;OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END CNT4B;ARCHITECTURE behav OF CNT4B ISSIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK, RST, ENA)BEGINIF RST = '1' THEN CQI <= '0000'; "0000" ELSIF CLK'EVENT AND CLK = '1' THENIF ENA = "1" THEN CQI <= CQI + 1; '1'ELSE CQI <= "0000";END IF; END IF; OUTY <= CQI ;END PROCESS;COUT<=CQI(0) AND CQI(1) AND CQI(2) AND CQI(3);END behav;2、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLK_6D ISPORT (CLK,RST: IN STD_LOGIC;CLK_OUT: OUT STD_LOGIC);END CLK_6D;ARCHITECTURE ONE OF CLK_6D ISVARIABLE TEMP:STD_LOGIC; SIGNALBEGINPROCESS(CLK)VARIABLE CNT6D: INTEGER RANGE 0 TO 3;CONSTANT SIGN: INTEGER:=2;BEGINIF (RST = “1”) THEN TEMP <= “0”; '1' , '0'ELSIF CLK'EVENT AND CLK='1' THEN (CLK'EVENT AND CLK='1')IF (CNT6D = SIGN) THENCNT6D := 0;TEMP <= NOT TEMP;ELSE CNT6D := CNT6D+1;END IF;END IF;END PROCESS;CLK_OUT <= TEMP;END ONE;3、library ieee;use ieee.std_logic_1164.all;entity encoder isport(b: in std_logic(7 downto 0);b:in std_logic_vector(7 downto 0)y: out std_logic(2 downto 0)); y:out std_logic_vector(2 downto 0) end encoder;architecture one of encoder isbeginprocess (b)begincase b iswhen "01111111"=>y<="111";when "10111111"=>y<="110";when "11011111"=>y<="101";when "11101111"=>y<="100";when "11110111"=>y<="011";when "11111011"=>y<="010";when "11111101"=>y<="001";when "11111110"=>y<="000";when others => null;end case;end process;end one;4、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY counter ISPORT ( reset: IN STD_LOGIC;clock: IN STD_LOGIC;num: buffer integer range 0 to 3；多一个“；”);END;ARCHITECTURE behav OF jishu IS jishu改为 counter BeginProcess(reset,clock)BeginIf reset=’1’ thennum<=0;Elsif rising_edge(clock) thenIf num=3 thennum<=0;elsenum<=num+1;少end if; end if;end process;end;5、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED; STD_LOGIC_UNSIGNED.ALL ENTITY LX3_2 ISPORT(CLK,CLR,OE:IN BIT;D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END LX3_2;ARCHITECTURE struc OF LX3_2 ISVARIABLE Q_TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL BEGINPROCESS(CLR) PROCESS(CLK)BEGINIF CLR='0' THEN Q_TEMP<='00000000'; "00000000"ELSIF CLK='1' THENQ_TEMP<=D;ELSE Q_TEMP<=Q_TEMP;END IF;END PROCESS;Q<=Q_TEMP WHEN OE='1' ELSE"ZZZZZZZZ";END struc;6、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY LX3_2 ISPORT( A :IN STD_LOGIC_VECTOR(3 DOWNTO 0);B :IN STD_LOGIC(3 DOWNTO 0); STD_LOGIC_VECTORGT,LT,EQ: OUT STD_LOGIC);END LX3_2;ARCHITECTURE one OF LX8_2 IS LX3_2BEGINPROCESS(A,B)BEGINGT<='0';LT<='0';EQ<='0';IF A>B THEN GT<=”0”; '0'ELSIF A<B THEN LT<=”0”; '0'ELSE EQ<=”0”; '0'END IF;END PROCESS;END one;1、在程序中存在两处错误，试指出，并说明理由：错误1原因：case顺序语句必须放在进程语句Process内。