Contact and Interconnection

Chapter 8 Contact and Interconnection
I.Contact and Interconnection–Increasing importance for
VLSI/ULSI Technology
II. Advanced Contact & Interconnection Technology –Integration of various thin film materials and process techniques
III. Contact Resistance
IV. Al/Si Ohmic Contact and Interconnect
V. Cu Interconnection by Damascene Technology
VI. Silicide. Polycide and Salicide
Chapter 8 Contact and Interconnection
I. Contact and Interconnection–Increasing importance for
VLSI/ULSI Technology
Requirements and problems of C&I for IC Progress
(1) High Speed:
Low interconnect resistance
Low contact resistance
Low capacitance
Problem: RC ↑
wt L R ρ= (+ Contact resistance)
i
i t Lw C ε= (+ Line-to-Line C) i i s t R L RC ε2= ↑
(2) High reliability
Uniform metal/Si interface
Low electromigration
Problem:
-- Metal/Si: interdiffusion &
interaction ÆAl “Spiking” –Contact
failure
-- Electromigration – void formation
– interconnect failure
(3) High density
-- Smaller contact, more narrow metal line
-- Multilevel metallization
N
PG A 3
/2=A – Chip area
G – Number of IC gates
P – Metal pitch (line width + space )
N – Number of metal levels
Problems: Increasing process complexity
∴C&I – One of the bottlenecks for deep sub µ IC technology!
II. Advanced Contact & Interconnection Technology –Integration of various thin film materials and process techniques
1.Various materials for C&I
z For early IC: Al
z At medium stage: (≥2-3 µm)
Al + Doped Poly-Si
z For Advanced VLSI/ULSI:
(1)High conductive metal & its
alloy: Al, Al-Si, Al-Si-Cu, Cu
(2) Heavily doped poly Si: n+-
Poly-Si, p+-Poly-Si
(3) Refractory metals: W, Ta ...
(4) Metal silicide: TiSi2 , CoSi2 ,PtSi , NiSi, WSi2
(5) Other metal alloy and compound: TiN , WN …
+ Different dielectric films:
Inorganic: SiO2 , PSG , BSG , BPSG
Organic polymers
bination of various processing technology
(1) Self-aligned technology:
*Self-aligned poly-Si gate and polycide gate technology
*Self-aligned silicide contact and gate technology (salicide)
(2) Diffusion barrier technology
(3) Multilevel interconnection
CMOS: 0.5 µm---3-4 Levels; 0.35 µm---4-5 Levels;
130nm--8Levels; 90nm--9Levels; 65nm--10Levels (by ITRS2001) (4) Layered matallization structure
Si (Al) / Contact (adhesion) layer
/ Diffusion barrier layer
/ Vertical interconnect
/ Lateral interconnect
/ Anti-reflection (capping) coating
(5) New materials and process techniques supporting above technologies
z Typical cross section of future advanced CMOS interconnection
Future C & I
Technology
depends on:
*Introduction of
new materials
*Integration of
new processes and
structures
3.Various thin film deposition, formation and etching
technologies
Sputtering
Evaporation
CVD
Solid state reaction
Reactive ion etching
Selective etching (wet & dry)
Planarization techniques: CMP; Etching back process 4.Requirements for Gate Electrode and Interconnects
Materials
-- Low resistivity
-- High temperature stability (~1000°C)
-- Fine line etching capability
-- Easy to passivation
-- Chemical stability to the commonly used solutions in IC process
-- Low contact resistance with Si & metals
-- Resistance to Electromigration
5. Requirements for Ohmic Contacts
-- Low contact resistivity
-- Limited interface interaction
-- Interface uniformity
-- Stability
z RC Delay Time of 1 cm interconnect line on SiO 2 (1 µm) / Si for different materials
Material Resistivity (µΩ·cm)Thickness (nm)
R S (Ω/□)RC (ns/cm)Al 2.72500.110.4
Cu 2.02500.080.3W 82500.32 1.1
Mo 82500.32 1.1
TiSi 2152500.6 2.1
CoSi 2152500.6 2.1
NiSi 152500.6
2.1
WSi 270250 2.89.7
MoSi 2~100250413.8TaSi 255250 2.27.6
TiN 502502 6.9
PolySi ~10005002069
III. Contact Resistance
Two types of M/Si contacts
Schottky contact on n --Si
Ohmic contact on n +-Si
z F
or
N D ≤1
017
cm -3 Current flow by
thermionic emission
]1))[exp(/exp(2*−−=KT
qV KT q T A J B φA*: Richardson constant; ΦB : Barrier height
z Specific contact resistance (R c )
)exp(*0KT
q T qA K dJ dV R B
V c φ=== [Ω·cm 2] If ΦB =0.85V → R c =4.7x105Ω·cm 2
ΦB =0.25V → R c =4x10-7Ω·cm 2
R c (on p-Si) < R c (on n-Si)
z For N D > 1019cm -3: Current flow by carrier tunneling
)](*4exp[D
B c N h m A R φεπ≈ ε – Dielectric permittivity;
m* – Effective mass of carrier
A – Constant
Example:
If 2
6101cm R c
•Ω×≈−; for contact hole µµ11×→ Ω==−−100)10(10246R Ω
=×400:5.05.0R µµ∴Lower R c is needed for deep
sub-µ CMOS
z Total resistance of a contact
r=r s +r c r s – spreading resistance of
semiconductor under contact (Ω)
r c – contact resistance (Ω)
Both r s , r c depend on doping and contact size
▲ Typical value of total resistance for a contact: r ≈ 10-100Ω/contact
▲ With shrinkage of contact size lower specific contact resistance is required
IV. Al/Si Ohmic Contact and Interconnect
1. Al -- Extensively used interconnect material for IC
-- No.3 material for Si devices fabrication after Si, SiO2▲ Low Resistivity: P ≈2.7Ω·cm
▲ Compatibility with Si & SiO2
Good adhesion with SiO2 due to
slight reaction to form Al2O3 at
Al/SiO2 interface
▲ Mature Al processing technology
Deposition (evaporation Æ
sputtering)
Etching (wet Æ dry)
2.Two problems
(1) Al spiking
Al melting point -- 660°C
Al-Si eutectic T-- 577°C
At T< 577°C:
z High solubility & diffusivity of Si in
Al: Æ “Etching” of Si by Al
Æ Si, Al interdiffustion
Æ Pits in Si surface Æ Al-Spiking
Æ pn junction failure
z Orientation effect of Al spiking
▲ A Spiking is more severe on (100)
Si-substrate
▲ Reason –anisotropical Al/Si
interface interaction
▲ “Etching” of Si by metal (like
wet etching) – slow etching
planes – {111} Æ (111) planes act
as an etch stop (slow dissolving
planes)
*(111)Si: Triangular pits
*(100)Si: Square – topped
pyramidal pits
In practice : due to residual interfacial SiOx Æ no
uniform interaction Æ Spiking
▲ Alloy transistors of Si & Ge were made on (111) substrate
(2)Al Electromigration
▲ Effect of momentum transfer from electron to metal ions Noticeable in the case of high current density (In IC, current density may: j ≈105 A/cm 2)▲ Metal ion transport flux, j m
KT j e NDZ j m ρ*=
N – Density of metal ions
D – Self-diffusion coeff. of metal
Z* -- Effective charge of ion
Ρ – Resistivity of metal
J – current density in meta l
Æ Hillocks growth toward the positive end
Voids formation near the negative end of the lead Æ Interconnect break, IC failure
▲ Temperature dependence of electromigration failure KT E a e
D D /0−=
E a – Diffusion activation energy
MTF – median time to failure
KT E m a e j A MTF /'−= A’ – constant, m ≈1-3 Experimental MTF for Al evaporated on cold sub. KT
e
ABj MTF /48.0216)(101.4−×= A – Cross section of Al line (cm 2)
B – 1 A 2·hr/cm 6 (a unit conversation constant) For Al evap. on hot sub Ægrain Ç
ÆE a Ç(~0.7eV)ÆMTF Ç
▲ Stress induced migration failure
3. Improvement of Al metallization
(1) Al-Si alloy: Al + 0.5-2% Si
*Reduce Si-dissolution into Al
*Problems: -- Resistivity increasing ;
– Al-doping Æp-type ÆR c Ç
(2) Al-Cu Alloy (+0.5-4% Cu)
Reduce Al electromigration Æ MTF Ç
Problems : ρÇ, Dry etching difficulty
(3) Diffusion barrier between Si & Al: TiW, TiN, TaN…
V. Cu
Interconnection by
Damascene
Technology
z Typical Cu-
interconnection
processing:
(a)沟槽刻蚀
(b) TiN, Cu 淀积
(c) 化学机械抛光
(d) 过抛蚀
(e) TiWN淀积
(f) 化学机械抛光
z Dual Cu Damascene Process
Formation of vertical(via) and
lateral interconnection(line) by
combined Cu damascene process
z Combination of Cu
interconnection with low K
dielectrics material and
process—key of the success of future advanced
interconnection technology
VI. Silicide. Polycide and Salicide
1.Metal Silicides -- Important Si based materials for ULSI (1)Type of silicides:
Variety of different
silicides (>200)
z Transition metal
silicides
*Refractory metal
silicides (from IVb, Vb,
VIb refractory metals)
-- TiSi2,WSi2,MoSi2,TaSi2 …
-- Formation T ≥600°C
-- High melting point
-- Diffusion species during formation – Si
*Near-Noble metal silicides (from VIII group metals)
-- CoSi2,NiSi2,PtSi,NiSi,Pd2Si …
-- Formation T lower (200 - 600°C)
-- Lower melting point
-- Diffusion species during formation –Si, or metal
(2) Properties interesting for IC application
-- Metal-like high conductivity (10-100 µΩ)
-- High T thermal stability
-- Good chemical stability (in oxidizing ambient, wet & plasma chemicals)
-- Uniform silicide / Si interface
▲ Low leakage Schottky barrier contact
▲ Low contact resistance Ohmic contact
(3) Variety of application for microelectronics
-- SBD devices for bipolar IC
-- Ohmic contact
-- Gate electrode for self-aligned device technology in both Si-MOS and GaAs-MESFET-IC
-- Low barrier devices for infrared detector (PtSi/p-Si…) -- Local interconnect
2. Silicide Film Formation Method
(1) Solid state reaction of M/S
-- Different phase at different T
-- MSix/Si interface formed beneath original Si surface
-- Lower ρ than deposited film
-- Possible impurity segregation during reaction
-- Consumption of Si: mM+nSi Æ M m Si n
(t m) (t si) (t silicide)
TiSi2 1.00 2.24 2.50
CoSi2 1.00 3.63 3.49
PtSi 1.00 1.32 1.98
NiSi 1.00 1.84 2.22
Pd2Si 1.00 0.68 1.42 (2) Physical depositon
-- Sputtering from composite targets
-- Co-sputtering (or co-evaporation) from elemental targets -- Low ρ phase formation by thermal annealing
-- composition and stoichiometry control
(3) CVD
-- By chemical reaction Æ WSi2, TiSi2, TaSi2, MoSi2
*WF6(vapor) + 2SiH4(vapor) Æ WSi2(solid) +6HF + H2
*TiCl6+ 2SiH4Æ TiSi2 +4HCl+2H2
-- Better step coverage, higher purity and higher throughput -- CVD WSi2 – more application
As-deposited film ρ≈600-900 µΩ·cm
After annealing ρ≈35-80 µΩ·cm
-- Commercial cold-wall system available
3. Polycide – Composite structure of silicide on poly-Si
▲ Polycide process technology
-- Poly-Si deposition & doping
-- Silicide (e.g. WSi2) deposition
by CVD or PVD
-- Thermal annealing
-- Gate mask lithography
-- Reactive ion etching (RIE) of WSi 2 and poly-Si
-- S/D implant
▲ Advantages
-- Low gate resistance
20-30 Ω⁄□ Æ 1-4Ω⁄□ (Depends on thickness)
-- Remain excellent PolySi/SiO 2/Si interface
-- Poly-Si pad prevents metal diffusion into gate oxide -- Possibility of growing stable SiO 2 ° SiO 2 formation with unchanged silicide film (WSi 2,
TiSi 2 …) by Si consumption from poly-Si layer
° Oxide growth may follow similar kinetics
)(2τ+=+t B AX X or Bt
X =2 For WSi 2/PolySi: Bt
X =82
.1▲ Applications
-- High density memory chips, DRAM, SRAM; -- ASICs 4. Salicide – Self-aligned Silicide Technology
(1) Main process steps:
-- Self-aligned PolySi & S/D
process
-- Dielectric deposition
-- RIE Æ sidewall dielectric
formation on poly-Si line
-- Metal deposition by sputtering (Ti, Co …)
-- 1st step annealing by RTA at lower T Æ reaction on
crystalline Si(S/D) and poly-Si(G)
-- Selective etching Æ Remove metal from FOX and sidewall -- 2nd step annealing by RTA at higher T Æ Formation high
conductive silicide phase
(2) Key technology
-- Solid state reaction of metal with both C-Si & Poly-Si ° Ti/Si, Co/Si, Pt/Si, Ni/Si
° Elimination of lateral growth
-- No reaction with SiO 2-- Integrity of Poly-Si and S/D junctions
(3) Advantages
-- A self-aligned technology –simultaneous silicidation of S/D region & gate line
-- Significant reduction of R□ & Rc of S/D regions
-- Significant reduction of gate level interconnects
-- Remain excellent PolySi/SiO2/Si interface
-- Good for small geometry & shallow junction devices Improve density, speed and reliability
-- Possibility for developing new technology for VLSI
(4) Silicides for Salicide Technology
z Ti/Si Æ TiSi2
▲Most common used
▲ Low resistivity (C54 phase)
▲ Easy to form
Problem: Difficulty in transformation of C49 Æ C54 for small geometry lines(<0.25µm)
z Co/Si Æ CoSi2
▲ Already application by some companies
▲ As Low resistivity as TiSi2
▲ More chemically stable
▲ Close lattice structure with
Si Æ possible epi. Growth
Problem: Consume more Si than
TiSi2, for the same R□, ~16% more Si
z Ni/Si Æ NiSi
▲L ow resistivity
▲L ow Si consumption
Problem: Low thermal stability;
non-mature
Possible application for CMOS
below 90nm with lower back–end processing T
Intensive R&D of salicide material & technology for nanometer scale CMOS fabrication
(From Dr. K. Han’s report at WIMNCT-2002)。