数字逻辑Chapter 6

D
Yi D mi
A0A1 1-to-4 Demultiplexers 1/2 74x139
G_L A B G A B Y0 Y1 Y2 Y3 Y0_L Y1_L Y2_L Y3_L
Y2 I7 I6 I4 I3
Y1 I7 I6 I3 I2
Y0 I7 I5 I3 I1
2. Priority Encoders
Interrupt System 74×148 EI I0 I1 A2 A1 A0
H7 I7 H6 I6 I7 H5 I5 I6 I7 H4 I4 I5 I6 I7 H3 I3 I4 I5 I6 I7 H2 I2 I3 I4 I5 I6 I7 H1 I1 I2 I3 I4 I5 I6 I7 H0 I0 I1 I2 I3 I4 I5 I6 I7
Output F
Select
F D0 A1 A0 D1 A1 A0 D2 A1A0 D3 A1A0
Y Y_L
F Di mi
i 0
3
Ex.6-5
Input BCD Codes X.
X3 X2 X1 X0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1
Z 2 (Y1_L Y3_L Y7_L ) Z3 (Y2_L Y3_L Y5_L )
Z 4 (Y0_L Y2_L Y4_L Y7_L )
74×138 “1” G1 G2A G2B Y0 Y1 Y2 Y3 C B A A B C Y4
Z4
Z3
Y5 Y6
Y7
Z2
Z1
Output F=1 if X÷3=Integer, else F=0 . 74×151 Truth Table F=X0’ F
1 0 0 1 0 0 1 0 0 1 d
F=X0 F=0
X0
0 1 0 1 0 1
X1 X2 X3
EN A B C D0 D1
Y
Y
F=X0’ F=X0
D2 D3 D4 D5 D6 D7
Y0
Y1 Y2 Y3 Y4 Y5 Y6
Y0_L
Y1_L
Y2_L Y3_L Y4_L Y5_L Y6_L Y7_L
B
C High
EN G1 G2 A G2 B
②Output: Indicating Input Code Word: Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0
Y7
Yi EN mi
For 74×138
Yi_L mi

If
G1 1 G2A 0 G2B 0

Z (Y3_L Y4_L Y5_L Y7_L)
1
Z1 ((m3 m4 m5 m6 )) (m3 m4 m5 m7 ) Z 2 ((m1 m3 m7 )) (m1 m3 m7 ) Z3 ((m2 m3 m5 )) (m2 m3 m5 ) Z4 ((m0 m2 m4 m7 )) (m0 m2 m4 m7 )
A B C D
a b c d e f g
6.3 Encoders
1. 8-3 Encoders Description: ①Input: 1-out-of 8 Codes ②Output: 3bit Binary Codes Don’t Care Term
2n~n
I7 0 0 0 I6 0 0 0 0 0 0 1 0 I5 0 0 0 0 0 1 0 0 I4 0 0 0 0 1 0 0 0
Yi_L (EN mi )
Ex.6-1
4-16 Decoders
Ex.6-2
5-32 Decoders
Ex.6-3 Design Combinational Logic Circuit using 74×138.
Z1 AC ABC ABC Z BC ABC 2 Z 3 AB ABC Z 4 ABC BC ABC
F F_L
1 0 0 0 1 0 0 1 1 0 1 0 … 1 1 1 1
F X0 X3X2X1 X0 X3X2X1 X0 X3X2X1 X0 X3X 2X1
32-to-1 Multiplexer
Demultiplexers Y0 Y1 Y2 Y3
Soln.
Z1 AC( B B) ABC ABC m3 m4 m5 m6 Z 2 BC( A A) ABC m1 m3 m7 Z3 AB(C C) ABC m2 m3 m5 Z 4 ABC BC( A A) ABC m0 m2 m4 m7
1/2 74x139 G_L A B G A B
Y0 Y1 Y2 Y3
Y0_L Y1_L Y2_L Y3_L
1 0
0 0 0
× × 0 0
0 1 1 1 0 1
1 1
1 1 0
1 1
1 0 1
1 1
0 1 1
1 0
1 1 1
1/2 74x139 G A B Y0 Y1 Y2 Y3
74×138 2. 3-8 Decoders 74×138 Enable and Output are Active Low Description: ①Input: 3bit Binary Number: A,B,C Enable Control: G1,G2A,G2B G1 G2A G2B Low A
Y2 EN I1I0 EN m2 Y3 EN I1I0 EN m3
I0 I1 EN
n~2n
Binary Decoders Truth Table
EN I1 I0 0 1 1 1 1 × × 0 0 0 1 1 1 0 1 Y3 Y2 Y1 Y0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
A2 H7 H6 H4 H3 A1 H7 H6 H3 H2 A0 H7 H5 H3 H1
I2
I3 I4 I5 I6 I7 GS EO
IDEL I0 I1 I2 I3 I4 I5 I6 I7
EO: IDEL GS=EO’ IF EI=0
2-4 Decoder
Y3
Y2
Y1 Y0
I0 I1
EN
Y0 Y1 Y2 Y3
Logic Symbol
1/2 74x139
74×139
Dual 2-4 Decoder Enable and Output are Active Low Truth Table
G A B Y3 Y2 Y1 Y0
G
A B
Y0 Y1 Y2 Y3
Low
A4
A3 A2 A1 A0
Ex.6-4 32-5 Encoders
6.4 Three-State Devices Address Bus Data Bus Floppy Hard Disk Disk Driver Driver Display
CDROM

CPU

ROM Keyboard Just one device active at one time! Hi-Z to Low or High is slower than Low or High to Hi-Z. SDRAM Printer
2. Seven-Segment Decoders
a f e 74×48 d g ba b c d e a b c d e
f f
g dp g dp 74×49
74×49
BI
Common-cathode BI: Blanking Input D,C,B,A: BCD Codes Input a,b,c,d,e,f,g: Seven-Segment Codes Output
Binary Encoders Truth Table
I3 0 0 0 1 0 0 0 0 I2 0 0 1 0 0 0 0 0 I1 0 1 0 0 0 0 0 0 I0 Y2 Y1 Y0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1
0 0 0 0 1
Chapter 6
Combinational Logic Design Practices
Preface
6.1 Documentation Standards
1.A Specification ■Define Input and Output ■Exact Description for Function of a Circuit 2.A Block Diagram ■Base Interconnection of a Circuit 3.A Schematic Diagram Don’t modify if have not licence ■The Final and all Details of Description for Interconnection of a Circuit 4.A Timming Diagram ■The Cause-and-effect Delays between Critical Signals 5.A Structured Logic Device Description ■The all Details of Description for CPLD or FPGA etc. 6.A Circuit Description ■The Special Description of a Circuit