UART

Timing Accuracy
• Since the transmitter and receiver keep track of time independently between clock recovery synchronization points, the combined inaccuracy of the transmitter and receiver’s clocks can not be too large. • For RS-232 communication, this combined inaccuracy is about 5%. • Usually, an RC oscillator is too inaccurate and a crystal is required.
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Sending and Receiving
• The PIC UART is full duplex, it can send data and receive data simultaneously. • To send data using the UART simply write the data to the TXREG special function register. • To used data received by the UART read the RCREG special function register.
Bit Time and Baud Rate
• The bit time (units of time) is the time from the start of one serial data bit value to the start of another. • The inverse of the bit time is the baud rate (units of frequency, Hz – however the units are normally omitted). • RS-232 baud rates are integer multiples and sub-multiples of 9600 (Hz).
Voltages
• The UART input/output uses 0V for logic 0 and 5V for logic 1. • The RS-232 standard (and the COM port) use +12V for logic 0 and –12V for logic 1. • To convert between these voltages levels we need an additional integrated circuit (such as Maxim’s MAX232).
UARTs EE 433/533 Embedded and Portable Computing Systems
UART • A Universal Asynchronous ReceiverTransmitter (UART) is used for serial communications – usually via a cable. • The UART generates signals with the same timing as the RS-232 standard used by the Personal Computer’s COM ports.
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UART Interrupts
• The UART can cause an interrupt when a new value is available to read in RCREG: Interrupt flag is RCIF in PIR1 Interrupt enable is RCIE in PIE1 Interrupt priority is RCIP in IPR1
Duration of Bits
• In general, RS-232 bit durations can be: 1) Start bit is always 1 bit time 2) Data bits are each always 1 bit time 3) Parity bit (if present) is always 1 bit time 4) Stop bit may be 1, 1.5, or 2 bit times in duration
UART Interrupts
• The UART can cause an interrupt when a data value is transferred from TXREG to TSR (the point at which it is safe to write a new value to TXREG): Interrupt flag is TXIF in PIR1 Interrupt enable is TXIE in PIE1 Interrupt priority is TXIP in IPR1
Sampling Points
• The synchronization point is at the start of the frame (always a 1 to 0 transition). • The 8 received data values are sampled 1.5BT, 2.5BT, … , 8.5BT after the synchronization point (BT = bit time). • The stop bit is sampled 9.5BT after the synchronization point (if it is not a logic 1, this is a framing error).
Send Data Buffering
• If a new send data item has been written to TXREG, it is automatically copied to TSR and sent whenever the TSR becomes empty. • A new TXREG value can be written while the TSR value is still being sent. • Writing an additional value to TXREG while both TSR and TXREG are occupied will cause the TXREG value to be lost.
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Parts Hale Waihona Puke f an RS-232 Frame
• A frame transmits a single character and is in general composed of: 1) A start bit (always logic 0) 2) Data bits (5, 6, 7, or 8 of them) 3) A parity bit (optional, even or odd parity) 4) A stop bit (always logic 1)
Synchronization Point
• RS-232 idles at a logic 1. • A frame always starts with either an idle-to-startbit or a stop-bit-to-start-bit transition. • Either way, the frame always starts with a logic 1 to logic 0 transition. • The UART looks for 1→0 for the start of the first frame and then looks for 1→0 after 9.5BT for the start of each subsequent frame.
Data Buffering
• The UART has buffer registers which are not visible to the user. • The send portion has a single buffer register called the transmit shift register (TSR). • The receive portion has two buffer registers, one called the receive shift register (RSR) and another than has no name.
UART pins
• The UART always transmits data on pin RC6/TX • The UART always receives data on pin RC7/RX • The RS-232 standard defines lots of other signals other than TX and RX used for handshaking. Non of these other signals is supported.
Receive Data Buffering
• When at least one received data value is unread, it will always be available in the RCREG. • An additional two unread data values can exist without losing data (stored in the unnamed and RSR registers). • If any portion of a fourth data value arrives with three unread values, then data will be lost.