SignalTap II的使用

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ELA Resource Utilization
ELA uses device resources for implementation
ALMs/LEs for ELA megafunction & routing Memory for sample storage
Quartus II Software Design Series : Verification
Debugging Tools – SignalTap II Embedded Logic Analyzer
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SignalTap II ELA
Captures the logic state of FPGA internal signals using a defined clock signal Gives designers ability to monitor buried signals Connects to Quartus II software through FPGA JTAG pins Captures real-time data
SignalTap II ELA Agenda
SignalTap II overview & features Using SignalTap II interface Additional SignalTap II features
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When to Use SignalTap II ELA
No external equipment available Design targets FPGA Additional device resources available for analyzer Faster data acquisition speeds JTAG connection available Performing functional debug
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Feature Overview
Feature
Multiple SignalTap II cores Incremental compilation Support Up to 1024 data channels/128K samples per channel Up to 10 trigger levels External Triggers Basic & advanced trigger support Store data in multiple output file formats
Using STP File
1. Create .STP file
• • • • • Assign sample clock Specify sample depth Assign signals to STP file Specify triggering Setup JTAG
2. Save .STP file & compile with design 3. Program device 4. Acquire data
2) Use MegaWizard® Plug-In Manager
Instantiate directly into HDL ELA tied directly to signals in RTL See Appendix for more details
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How Does It Work?
1. Configure ELA 2. Download ELA into FPGA along with design 3. ELA samples internal signals 4. Quartus II software communicates with ELA through JTAG
Set number of samples stored for each data signal 0 to 128K sample depth
Select RAM type for Stratix® series FPGAs
Useful when preserving specific memory type is necessary
Instance Manager JTAG Chain Configuration
Waveform Viewer
Signal Configuration
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Instance Manager
Instance manager
Selects current ELA to setup/view Displays the current status of each instance Displays size (resource usage) of ELA
Allows user to watch for many successive events Enables interfacing logic analyzer with other devices and logic analyzers Enables simple (boolean AND) triggers or ones based on more complicated boolean and sequential expressions Allows sampled data to be used for simulation, data analysis or documentation
Select new (file menu) Other files SignalTap II file
Default file name will be STP1.Stp
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Main .STP File Components
.STP File
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Benefit
Supports multiple clock domains or functional blocks in single device Allows user to add/edit logic analyzer without affecting existing design placement & routing Allows user to view large sample of data
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Signal Configuration
Manages data capture & signal configuration
Sample clock Sample depth Trigger position Trigger-in & trigger-out
Circular Buffer
1. Data is circled through acquisition buffer until trigger event occurs 2. After trigger event occurs, post-trigger data is collected until buffer fills up
1) Use SignalTap II file (.STP)
Use Quartus II GUI Configure STP details manually STP separate from design files Connect ELA to signals in any level of hierarchy
LE count is a function of the number of channels & trigger levels Memory block count is a function of number of channels & sample depth
Selectable trade-off between depth & number of channels 128K sample depth with 1024 channels not practical – 32,768 M4K blocks
Example: 4K is segmented into 4-1K segments
1. Data is circled through acquisition buffer until trigger event occurs 2. When trigger event occurs, post-trigger data is collected until segment fills up 3. Process repeats until all segments are filled
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Example: Circular Buffer
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Segmented Buffer
Segment 1
Trigger Event
Segment 2
Segment 3
Acquisition buffer is segmented into smaller, user defined blocks
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Assign Sample Clock
Use global clock for best results Data written to memory on every sample clock rising edge Clock signal cannot be monitored as data External clock pin created automatically if clock unassigned
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Data Capgger position
Pre Center Post Continuous
Segmented
Specify segment depth
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SignalTap II Agenda
SignalTap II overview & features Using SignalTap II interface Additional SignalTap II features
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SignalTap II Design Flow
auto_stp_external_clock ELA expects external signal to be connected to clock pin
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Specify Sample Depth & RAM Type
Sample depth
Up to 270 MHz
Is available for free
Installed with full subscription or web edition Installed with stand-alone programmer
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1) Creating A New .STP File
To create a .STP file
Method 1
Tools menu SignalTap II Embedded Logic Analyzer
Method 2