单片机AT89C2051中英文说明书
基于89C51单片机的中英翻译
（AT89C51中英文翻译对照）Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1. IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these criticalapplications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix meansback annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides postsilicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -lator disabling all other chip functions until the next hardware reset.Pin ConfigurationsBlock DiagramPin DescriptionVCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins the y are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/sou -rce four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped duri -ng each access to external DataMemory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationNote: C1, C2 = 30 pF 10 pF for Crystals= 40 pF 10 pF for Ceramic ResonatorsPower-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokespower-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, andthe next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Flash Programming ModesFigure 3. Programming the Flash Figure 4. Verifying the FlashFlash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V) Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V)Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.Flash Programming and Verification CharacteristicsTA = 0°C to 70°C, VCC = 5.0 10%Note: 1. Only used in 12-volt programming mode.Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°CStorage Temperature ..................................... -65°C to +150°CVoltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6VDC Output Current...................................................... 15.0 mADC CharacteristicsTA = -40°C to 85°C, VCC = 5.0V 20% (unless otherwise noted)AC CharacteristicsUnder operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.External Program and Data Memory CharacteristicsExternal Program Memory Read CycleExternal Data Memory Read CycleExternal Data Memory Write CycleExternal Clock Drive WaveformsSerial Port Timing: Shift Register Mode Test Conditions (VCC = 5.0 V 20%; Load Capacitance = 80 pF)Shift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1) Float Waveforms(1)A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps.An analog-to-digital converter(ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself.Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for adigital-to-analog converter(DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amp lified) to a form suitable for operating an actuator.The signals used within microcomputer circuits are almost always too small to be connected directly to the “outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator.To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. T hese hardware devices, called peripherals, are the CPU’s window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions.Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。
关于AT89C51单片机的中英翻译
The Introduction of AT 89C51 DescriptionMicrocontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system tocontinue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin Description·VCC: Supply voltage.·GND: Ground.·Port 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification.·Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 1 also receives the low-order address bytes during Flash programming and verification.·Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory andduring accesses to external data memory that uses 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.·Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups.Port 3 also serves the functions of various special features of the AT89C51 as listed below。
AT89C2051简明资料
AT89C2051简明资料片内ROM------RAM------I／O口线-------中断源-------定时/计数器(个)2k(Flash)------128-----------15--------------5------------------2片内ROM寿命为1000次擦写周期，数据保存期达10年，宽电压工作范为2.7V－6V；全静态工作方式：0Hz－24MHz；两级程序存储器锁定位；128×8位片内RAM；15个可编程I／O口线；两个16位的定时/计数器；5个中断源；可编程串行通道；直接LED驱动输出；片内模拟量比较器；低功耗闲置与掉电保护模式。
信号引脚功能AT89C2051是一种20引脚的双列直插式IC芯片，引脚是单片机的硬件外特性，用户通过引脚连接外部器件就能组建单片机系统。
(1) P1口：它是8位双向口线，即P1.0－P1.7。
口引脚P1.0(12脚)和1.1(13脚)用于外部接口工作时，要求配置外部的上拉电阻；P1.2－P1.7内部设有上拉电阻，用于外部接口工作时由外部负载工作方式决定上否配置上拉电阻。
P1口带有输出缓冲器，可吸收20mA的电流并能直接驱动LED显示。
P1口的功能之一是在闪速编程和程序校验期间接收代码数据(即编程的数据输入口)。
(2) P3口：它是带有内部上拉电阻的7位双向口线，即P3.0－P3.5和P3.7。
P3.6因内部功能的需要，它虽是通用的I/O口引脚但不可访问。
P3口的其它特性与P1口相同，此外P3口还具有第二功能。
(3) 复位端RST(1脚)：当1脚加“H”高电平时芯片内部的功能电路复位，此时I/O口引脚复位到“1”电平。
(4) XTAL1(5脚)：振荡器外接晶振，内部时钟发生器输入。
(5) XTAL2(4脚)：振荡器外接晶振、反向放大器输出。
(6) 电源端20脚(+2.7－6V)和10脚(地端)。
引脚的复用功能由上述对AT89C2051引脚介绍可见：P1口和P3口共占15个引脚，外加复位、振荡(时钟)和电源端等已把芯片的引脚全部占完。
51单片机AT89C51 AT89C2051中文资料
51单片机AT89C51/AT89C2051中文资料--------------------------------------------------------------------------------51单片机AT89C51/AT89C2051中文资料AT89C51是一种带4K字节闪烁可编程可擦除只读存储器（FPEROM—Falsh Programmable and Erasable Read Only Memory）的低电压，高性能CMOS8位微处理器，俗称单片机。
AT89C2051是一种带2K字节闪烁可编程可擦除只读存储器的单片机。
单片机的可擦除只读存储器可以反复擦除100次。
该器件采用ATMEL高密度非易失存储器制造技术制造，与工业标准的MCS-51指令集和输出管脚相兼容。
由于将多功能8位CPU和闪烁存储器组合在单个芯片中，ATMEL的A T89C51是一种高效微控制器，AT89C2051是它的一种精简版本。
AT89C单片机为很多嵌入式控制系统提供了一种灵活性高且价廉的方案。
1．主要特性：·与MCS-51 兼容·4K字节可编程闪烁存储器寿命：1000写/擦循环数据保留时间：10年·全静态工作：0Hz-24Hz·三级程序存储器锁定·128*8位内部RAM·32可编程I/O线·两个16位定时器/计数器·5个中断源·可编程串行通道·低功耗的闲置和掉电模式·片内振荡器和时钟电路2．管脚说明：VCC：供电电压。
GND：接地。
P0口：P0口为一个8位漏级开路双向I/O口，每脚可吸收8TTL门电流。
当P1口的管脚第一次写1时，被定义为高阻输入。
P0能够用于外部程序数据存储器，它可以被定义为数据/地址的第八位。
在FIASH编程时，P0 口作为原码输入口，当FIASH进行校验时，P0输出原码，此时P0外部必须被拉高。
AT89C2051中文资料
AT89C2051中文资料特性：·与MCS－51产品兼容·2K字节可重编程闪存－耐久性：1000次读/写周期·工作电压2.7V至V·全静态运行：0Hz至24MHz·两级程序锁存·128×8位内部RAM·15个可编程I/O口·两个16位定时器/计数器·六个中断源·可编程串行UART（= Universal Asynchronous Receiver Transmitter通用异步收发器）通道·可直接驱动LED的输出·芯片级模仿比较器·低功耗空闲模式和微功耗模式（Power-down mode）说明A T89C2051是一种低电压、高性能的8位CMOS微型计算机。
带2K字节的闪存和可擦可编程只读存储器（EPROM）。
该器件应用爱特美尔（Atmel）的高密度非易失性技术生产，与工业级MCS51架构组相兼容。
将一片通用的8位CPU与闪存集成在单块芯片上，爱特美尔A T89C2051是一种功能强盛的微型计算机。
它为许多嵌入式控制提供了高灵活性低成本的解决方案。
A T89C2051的标准特性如下：2K字节闪存，128字节RAM，15个I/O口，两个16位定时器/计数器，一个五失量两级中断结构，一个全双工串行通信口，一个精准模拟比较器，芯片级振荡器和时钟电路。
另外，A T89C2051用静态逻辑设计，可在低至零频下工作，支持两种软件可选节能模式。
空闲模式下CPU不工作，而RAM，定时器/计数器，串口和中断系统继承工作。
微功耗模式（power-down mode)下保存RAM的内容，但冻结振荡器，禁止其它所有的芯片功能直到下一个硬件复位到来。
特定指令的限制A T89C2051是爱特美尔微控制器家族中经济划算的一款产品。
它包含2K字节的闪速程度存储器。
它与MCS-51架构完全兼容，并且可以使用MCS-51指令组来编程。
AT89C2051管脚图引脚图中文资料
AT89C2051管脚图引脚图中文资料98c2051外部引脚图：（可以直接拷入ASM程序文件中，作注释使用，十分方便）┏━┓┏━┓RET┫1 ┗┛20┣ VccRXD P3.0 ┫2 19┣ P1.7TXD P3.1 ┫3 18┣ P1.6-INT0 P3.2 ┫6 17┣ P1.5-INT1 P3.3 ┫7 16┣ P1.4T0 P3.4 ┫8 15┣ P1.3T1 P3.5 ┫9 14┣P1.2P3.7 ┫11 13┣P1.1 A1(+)X1┫4 12┣ P1.0 A0(-)X2┫5 10┣ GND┗━━━━┛——————————————————————————————————————【引脚电器性能】AT89C2051单片机的P口特点：P1口：P1口是一个8位双向I/O端口，其中P1.2～P1.7引脚带有内部上拉电阻，P1.0和P1.1要求外部上拉电阻。
P1.0和P1.1还分别作为片内精密模拟比较器的同相输入(AIN0)和反相输入(AIN1)。
P1口输出缓冲器可吸收20mA电流，并能直接驱动LED显示。
对端口写1时，通过内部的上拉电阻把端口拉到高电位，这时可作输入口。
P2口作输入口使用时，因为内部有上拉电阻，那些被外部信号拉低的引脚会输出一个电流（Iil）。
P3口：P3.0～P3.5、P3.7是带有内部上拉电阻的7个双向I/O端口。
P3.6用于固定输入片内比较器的输出信号并且它作为一通用I/O口引脚而只读。
P3口输出缓冲器可吸收20mA电流。
对端口写1时，通过内部的上拉电阻把端口拉到高电位，这时可作输入口。
P3口作输入口使用时，因为内部有上拉电阻，那些被外部信号拉低的引脚会输出一个电流（Iil）。
AT89C51单片机的P口特点：P0口：是一个8位漏极开路输出型双向I/O端口。
作为输出端口时，每位能以吸收电流的方式驱动8 个TTL输入，对端口写1时，又可作高阻抗输入端用。
在访问外部程序或数据存储器时，它是时分多路转换的地址（低8位）/数据总线，在访问期间将激活内部的上拉电阻。
AT89C52英文图文说明书
t a o68PLCC.0(T 2)C .1(T 2E X ).0(AD 0).2(R X D )P .3(A D 3).2(A D 2).3.1(A D 1)(I N T 0)P (T X D )P (T 1)P ()P (T 0)P (((R I N D E X C O R N E .4P P P Features•Compatible with MCS-51™ Products•8K Bytes of In-System Reprogrammable Flash Memory –Endurance: 1,000 Write/Erase Cycles •Fully Static Operation: 0 Hz to 24 MHz •Three-Level Program Memory Lock •256 x 8-Bit Internal RAM •32 Programmable I/O Lines •Three 16-Bit Timer/Counters •Eight Interrupt Sources•Programmable Serial Channel•Low Power Idle and Power Down ModesDescriptionThe AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.PDIP(T 2)P 1.0V C C(T 2E X )P 1.1P 0.0(A D 0)P 1.2(I N T 0)P 3.2A L E /(R D )P 3.7P 2.3(A 11)(T X D )P 3.1E A /V P P (W R )P 3.6P 2.4(A 12)(R X D )P 3.0P 0.7(A D 7)(T 1)P 3.5P 2.6(A 14)R S TP 0.6(A D 6)P 0.5(A D 5)P 0.4(A D 4)P 0.3(A D 3)P 0.2(A D 2)P 1.3P 0.1(A D 1)(I N T 1)P 3.3X TA L 2P 2.2(A 10)(T 0)P 3.4P 2.7(A 15)X TA L 1P 2.1(A 9)G N DP 2.0(A 8)P 2.5(A 13)P 1.4P 1.5P 1.6P 1.7Pin ConfigurationsPQFP/TQFPI N D E X .0(T 2)C .1(T 2E X ).2.3.0(AD 0).3(A D 3).2(A D 2).1(A D 1)(((4(continued)Block Diagramt a o c h i p.c nAT89C52The AT89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock cir-cuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.Pin DescriptionV CCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external pro-gram and data memory. In this mode, P0 has internal pul-lups.Port 0 also receives the code bytes during Flash program-ming and outputs the code bytes during program verifica-tion. External pullups are required during program verifica-tion.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal pullups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pul-lups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table.Port 3 also receives some control signals for Flash pro-gramming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable is an output pulse for latching the low byte of the address during accesses to external mem-Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external tim-ing or clocking purposes. Note, however, that one ALEPort Pin Alternate FunctionsP1.0T2 (external count input to Timer/Counter2),clock-outP1.1T2EX (Timer/Counter 2 capture/reload triggerand direction control)Port Pin Alternate FunctionsP3.0RXD (serial input port)P3.1TXD (serial output port)P3.2INT0 (external interrupt 0)P3.3INT1 (external interrupt 1)P3.4T0 (timer 0 external input)P3.5T1 (timer 1 external input)P3.6WR (external data memory write strobe) P3.7RD (external data memory read strobe)t a o c h i p.c nt a o c h i p .c npulse is skipped during each access to external data mem-ory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only dur-ing a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.Program Store Enable is the read strobe to external pro-gram memory.When the AT89C52 is executing code from external pro-gram memory, PSEN is activated twice each machine each access to external data memory.EA/V PPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external pro-gram memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.CC for internal program execu-tions.This pin also receives the 12-volt programming enable volt-age (V PP ) during Flash programming when 12-volt pro-gramming is selected.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Table 1. AT89C52 SFR Map and Reset Values0F8H 0FFH 0F0H B 000000000F7H 0E8H 0EFH 0E0H ACC 000000000E7H 0D8H 0DFH 0D0H PSW 000000000D7H 0C8H T2CON 00000000T2MOD XXXXXX00RCAP2L 00000000RCAP2H 00000000TL200000000TH2000000000CFH 0C0H 0C7H 0B8H IP XX0000000BFH 0B0H P3111111110B7H 0A8H IE 0X0000000AFH 0A0H P2111111110A7H 98H SCON 00000000SBUF XXXXXXXX9FH 90H P11111111197H 88H TCON 00000000TMOD 00000000TL000000000TL100000000TH000000000TH1000000008FH 80HP011111111SP 00000111DPL 00000000DPH 00000000PCON 0XXX000087HAT89C52Special Function RegistersA map of the on-chip memory area called the Special Func-tion Register (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoc-cupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indetermi-nate effect.User software should not write 1s to these unlisted loca-tions, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table4) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.Table 2. T2CON—Timer/Counter 2 Control RegisterData MemoryThe AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are avail-able as stack space.T2CON Address = 0C8H Reset Value = 0000 0000BBit AddressableBit TF2EXF2RCLK TCLK EXEN2TR2C/T2CP/RL2 76543210Symbol FunctionTF2Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1.EXF2Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 =1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.TCLK T ransmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.EXEN2Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.TR2Start/Stop control for Timer 2. TR2 = 1 starts the timer.C/T2Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).CP/RL2Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2= 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.t a o c h i p.c nTimer 0 and 1Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscil-lator periods, the count rate is 1/12 of the oscillator fre-quency.Table 3. Timer 2 Operating ModesIn the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transi-tion, the maximum count rate is 1/24 of the oscillator fre-quency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the cur-rent value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illus-trated in Figure 1.Auto-Reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer2 can count up or down, depending on the value of the T2EX pin.RCLK +TCLK CP/RL2TR2MODE00116-Bit Auto-Reload01116-Bit Capture1X1Baud Rate GeneratorX X0(Off)Figure 1. Timer in Capture Modet a o c h i p.c nAT89C52Figure 2 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The over-flow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by soft-ware. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer regis-ters, TH2 and TL2, respectively.A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)Table 4. T2MOD—Timer 2 Mode Control RegisterT2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable——————T2OE DCEN Bit76543210Symbol Function—Not implemented, reserved for futureT2OE Timer 2 Output Enable bit.DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.t a o c h i p.c nFigure 3. Timer 2 Auto Reload Mode (DCEN = 1)(DOWN COUNTING RELOAD VALUE)TOGGLET2EX PINFigure 4. Timer 2 in Baud Rate Generator Modet a o c h i p .c nAT89C52Baud Rate GeneratorTimer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2into its baud rate generator mode, as shown in Figure 4.The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation.The Timer can be configured for either timer or counteroperation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally,as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, itincrements every state time (at 1/2 the oscillator fre-quency). The baud rate formula is given below.where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not gener-ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt.Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.Figure 5. Timer 2 in Clock-Out ModeModes 1 and 3 Baud Rates Timer 2 Overflow Rate16-----------------------------------------------------------=Modes 1 and 3Baud Rate---------------------------------------Oscillator Frequency 3265536RCAP2H RCAP2L (,)–[]×---------------------------------------------------------------------------------------------=t a o c h i p .Programmable Clock OutA 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regu-lar I/O pin, has two alternate functions. It can be pro-grammed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4MHz at a 16 MHz operating frequency.To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)must be set. Bit TR2 (T2CON.2) starts and stops the timer.The clock-out frequency depends on the oscillator fre-quency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2as a baud-rate generator and a clock generator simulta-neously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.UARTThe UART in the AT89C52 operates the same way as the UART in the AT89C51.InterruptsThe AT89C52 has a total of six interrupt vectors: two exter-nal interrupts (INT0 and INT1), three timer interrupts (Tim-ers 0, 1, and 2), and the serial port interrupt. These inter-rupts are all shown in Figure 6.Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.Note that Table 5 shows that bit position IE.6 is unimple-mented. In the AT89C51, bit position IE.5 is also unimple-mented. User software should not write 1s to these bit posi-tions, since they may be used in future AT89 products.Timer 2 interrupt is generated by the logical OR of bits TF2and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,and that bit will have to be cleared in software.The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However,the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.Table 5. Interrupt Enable (IE) RegisterFigure 6. Interrupt SourcesClock-Out Frequency Oscillator Fequency465536RCAP2H RCAP2L (,)–[]×-----------------------------------------------------------------------------------------= (MSB) (LSB)EA—ET2ESET1EX1ET0EX0Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt.Symbol Position FunctionEAIE.7Disables all interrupts. If EA =0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.—IE.6Reserved.ET2IE.5Timer 2 interrupt enable bit.ES IE.4Serial Port interrupt enable bit.ET1IE.3Timer 1 interrupt enable bit.EX1IE.2External interrupt 1 enable bit.ET0IE.1Timer 0 interrupt enable bit.EX0IE.0External interrupt 0 enable bit.User software should never write 1s to unimplemented bits, because they may be used in future A T89 products.AT89C52Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 8. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maxi-mum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the spe-cial functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is termi-nated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to exter-nal memory.Power Down ModeIn the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Regis-ters retain their values until the power down mode is termi-nated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and sta-bilize.Figure 7. Oscillator ConnectionsNote: C1, C2 = 30 pF ± 10 pF for Crystals= 40 pF ± 10 pF for Ceramic Resonators Figure 8. External Clock Drive ConfigurationStatus of External Pins During Idle and Power Down ModesXTAL2GNDXTAL1XTAL2 XTAL1 GNDNCEXTERNALOSCILLATORSIGNALMode Program Memory ALE PSEN PORT0PORT1PORT2PORT3 Idle Internal11Data Data Data Data Idle External11Float Data Address Data Power Down Internal00Data Data Data Data Power Down External00Float Data Data Datat a o c h i p.c nProgram Memory Lock BitsThe AT89C52 has three lock bits that can be left unpro-grammed (U) or can be programmed (P) to obtain the addi-tional features listed in the following table.Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow-ered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The at that pin in order for the device to function properly.Programming the FlashThe AT89C52 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (V CC) program enable signal. The low voltage program-ming mode provides a convenient way to program the AT89C52 inside the user’s system, while the high-voltage programming mode is compatible with conventional third-party Flash or EPROM programmers.The AT89C52 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C52 code memory array is programmed byte-by-byte in either programming mode. To program any non-blank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89C52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 9 and 10. To program the AT89C52, take the fol-lowing steps.1.Input the desired memory location on the addresslines.2.Input the appropriate data byte on the data lines.3.Activate the correct combination of control signals.4.Raise EA/V PP to 12V for the high-voltage programmingmode.5.array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps1 through 5, changing the address and data for theentire array or until the end of the object file is reached. Data Polling: The AT89C52 features Data Polling to indi-cate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the com-plement of the written data on PO.7. Once the write cycle has been completed, true data is valid on all outputs, and after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Program Lock BitsLB1LB2LB3Protection Type1U U U No program lock features.2P U U MOVC instructions executedfrom external programmemory are disabled fromfetching code bytes frominternal memory, EA issampled and latched on reset,and further programming ofthe Flash memory is disabled. 3P P U Same as mode 2, but verify isalso disabled.4P P P Same as mode 3, but externalexecution is also disabled.V PP = 12V V PP = 5VT op-Side Mark A T89C52xxxxyywwA T89C52xxxx-5yyww Signature(030H)=1EH(031H)=52H(032H)=FFH(030H)=1EH(031H)=52H(032H)=05Ht a o c h i p.c n。
AT89C2051单片机及其引脚图的详细说明
AT89C2051单片机及其引脚图的详细说明默认分类2011-02-07 11:40:41 阅读529 评论0字号：大中小订阅AT89C2051单片机是51系列单片机的一个成员，是8051单片机的简化版。
内部自带2K字节可编程FLASH存储器的低电压、高性能COMS八位微处理器，与Intel MCS-51系列单片机的指令和输出管脚相兼容。
由于将多功能八位CPU和闪速存储器结合在单个芯片中，因此，AT89C2051构成的单片机系统是具有结构最简单、造价最低廉、效率最高的微控制系统，省去了外部的RAM、ROM和接口器件，减少了硬件开销，节省了成本，提高了系统的性价比。
AT89C2051是一个有20个引脚的芯片，引脚配置如图3所示。
与8051相比，AT89C2051减少了两个对外端口（即P0、P2口），使它最大可能地减少了对外引脚下，因而芯片尺寸有所减小。
AT89C2051芯片的20个引脚功能为：VCC 电源电压。
GND 接地。
RST 复位输入。
当RST变为高电平并保持2个机器周期时，所有I/O引脚复位至“1”。
XTAL1 反向振荡放大器的输入及内部时钟工作电路的输入。
XTAL2 来自反向振荡放大器的输出。
P1口8位双向I/O口。
引脚P1.2～P1.7提供内部上拉，当作为输入并被外部下拉为低电平时，它们将输出电流，这是因内部上拉的缘故。
P1.0和P1.1需要外部上拉，可用作片内精确模拟比较器的正向输入（AIN0）和反向输入（AIN1），P1口输出缓冲器能接收20mA电流，并能直接驱动LED显示器；P1口引脚写入“1”后，可用作输入。
在闪速编程与编程校验期间，P1口也可接收编码数据。
P3口引脚P3.0～P3.5与P3.7为7个带内部上拉的双向I/0引脚。
P3.6在内部已与片内比较器输出相连，不能作为通用I/O引脚访问。
P3口的输出缓冲器能接收20mA的灌电流；P3口写入“1”后，内部上拉，可用输入。
P3口也可用作特殊功能口，其功能见表1。
单片机AT89C2051中文资料
单片机AT89C2051中文资料（1）2007-04-05 09:52AT89C205189C2051是由ATMEL 公司推出的一种小型单片机。
95年出现在中国市场。
其 主要特点为采用Flash 存贮器技术，降低了制造成本，其软件、硬件与 MCS-51 完全兼容，可以很快被中国广大用户接受，其程序的电可擦写特性，使得开发 与试验比较容易。
1引脚89C2051共有20条引脚，详见图1.从图中可见，2051继承了 8031最重要引脚：rill ®tS06H1W>iP1 口共8脚，准双向端口。
P3.0〜P3.6共7脚，准双向端口，并且保留了全部的 P3的第二功能，如P3.0、 P3..1的串行通讯功能，P3.2、P3..3的中断输入功能，P3.4、P3.5的定时器输入功 能。
在引脚的驱动能力上面，89C2051具有很强的下拉能力，P1,P3 口的下拉能力均 可达到20mA.相比之下，89C51/87C51的端口下拉能力每脚最大为 15mA 。
但是 限定9脚电流之和小于71mA.这样，引脚的平均电流只 9mA 。
89C2051驱动能 力的增强，使得它可以直接驱动 LED 数码管。
为了增加对模拟量的输入功能，2051在内部构造了一个模拟信号比较器，其输 入端连到P1.0和P1.1 口，比较结果存入 P3.6对应寄存器，（P3.6在2051外部 无引脚），原理见图2。
对于一些不大复杂的控制电路我们就可以增加少量元件来实现，例如，对温度 的控制，过压的控制等。
图3为测量示意图。
其中，R 用于测量门限的调节，IN 端接输入模拟信号。
2电源89C2051有很宽的工作电源电压，可为2.7〜6V,当工作在3V 时，电流相当于6V 工作时的1/4。
89C2051工作于12Hz 时，动态电流为 5.5mA ，空闲态为1mA, 掉电态仅为20nA 。
这样小的功耗很适合于电池供电的小型控制系统。
3存储器89C2051片内含有2k 字节的Flash 程序存储器，128字节的片内RAM,与80C31 内部完全类似。
单片机89C52中英文对照翻译(经典版)
AT89C52 internal structure analysis DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8Kbytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash ona monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operationdown to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, andinterrupt system to continue functioning. The Power-down mode saves the RAM contentsbut freezes the oscillator, disabling all other chip functions until the next interruptor hardware reset.Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port, eachpin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification.External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, asshown in the following table.Port 1 also receives the low-order address bytes duringFlash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetchesfrom external program memory and during accesses toexternal data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is in external execution mode.PSENProgram Store Enable (PSEN) is the read strobe to externalprogram memory.When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000Hup to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate er software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers:Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for each ofthe six interrupt sources in the IP register.Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.Program MemoryIf the EA pin is connected to GND, all program fetches are directed toexternal memory.On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location aboveaddress 7FH, the address mode used in the instructionspecifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space.For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 cont ains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirectaddressing, so the upper 128 bytes of data RAM are availableas stack space.Watchdog Timer(One-time Enabled with Reset-out)The WDT is intended as a recovery method in situationswhere the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive anoutput RESET HIGH pulse at the RST pin.Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow.The 13-bit counter overflows when it reaches 8191(1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior toentering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether theWDT continues tocount if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.UARTThe UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, refer to the ATMEL Web site (). From the home page, select ‘Products’,then ‘8051-Architecture Flash Microcontroller’, then‘Product Overview’.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same wayas Timer 0 and Timer 1 in the AT89C51 and AT89C52. Forfurther information on the timers’ operation, refer to the ATMEL Web site (). From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’, then ‘Product Overview’.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samplesshow a high in one cycle and a low in the next cycle, thecount is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Sin ce two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency.To ensure that a given level is sampled at least once before it changes, the level should be held for at leastone full machine cycle.Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 5.Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.Figure 6 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down,as shown in Figure 6. In thismode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers,TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.译文：89C52的内部结构分析功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。
AT 89C51中英文翻译资料
The Introduction of AT 89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used ashighimpedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current, because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also- 2 -serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each- 3 -machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Out put from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.- 4 -Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function- 5 -Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH)and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage(VCC) program enable signal. The- 6 -low-voltage programming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming theAT89C51, the address, data and control signals should beset up according to the Flash programming mode table. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.- 7 -Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written w ith all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes:The sign ature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 andP3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.- 8 -AT89C51的介绍描述AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。
AT89C51单片机中英文文献翻译
AT89C51的概况1 AT89C51应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。
这些单片机的高速处理速度和增强型外围设备集合使得它们适合于这种高速事件应用场合。
然而，这些关键应用领域也要求这些单片机高度可靠。
健壮的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工具环境保证了高可靠性和低市场风险。
Intel 平台工程部门开发了一种面向对象的用于验证它的AT89C51 汽车单片机多线性测试环境。
这种环境的目标不仅是为AT89C51 汽车单片机提供一种健壮测试环境，而且开发一种能够容易扩展并重复用来验证其他几种将来的单片机。
开发的这种环境连接了AT89C51。
本文讨论了这种测试环境的设计和原理，它的和各种硬件、软件环境部件的交互性，以及如何使用AT89C51。
1.1 介绍8 位AT89C51 CHMOS 工艺单片机被设计用于处理高速计算和快速输入/输出。
MCS51 单片机典型的应用是高速事件控制系统。
商业应用包括调制解调器，电动机控制系统，打印机，影印机，空调控制系统，磁盘驱动器和医疗设备。
汽车工业把MCS51 单片机用于发动机控制系统，悬挂系统和反锁制动系统。
AT89C51 尤其很好适用于得益于它的处理速度和增强型片上外围功能集，诸如：汽车动力控制，车辆动态悬挂，反锁制动和稳定性控制应用。
由于这些决定性应用，市场需要一种可靠的具有低干扰潜伏响应的费用-效能控制器，服务大量时间和事件驱动的在实时应用需要的集成外围的能力，具有在单一程序包中高出平均处理功率的中央处理器。
拥有操作不可预测的设备的经济和法律风险是很高的。
一旦进入市场，尤其任务决定性应用诸如自动驾驶仪或反锁制动系统，错误将是财力上所禁止的。
重新设计的费用可以高达500K 美元，如果产品族享有同样内核或外围设计缺陷的话，费用会更高。
另外，部件的替代品领域是极其昂贵的，因为设备要用来把模块典型地焊接成一个总体的价值比各个部件高几倍。
AT89C51单片机中英文文献翻译
The General Situation of AT89C511 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lockbraking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components are extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Figure 1-2-1 Block Diagram1.3 Pin DescriptionVCC: Supply voltage.GND: Ground.Port 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification.Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN: Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice eachmachine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP: External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. The spinal receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2: Output form the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down Mode:In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRS but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The AT89C51 code memory array is programmed byte by byte in either programming mode. Toprogram any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmsBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 Ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.2.1 Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Figure 2-1-1 Programming the Flash Figure 2-2-2 Verifying the Flash2.2 Chip Erase:The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.2.3 Reading the Signature Bytes:The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows:(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming2.4 Programming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter (ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for digital-to-analog converter (DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amplified) to a form suitable for operating an actuator. The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPU’s window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions. Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.AT89C51的概况1 AT89C51的应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。
中英文翻译 AT89C52 单片机
AT89C2051AT89C2051 Reference Manual AT89C2051 is made in the ATMEL Corporation, which is the low-voltage, high-performance CMOS8-bit microcontroller.Tablets containing repeated 2k bytes of program memory erasable read-only (PEROM) and random 128bytes data memory (RAM), device using ATMEL's high density, non-volatile memory technology, Compatible with the standard of MCS-51 instruction set, built-chip 8-bit general-purpose central processing unit and repeatedly write the Flash memory, which can effectively reduce the development costs. AT89C2051 features a powerful single-chip can provide cost-effective in many Applications.AT89C2051 MCU MCU is a series of 51 members, is the 8051 version of SCM. Internal comes with a programmable EPROM 2 k bytes of high-performance microcontrollers. With the industry standard MCS-51 orders and pin-compatible, so it is a powerful micro-controllers, many embedded control applications, it provides a highly flexible and effective solutions. AT89C2051 has the following characteristics: 2 k bytes EPROM, 128 bytes RAM, 15 I / O lines, two 16 regular / counter, two five vector interrupt structure, a full two-way serial port, and includes Precision analog comparator and on-chip oscillator, a 4.25 V to 5.5 V voltage scope of work and 12 MHz/24MHz frequency, and also offers the encryption array of two program memory locking, power-down and the clock circuit. In addition, AT89C2051 also supports two kinds of software-selectable power-saving mode power supply. During my free time, CPU stop and let RAM, timing / counter, serial port and interrupt system to continue to work. Power-down can preserve the contents of RAM, but will stop oscillator chip-to prohibit all the other functions until the next hardware reset.AT89C2051 have two 16 time / counter register Timer0t Timer1. As a timer, each machine cycle register an increase, such registers to counting machine cycle. Because a machine cycle is 12 oscillator cycles, the count rate is the frequency oscillator 1 / 12. As a counter, the register in the corresponding external input pin P3.4/T0 and P3.5/T1 emerged from the 1-0 when the changes by 1. Two machine cycle because of the need to identify a 1-0 change, the largest count rate is the frequency oscillator 1 / 24, the external input P3.2/INT0 and P3.3/INT1 programming, for Measuring the pulse width of the door.Therefore, AT89C2051 constitute the SCM system is a simple structure, the costof the cheapest, most efficient micro-control system, eliminating the external RAM, ROM and interface devices, reducing hardware costs, cost savings, improved The cost-effective system.Clock circuitMCU clock signal used to provide various micro-chip microcontroller operation of the benchmark time, the clock signal is usually used by the form of two circuits: the internal and external shocks oscillation. MCS-51 has a microcontroller internal oscillator for a reverse of the high-gain amplifier, pin XTALl and XTAL2 are here to enlarge the electrical inputs and outputs, as in-house approach, a simple circuit, from the clock Signal relatively stable, and actually used often in this way, as shown in Figure 3-1 in its external crystal oscillator (crystal) or ceramic resonator constituted an internal oscillation, on-chip high-gain amplifier and a reverse Feedback components of the chip quartz crystal or ceramic resonator together to form a self oscillator and generate oscillation clock pulse. Figure 3-1 in the external crystal and capacitors C1 and C2 constitute a parallel resonant circuits, their stability from the oscillation frequency, rapid start-up role, and its value are about 33 PF, crystal frequency of elections 12 MHz.Reset CircuitIn order to initialize the internal MCU some special function register to be reset by the way, will reset after the CPU and system components identified in the initial state, and from the initial state began work properly. MCU is reset on the circuit to achieve, in the normal operation of circumstances, as long as the RST-pin on a two machine cycle time over the high, can cause system reset, but if sustained for the RST-pin HIGH, in a circle on the MCU reset state. After the system will reset input / output (I / 0) home port register for the FFH, stack pointer SP home for 07 H, SBUF built-in value for the indefinite, all the rest of the register-0, the status of internal RAM from the impact of reduction, On the system, when the contents of RAM is volatile. Reset operation There are two situations in which a power-on reset and manual (switch) reduction. The system uses a power-on reset mode. Figure 3-1 in the R0 and C0 formed a power-on reset circuit, and its value for R for 8.2 K, C for the 10 uF.Main features:Compatible the MCS51 command system;Contains the 2KB memory re-programming FLASH (1000);Picture one the pin of AT89C2051AT89C2051’s functional description:VCC: Power Supply V oltageGND: landP1 port: P1 mouth is a group of 8-bit bi-directional I / O interface, P1.2 ~ P1.7 provide internal pull-up resistor,P1.0 and P1.1 internal supreme pull-up resistor. P1 mouth output buffer can absorb the current 20mA and direct-drive LED.When Programming and calibration, P1 mouth as the eighth address receive.P3 mouth: P3 port P3.0 ~ P3.5, P3.7 is the internal pull-up resistor with the seven bi-directional I / O interface. Did not bring out the P3.6，It as a generic I / O port, but can not visit. Can be used as a fixed-chip input comparator output signal. when P3 write 1, they were highed the internal pull-up resistor can be raised as an input port.P3 port special function as shown in table 1:Table 1 P3 mouth’s special featuresPIN functional characteristics20191817161514131211GND P3.5P3.4P3.3P3.2XTAL1XTAL2P3.1P3.0RST P3.7P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7VCC 12345678910RST：Reset output. When the oscillator device reset, RST pin to maintain the high level of two machine cycle time.XTAL1: the RP-oscillator amplifier and internal clock generator input.XTAL2: RP-oscillator output amplifier.TimerOverview of the Timer89C2051 single-chip-chip has two 16-bit timer / counter, That is the timer 0 (T0) and Timer 1 (T1). They all have from time to time and event count function, Can be used for timing control, delay of external events, such as counting and testing occasions. Timer’s T0 and T1—— two 16-bit timers in fact is 16-bit counter plus 1. Among them, T0 compositioned by the two 8-bit special function registers TH0 and TL0; T1 posed by the TH1 and TL1. These functions were controled by the special function registers TMOD and TCONWhen set to the work in the timing, Through the pin count of the external pulse signal. When the input pulse signal generated by the falling edge of 1-0, The value of timer plus 1. At of every machine cycle during the S5P2 sampling pin T0 and T1 the input level, if a machine cycle before sample value of 1, The next machine cycle sampling value is 0, The counter plus 1. Since then during S3P1 of the machine cycle, New value will into the counter.so Detection of a 1-0 transition of the two machine cycles,So The maximum count frequency of oscillation frequency of 1 / 24. In addition to the option of work from time to time or count,Each timer / counter have four kinds of work mode, That is, each of timer circuit kinds of four constitute a structural modelTwo low-power modeIdle modeIn idle mode, CPU to maintain sleep and all-chip peripherals remain active, this way generated in Software, At this point, Chip RAM and all the contents of special function registers remain unchanged. Idle mode was terminated by any interrupt request permission to or hardware reset.P1.0 and P1.1 ,in the non-use of external pull-up resistor on the case should be set to "0", Or in the use of pull-up resistor is set to "1."It should be noted that: when uses of hardware reset Termination idle mode, AT89C2051 is usually stopped from the program until the internal reset control of the two machine cycles before the restore procedure Service. In this case the hardware within the prohibition of the reading and writing of internal RAM, However, to allow access to ports, To eliminate the Hardware reset in the idle mode of port accidents may write, In principle, to enter the idle mode of instruction should not be under the command of a pin or an external memory port for a visit.Power-down modeIn power-down mode, the oscillator to stop working, enter the power-down mode ,Instructions, who was the last one, the implementation of the Directive, Chip RAM and all the contents of special function registers the termination of the previous power-down mode be frozen. To withdraw from power-down mode is the only way to reset the hardware, Reset will redefine all the Special Function Registers but Does not change the contents of RAM before the the Vcc work returned to normal levels Shall be null and void and must be reset to maintain a certain period of time in order to restart and oscillator stabilityP1.0 and P1.1 in the non-use of external pull-up resistor on the case should be set to "0", Or in the use of pull-up resistor is set to "1."OscillatorOscillator connected clientXTAL1: RP-oscillator amplifier and internal clock generator inputXTAL2: RP-oscillator amplifier outputCharacteristics of OscillatorXTAL1, XTAL2 ware the RP-chip oscillator amplifier inputs and outputs, Quartzcrystal can be composed of the clock oscillator or ceramic oscillator, For more information from the external input clock driver AT89C2051, XTAL1 input clock signal from, XTAL2 should be left vacant.As the input to the internal circuit is a 2-flip-flop, Therefore, the external clock signal input without special requirements, However, it must comply with the maximum level and minimum norms and timing中文翻译：AT89C2051AT89C2051数据参考手册AT89C2051是美国ATMEL公司生产的低电压、高性能CMOS8位单片机，片内含2k bytes的可反复擦写的只读程序存储器（PEROM）和128bytes的随机数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51指令系统，片内置通用8位中央处理器和可反复擦写的Flash存储器，可有效地降低开发成本。
单片机AT89C2051中英文说明书
AT89C2051主要性能参数：与MCS-51产品指令系统完全兼容1．2k字节可重擦写闪速存储器2.1000次擦写周期3.2.7—6V的工作电压范围4.全静态操作：OHz—24MHz5.两级加密程序存储器6.128x8字节内部RAM7.15个可编程I/O口线8.两个16位定时/计数器9.6个中断源10.可编程串行UART通道11.可直接驱动LED的输出端口12.内置一个模拟比较器13.低功耗空闲和掉电模式功能特性概述A T89C2051提供以下标准的功能：2k字节Flash闪速存储器，128字节内部RAM,15个I/O 口线，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，内置一个精密比较器，片内振荡器及时钟电路。
同时，AT89C2051可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。
空闲方式停止CPU的工作，但振荡器停止工作并禁止其他所有部件工作直到下一个硬件复位。
方框图引脚功能说明：Vcc:电源电压GND: 地P1口：p1口是一组8位双向I/O口，P1.2~P1.7提供内部上拉电阻，P1.0和p1.1内部无上拉电阻，主要考虑他们分别是内部精密比较器的相同输入器（AINO）和反相输入端（AINI）,如果需要应在外部接上拉电阻。
P1口输入缓冲器可吸收20mA电流并可直接驱动LED当P1口引脚写入“1”时可作输入端，当引脚P1.2~P1.7用作输入并被外部拉低时，他们将因为内部的上拉电阻位输出电流（In）。
P1口还在flash闪速编程及程序校验时接收代码数据。
P3口：P3口的P3.0~P3.5、P3.7是带有内部上拉电阻的7个双向I/O口。
P3.6没有引出，它作为一个通用的I/O口淡并不可以访问，但可以作为固定输入片内比较器的输出信号，P3.口缓冲器可吸收20mA电流。
当P3口写入“1”时，他们被内部上拉电阻拉高并可作为输入端口。
作为输入端是，被外部拉低的P3口将用上拉电阻输出电流（In）。
at89c52单片机中英文资料对照外文翻译文献综述
at89c52单片机简介中英文资料对照外文翻译文献综述A T89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。
Storage RAM immediately﹑memoy read ROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。
Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。
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AT89C2051
主要性能参数：
与MCS-51产品指令系统完全兼容
1．2k字节可重擦写闪速存储器
次擦写周期
3.2.7—6V的工作电压范围
4.全静态操作：OHz—24MHz
5.两级加密程序存储器
字节内部RAM
个可编程I/O口线
8.两个16位定时/计数器
个中断源
10.可编程串行UART通道
11.可直接驱动LED的输出端口
12.内置一个模拟比较器
13.低功耗空闲和掉电模式
功能特性概述
AT89C2051提供以下标准的功能：2k字节Flash闪速存储器，128字节内部RAM,15个I/O 口线，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，内置一个精密比较器，片内振荡器及时钟电路。
同时，AT89C2051可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。
空闲方式停止CPU的工作，但振荡器停止工作并禁止其他所有部件工作直到下一个硬件复位。
方框图
引脚功能说明：
Vcc:电源电压
GND: 地
P1口：p1口是一组8位双向I/O口，~提供内部上拉电阻，和内部无上拉电阻，主要考虑他们分别是内部精密比较器的相同输入器（AINO）和反相输入端（AINI）,如果需要应在外部接上拉电阻。
P1口输入缓冲器可吸收20mA电流并可直接驱动LED当P1口引脚写入“1”时可作输入端，当引脚~用作输入并被外部拉低时，他们将因为内部的上拉电阻位输出电流（In）。
P1口还在flash闪速编程及程序校验时接收代码数据。
P3口：P3口的~、是带有内部上拉电阻的7个双向I/O口。
没有引出，它作为一个通用的I/O口淡并不可以访问，但可以作为固定输入片内比较器的输出信号，P3.口缓冲器可吸收20mA电流。
当P3口写入“1”时，他们被内部上拉电阻拉高并可作为输入端口。
作为输入端是，被外部拉低的P3口将用上拉电阻输出电流（In）。
P3口还用于实现AT89C2051特殊的功，如下表所示：
P3口还接收一些用于flash闪速编程及程序校验的控制信号。
RST:复位输入。
RST引脚一旦变成两个机器周期以上高电平，所有的I/O 口都将复制到“1”（高电平）状态，振荡器正在工作时，持续两个机器周期以上的高电平便可以王城复位，没个机器周期为12个振荡时钟周期。
XTAL1：振荡器反相放大器的内部时钟发生器的输入端。
XTA12：振荡器反相放大器的输出端。
振荡器的特征：
XTAL1、XTAL2为片内振荡器的反相放大器的输入或输出端，如下图所示。
可采用石英晶体或陶瓷振荡器振荡器组成时钟振荡器，如需从外部输入时钟驱动AT89C2051，时钟信号从XTAL1、XTAL2应悬空。
由于输入到内部电路是经过一个2分频触发器，所有输入的外部时钟信号无需特殊要求，但它必须符合电平的最大和最小值及时时序规范。
某些指令的约束条件：
A89C2051是经济型低价位的微控制器，它含有2k字节的flash闪速程序存储器，指令系统与MCS—51完全兼容，可使用MCS—51指令系统对其进行编程。
但是在使用某些有关指令进行编程时程序员须注意一些事项。
和跳转或分支有关的指令有一定的空间约束，使目的地址能安全落在A89C2051的2k 字节的物理程序存储器空间内，程序员必须注意这一点。
对于2K字节存储器的A89C2051来说，LJMP E0H是一条有效指令，而LJMP 900H则无效指令。
1.分支指令
对于LCALL、LJMP、ACALL、AJMP、JMP、MP@+DPTR等指令，只要程序员记住这些分支指令的目的地址在程序存储器大小的物理范围内，这些无条件分支指令就会正确执行，超出物理空间的限制会出现不可预知的程序出错。
JZ、NZ、CJB等这些条件转移指令的使用与上述原则一样。
2 . 与MOVX相关的指令，数据存储器
A89C2051包含128字节内部数据存储器，这样，A89C2051的堆深度局限于内部RAM 的128字节范围内，它既不支持外部数据存储器的访问，也不支持外部程序存储器的执行，因此程序中不应有MOVX指令。
程序存储器的加密：
A89C2051可使用对芯片上的两个加密位进行编程或不编程得到下表所示功能：
空闲模式：
在空闲模式下，CPU保持睡眠状态而所有片内的外设保持激活状态，这种方式有软件产生。
此时RAM和所有特殊功能寄存器的内容保持不变。
掉电模式：
在掉电模式下，振荡器停止工作，进入点点模式的指令时最后一条指令。
Flash闪速存储器的编程：
在擦出状态下用2k字节的片内PEROM带码存储进行封装微控制器，其程序存储器是可反复编程的。
数据查询：
AT89C2051具有写周期节航速的数据查询功能，在写周期期间，对最后写入的字节尝试读将令上写入数据的炒作结束。
当写周期完成，全部输出端的数据有效。
编程接口：
Flash闪速中的每一带码字节进行写入切整个存储器可在控制信号的正确组合下进行擦除。