数电实验(verilog文档)

// 本实验的代码还未提交，但是都进行仿真通过。

不保证老师那边没问题。

// 1、N进制加法计数器异步清零// 这里是24进制，更改下对应的二进制位数和进制就可以了。

module count_24(clk, reset, enable, full, out);input clk, reset, enable;output full;output [4:0] out;reg [4:0] out;always @(posedge clk or posedge reset)beginif(reset)out <= 5'b00000;elsebeginif(enable)beginif(out == 23)out <= 0;elseout <= out + 1;endelseout <= out;endendassign full = (out == 23) ? 1 : 0;endmodule// 2、16位数控分频器只能进行偶数次分频，最小二分频module div_16bits(clk, rst, ctrl, fout); // only even divinput clk, rst;input [15:0] ctrl;output fout;reg fout, full;reg [15:0] data;always @(posedge clk or posedge rst) // 异步清零beginif(rst)data <= {16{1'b0}};elsebeginif(data == {16{1'b1}})begindata <= ctrl;full <= 1'b1;endelsebegindata <= data + 1'b1;full <= 1'b0;endendendalways @(posedge full) // 进行二分频，同时调节占空比为 50% fout = ~fout;endmodule// 3、含并行置位的8位移位寄存器设计module reg_pe8(clk, func, para, ser_in, qout, data);input clk, func, ser_in; // func ：功能选择 1：移位 0：置位input [7:0] para; // 并行输入output qout; // 输出左移位output [7:0] data; // 并行输出reg qout;reg [7:0] data;always @(posedge clk)beginif(~func)begindata <= para;qout <= para[7];endelse{qout, data[7:0]} <= {data[7:0], ser_in};endendmodule// 4、16位定时计数器设计、// 顶层模块module time_count_16(taclk, aclk, smclk, inclk, tasel,divder, ctrl, taclr, ta_ifg, t_clk, count);input taclk, aclk, smclk, inclk; // clk input to select input [1:0] tasel; // 时钟信号选择input taclr;output ta_ifg, t_clk;input [1:0] divder;input [3:0] ctrl;output [3:0] count;reg [4:0] div;wire clk;always @(divder)case(divder)2'd0: div = 1;2'd1: div = 2;2'd2: div = 4;2'd3: div = 8;endcase// 模块例化，差不多相当于函数调用注意：.taclk(taclk) 前面有个点号tasel_4 taclk_sel_ic(taclk, aclk, smclk, inclk, tasel, clk);div_16bits div_clk_ic(clk, taclr, div, t_clk);count_16bits count_clk_ic(t_clk, taclr, ctrl, count, ta_ifg);endmodule// 模块一：时钟选择模块输入四个时钟： TACLK, ACLK, SMCLK, INCLKmodule tasel_4(taclk, aclk, smclk, inclk, tasel, clk_out);input taclk, aclk, smclk, inclk;input [1:0] tasel;output clk_out;reg clk_out;always @(tasel)case(tasel)2'b00: clk_out = taclk;2'b01: clk_out = aclk;2'b10: clk_out = smclk;2'b11: clk_out = inclk;endcaseendmodule// 模块二：分频模块，对上面选择的时钟信号进行分频，可是写的分频器不能进行一分// 频，只能进行偶数次分频，即最小二分频。

module div_16bits(clk, rst, ctrl, fout); // only even divinput clk, rst;input [15:0] ctrl;output fout;reg fout, full;reg [15:0] data;always @(posedge clk or posedge rst) // 异步清零beginif(rst)data <= {16{1'b0}};elsebeginif(data == {16{1'b1}})begindata <= ctrl;full <= 1'b1;endelsebegindata <= data + 1'b1;full <= 1'b0;endendendalways @(posedge full) // 进行二分频，同时调节占空比为 50%fout = ~fout;endmodule// 模块三： 16位计数器（TAR）可进行预置数module count_16bits(clk, reset, data_in, data_out, full); // data_in 预置数input clk, reset;output full;input [3:0] data_in;output [3:0] data_out;reg [3:0] data_out;always @(posedge clk or posedge reset) // 异步清零beginif(reset)data_out <= data_in;elsebeginif(data_out == 4'b1111)data_out <= data_in;elsedata_out <= data_out + 1'b1;endendassign full = (data_out == 4'b1111) ? 1'b1 : 1'b0;endmodule// 5、频率和占空比可调PWM 设计// 顶层模块// clk 时钟信号 ctrl 周期控制字 pwm_ctrl 脉宽控制字// 上届的实验指导书有模块结构图，对照着看就明白了。

module pwm_ctrl(clk, ctrl, pwm_ctrl, out);input clk;input [7:0] ctrl, pwm_ctrl;output out;wire fout;wire [7:0] counter;// 同上例进行模块例化div_8 div_8_ic(clk, ctrl, fout);counter_8 counter_8_ic(fout, counter);comp_8 comp_8_ic(counter, pwm_ctrl, out); endmodule// 模块一： 8位数控分频器module div_8(clk, ctrl, fout);input clk;input [7:0] ctrl;output fout;reg fout, out_tmp;reg [7:0] counter;always @(posedge clk)beginif(counter == 8'b1111_1111)begincounter <= ctrl;out_tmp <= 1'b1;endelsebegincounter <= counter + 1'b1;out_tmp <= 1'b0;endendalways @(posedge out_tmp)fout <= ~fout;endmodule// 模块二 8位计数器module counter_8(clk, counter);input clk;output [7:0] counter;reg [7:0] cnt_temp;assign counter = cnt_temp;always @(posedge clk)beginif(cnt_temp == 8'b1111_1111)cnt_temp <= 8'b0000_0000;elsecnt_temp <= cnt_temp + 1'b1;endendmodule// 模块三数值比较器module comp_8(counter, ctrl, pwm_out);input [7:0] counter, ctrl;output pwm_out;assign pwm_out = (counter > ctrl) ? 1'b1 : 1'b0; endmodule。