DM74LS373中文资料

© 2000 Fairchild Semiconductor Corporation DS006431April 1986Revised March 2000DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-FlopsDM74LS373 • DM74LS3743-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-FlopsGeneral DescriptionThese 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or rela-tively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for inter-face or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.The eight latches of the DM74LS373 are transparent D-type latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up.The eight flip-flops of the DM74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-imped-ance state the outputs neither load nor drive the bus lines significantly.The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.Featuress Choice of 8 latches or 8 D-type flip-flops in a single package s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputss P-N-P inputs reduce D-C loading on data linesOrdering Code:Devices also available in T ape and Reel. Specify by appending the suffix letter “X” to the ordering code.Order Number Package NumberPackage DescriptionDM74LS373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74LS374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide IDM29901NCN20A20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 2D M 74L S 373 • D M 74L S 374Connection DiagramsDM74LS373DM74LS374Function TablesDM74LS373DM74LS374H = HIGH Level (Steady State)L = LOW Level (Steady State)X = Don’t CareZ = High Impedance State↑ = Transition from LOW-to-HIGH levelQ 0 = The level of the output before steady-state input conditions were established.Logic DiagramsDM74LS373Transparent LatchesDM74LS374Positive-Edge-Triggered Flip-FlopsOutput Enable D Output ControlG L H H H L H L L L L X Q 0HXXZOutput Clock D Output ControlL ↑H H L ↑L L L L X Q 0HXXZDM74LS373 • DM74LS374Absolute Maximum Ratings (Note 1)Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditions for actual device operation.DM74LS373 Recommended Operating ConditionsNote 2: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.Note 3: T A = 25°C and V CC = 5V.DM74LS373 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)Note 4: All typicals are at V CC = 5V, T A = 25°C.Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.Supply Voltage 7V Input Voltage7VStorage Temperature Range−65°C to +150°COperating Free Air Temperature Range0°C to +70°CSymbol ParameterMin Nom Max Units V CC Supply Voltage4.7555.25V V IH HIGH Level Input Voltage 2V V IL LOW Level Input Voltage 0.8V I OH HIGH Level Output Current −2.6mA I OL LOW Level Output Current 24mA t W Pulse Width Enable HIGH 15ns (Note 3)Enable LOW15t SU Data Setup Time (Note 2) (Note 3)5↓ns t H Data Hold Time (Note 2) (Note 3)20↓ns T AFree Air Operating Temperature70°CSymbol ParameterConditionsMinTyp Max Units (Note 4)V I Input Clamp Voltage V CC = Min, I I = −18 mA −1.5V V OH HIGH Level V CC = Min, I OH = Max 2.4 3.1VOutput Voltage V IL = Max, V IH = Min V OLLOW Level V CC = Min, I OL = MaxOutput VoltageV IL = Max, V IH = Min 0.350.5VI OL = 12 mA, V CC = Min 0.4I I Input Current @ Max Input Voltage V CC = Max, V I = 7V 0.1mA I IH HIGH Level Input Current V CC = Max, V I = 2.7V 20µA I IL LOW Level Input Current V CC = Max, V I = 0.4V −0.4mA I OZH Off-State Output Current with V CC = Max, V O = 2.7V 20µA HIGH Level Output Voltage Applied V IH = Min, V IL = Max I OZL Off-State Output Current with V CC = Max, V O = 0.4V −20µA LOW Level Output Voltage Applied V IH = Min, V IL = Max I OS Short Circuit Output Current V CC = Max (Note 5)−50−225mA I CCSupply CurrentV CC = Max, OC = 4.5V,2440mA D n , Enable = GND 4D M 74L S 373 • D M 74L S 374DM74LS373 Switching Characteristicsat V CC = 5V and T A = 25°CNote 6: C L = 5 pF.DM74LS374 Recommended Operating ConditionsNote 7: The symbol (↑) indicates the rising edge of the clock pulse is used for reference.Note 8: T A = 25°C and V CC = 5V.R L = 667ΩSymbol ParameterFrom (Input)C L = 45 pF C L = 150 pF UnitsTo (Output)MinMax MinMax t PLH Propagation Delay Time Data to Q 1826ns LOW-to-HIGH Level Output t PHL Propagation Delay Time Data to Q 1827ns HIGH-to-LOW Level Output t PLH Propagation Delay Time Enable to Q 3038ns LOW-to-HIGH Level Output t PHL Propagation Delay Time Enable to Q 3036ns HIGH-to-LOW Level Output t PZH Output Enable Time Output Control to Any Q 2836ns to HIGH Level Output t PZL Output Enable Time Output Control to Any Q 3650ns to LOW Level Output t PHZ Output Disable TimeOutput Control to Any Q 20ns from HIGH Level Output (Note 6)t PLZOutput Disable TimeOutput Control to Any Q25nsfrom LOW Level Output (Note 6)Symbol ParameterMin Nom Max Units V CC Supply Voltage4.7555.25V V IH HIGH Level Input Voltage 2V V IL LOW Level Input Voltage 0.8V I OH HIGH Level Output Current −2.6mA I OL LOW Level Output Current 24mA t W Pulse Width Clock HIGH 15ns (Note 8)Clock LOW15t SU Data Setup Time (Note 7) (Note 8)20↑ns t H Data Hold Time (Note 7) (Note 8)1↑ns T AFree Air Operating Temperature70°CDM74LS373 • DM74LS374DM74LS374 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)Note 9: All typicals are at V CC = 5V, T A = 25°C.Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second.DM74LS374 Switching Characteristicsat V CC = 5V and T A = 25°CNote 11: C L = 5 pF.Symbol ParameterConditionsMinTyp Max Units (Note 9)V I Input Clamp Voltage V CC = Min, I I = −18 mA −1.5V V OH HIGH Level V CC = Min, I OH = Max 2.43.1VOutput Voltage V IL = Max, V IH = Min V OLLOW Level V CC = Min, I OL = Max0.350.5VOutput VoltageV IL = Max, V IH = Min I OL = 12 mA, V CC = Min 0.250.4I I Input Current @ Max Input Voltage V CC = Max, V I = 7V 0.1mA I IH HIGH Level Input Current V CC = Max, V I = 2.7V 20µA I IL LOW Level Input Current V CC = Max, V I = 0.4V −0.4mA I OZH Off-State Output Current with V CC = Max, V O = 2.7V 20µA HIGH Level Output Voltage Applied V IH = Min, V IL = Max I OZL Off-State Output Current with V CC = Max, V O = 0.4V −20µA LOW Level Output Voltage Applied V IH = Min, V IL = Max I OS Short Circuit Output Current V CC = Max (Note 10)−50−225mA I CCSupply CurrentV CC = Max, D n = GND, OC = 4.5V2745mAR L = 667ΩSymbol Parameter C L = 45 pF C L = 150 pF Units Min MaxMin Maxf MAX Maximum Clock Frequency 3520MHz t PLH Propagation Delay Time 2832ns LOW-to-HIGH Level Output t PHL Propagation Delay Time 2838ns HIGH-to-LOW Level Output t PZH Output Enable Time 2844ns to HIGH Level Output t PZL Output Enable Time 2844ns to LOW Level Output t PHZ Output Disable Time20ns from HIGH Level Output (Note 11)t PLZOutput Disable Time25nsfrom LOW Level Output (Note 11) 6D M 74L S 373 • D M 74L S 374Physical Dimensionsinches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 WidePackage Number M20B DM74LS373 • DM74LS374Physical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M20D8D M 74L S 373 • D M 74L S 374 3-S T A TE O c t a l D -T y p e T r a n s p a r e n t L a t c h e s a n d E d g e -T r i g g e r e dF l i p -F l o p sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N20AFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。