杜熬—电子实验报告—跑表

数字跑表实验报告报告人：杜熬学院：资源与环境学院学号：2907201005指导教师：李颖总体设计框图单元电路划分（1）计数器（2）分频器（3）使能控制器（4）扫描显示控制器各单元电路设计计数器程序中可以采用写一个六进制和十进制的计数器，然后采用画图的方法实现总计数器的设计（即采用两个六进制计数器和四个十进制计数器），但是本实验中采用了直接对总的计数器进行总体描述来实现，采用了异步计数的原理（即将一个计数器的进位端口和高位计数器的clk脉冲输入端而不是使能端相连），下面来看程序设计：------------------------------------------------------------------------------------ Company:-- Engineer:---- Create Date: 19:25:11 08/21/2011-- Design Name:-- Module Name: counter6 - Behavioral-- Project Name:-- Target Devices:-- Tool versions:-- Description:---- Dependencies:---- Revision:-- Revision 0.01 - File Created-- Additional Comments:------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity counter isPort ( clk : in STD_LOGIC;clear : in STD_LOGIC;count_en : in STD_LOGIC;counter_1 : out STD_LOGIC_VECTOR (3 downto 0);counter_2 : out STD_LOGIC_VECTOR (3 downto 0);counter_3 : out STD_LOGIC_VECTOR (3 downto 0);counter_4 : out STD_LOGIC_VECTOR (3 downto 0);counter_5 : out STD_LOGIC_VECTOR (3 downto 0);counter_6 : out STD_LOGIC_VECTOR (3 downto 0));end counter;architecture Behavioral of counter issignal count_temp1:std_logic_vector(3 downto 0):="0000"; signal count_temp2:std_logic_vector(3 downto 0):="0000"; signal count_temp3:std_logic_vector(3 downto 0):="0000"; signal count_temp4:std_logic_vector(3 downto 0):="0000"; signal count_temp5:std_logic_vector(3 downto 0):="0000"; signal count_temp6:std_logic_vector(3 downto 0):="0000"; signal carry1:std_logic;signal carry2:std_logic;signal carry3:std_logic;signal carry4:std_logic;signal carry5:std_logic;beginprocess(clk,count_en,clear)beginif(clear='0')thencount_temp1<="0000";else if(count_en='1')thenif clk'event and clk='1' thenif count_temp1="1001" thencount_temp1<="0000";carry1<='1';elsecount_temp1<= count_temp1+1;carry1<='0';end if;else count_temp1<= count_temp1;end if;end if;end if;end process;counter_1<= count_temp1;process(carry1,clear)beginif(clear='0')thencount_temp2<="0000";else if carry1'event and carry1='1' thenif count_temp2="1001" thencount_temp2<="0000";carry2<='1';elsecount_temp2<= count_temp2+1;carry2<='0';end if;else count_temp2<= count_temp2;end if;end if;end process;counter_2<= count_temp2;process(carry2,clear)beginif(clear='0')thencount_temp3<="0000";else if carry2'event and carry2='1' thenif count_temp3="1001" thencount_temp3<="0000";carry3<='1';elsecount_temp3<= count_temp3+1;carry3<='0';end if;else count_temp3<= count_temp3;end if;end if;end process;counter_3<= count_temp3;process(carry3,clear)beginif(clear='0')thencount_temp4<="0000";else if carry3'event and carry3='1' thenif count_temp4="0101" thencount_temp4<="0000";carry4<='1';elsecount_temp4<=count_temp4+1;carry4<='0';end if;else count_temp4<=count_temp4;end if;end if;end process;counter_4<=count_temp4;process(carry4,clear)beginif(clear='0')thencount_temp5<="0000";else if carry4'event and carry4='1'thenif count_temp5="1001" thencount_temp5<="0000";carry5<='1';elsecount_temp5<=count_temp5+1;carry5<='0';end if;else count_temp5<=count_temp5;end if;end if;end process;counter_5<=count_temp5;process(carry5,clear)beginif(clear='0')thencount_temp6<="0000";else if carry5'event and carry5='1' thenif count_temp6="0101" thencount_temp6<="0000";elsecount_temp6<=count_temp6+1;end if;else count_temp6<=count_temp6;end if;end if;end process;counter_6<=count_temp6;end Behavioral;仿真文件：LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;ENTITY counter_test_vhd ISEND counter_test_vhd;ARCHITECTURE behavior OF counter_test_vhd IS-- Component Declaration for the Unit Under Test (UUT) COMPONENT counterPORT(clk : IN std_logic;clear : IN std_logic;count_en : IN std_logic;counter_1 : OUT std_logic_vector(3 downto 0);counter_2 : OUT std_logic_vector(3 downto 0);counter_3 : OUT std_logic_vector(3 downto 0);counter_4 : OUT std_logic_vector(3 downto 0);counter_5 : OUT std_logic_vector(3 downto 0);counter_6 : OUT std_logic_vector(3 downto 0));END COMPONENT;--InputsSIGNAL clk : std_logic := '0';SIGNAL clear : std_logic := '1';SIGNAL count_en : std_logic := '1';--OutputsSIGNAL counter_1 : std_logic_vector(3 downto 0);SIGNAL counter_2 : std_logic_vector(3 downto 0);SIGNAL counter_3 : std_logic_vector(3 downto 0);SIGNAL counter_4 : std_logic_vector(3 downto 0);SIGNAL counter_5 : std_logic_vector(3 downto 0);SIGNAL counter_6 : std_logic_vector(3 downto 0); BEGIN-- Instantiate the Unit Under Test (UUT)uut: counter PORT MAP(clk => clk,clear => clear,count_en => count_en,counter_1 => counter_1,counter_2 => counter_2,counter_3 => counter_3,counter_4 => counter_4,counter_5 => counter_5,counter_6 => counter_6);tb : PROCESSBEGINclk<='0';wait for 100 ns;clk<='1';wait for 100 ns;END PROCESS;END;仿真结果：分频器将原来48MHZ的频率分为100HZ和1000HZ，程序设计中采用了两个中间变量，通过控制中间变量来实现分频的目的，100HZ的中间变量的范围设置为240000，1000HZ的中间变量的范围设置为24000，下面请看程序：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity frequency isPort ( clkin: in STD_LOGIC;clk1k: out STD_LOGIC ;clk100 : out STD_LOGIC );end frequency;architecture Behavioral of frequency issignal count_temp1:integer range 1 to 240000:=1;signal count_temp2:integer range 1 to 24000:=1;signal a:STD_LOGIC:='0';signal b:STD_LOGIC:='0';beginprocess(clkin)beginif clkin'event and clkin = '1' thenif count_temp1 = 240000 thencount_temp1<= 1;a <= not a;elsecount_temp1<= count_temp1 + 1;end if;end if;if clkin'event and clkin = '1' thenif count_temp2= 24000 thencount_temp2<= 1;b<= not b;elsecount_temp2<=count_temp2 + 1;end if;end if;end process;clk100<=a;clk1K<=b;end Behavioral;测试文件：LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;ENTITY fenpin_test_vhd ISEND fenpin_test_vhd;ARCHITECTURE behavior OF fenpin_test_vhd IS-- Component Declaration for the Unit Under Test (UUT) COMPONENT frequencyPORT(clkin : IN std_logic;clk1k : OUT std_logic;clk100 : OUT std_logic);END COMPONENT;--InputsSIGNAL clkin : std_logic := '0';--OutputsSIGNAL clk1k : std_logic;SIGNAL clk100 : std_logic;BEGIN-- Instantiate the Unit Under Test (UUT)uut: frequency PORT MAP(clkin => clkin,clk1k => clk1k,clk100 => clk100);tb : PROCESSBEGINclkin<='0';wait for 100 ns;clkin<='1';wait for 100 ns;END PROCESS;END;测试结果：使能控制器设置一个中间变量，当一个下降沿来时，变量翻转一下，实现暂停开始的控制，下面来看程序：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity en isPort ( en_in : in STD_LOGIC;en_out : out STD_LOGIC);end en;architecture Behavioral of en issignal en_temp:STD_LOGIC:='0';beginprocess(en_in)beginif en_in'event and en_in='0' thenen_temp<=not en_temp;end if;end process;en_out<=en_temp;end Behavioral;测试文件LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;ENTITY en_test_vhd ISEND en_test_vhd;ARCHITECTURE behavior OF en_test_vhd IS-- Component Declaration for the Unit Under Test (UUT) COMPONENT enPORT(en_in : IN std_logic;en_out : OUT std_logic);END COMPONENT;--InputsSIGNAL en_in : std_logic ;--OutputsSIGNAL en_out : std_logic;BEGIN-- Instantiate the Unit Under Test (UUT)uut: en PORT MAP(en_in => en_in,en_out => en_out);tb : PROCESSBEGINen_in<='0';wait for 100 ns;en_in<='1';wait for 100 ns;END PROCESS;END;测试结果显示控制器通过1kz动态扫描输出，请看程序：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity multi isPort ( clk : in STD_LOGIC;counter1 : in STD_LOGIC_VECTOR (3 downto 0);counter2: in STD_LOGIC_VECTOR (3 downto 0);counter3: in STD_LOGIC_VECTOR (3 downto 0);counter4: in STD_LOGIC_VECTOR (3 downto 0);counter5: in STD_LOGIC_VECTOR (3 downto 0);counter6: in STD_LOGIC_VECTOR (3 downto 0);di: out STD_LOGIC;sel : out STD_LOGIC_VECTOR (2 downto 0);duanxuan : out STD_LOGIC_VECTOR (7 downto 0)); end multi;architecture Behavioral of multi issignal data_temp :STD_LOGIC_VECTOR (3 downto 0);signal seg:STD_LOGIC_VECTOR (7 downto 0);signal count:STD_LOGIC_VECTOR (2 downto 0):="000";beginprocess(clk)beginif clk'event and clk='1' thendi<='0';if count="101" thencount<="000";elsecount<=count+1;end if;end if;end process;sel<=count;process(count)begincase count iswhen "000"=>data_temp<=counter1;when "001"=>data_temp<=counter2;when "010"=>data_temp<=counter3;when "011"=>data_temp<=counter4;when "100"=>data_temp<=counter5;when "101"=>data_temp<=counter6;when others=>data_temp<="1111"; end case;end process;process(data_temp)begincase data_temp iswhen "0000"=>seg<="11000000";when "0001"=>seg<="11111001";when "0010"=>seg<="10100100";when "0011"=>seg<="10110000";when "0100"=>seg<="10011001";when "0101"=>seg<="10010010";when "0110"=>seg<="10000010";when "0111"=>seg<="11111000";when "1000"=>seg<="10000000";when "1001"=>seg<="10010000";when others=>seg<="11111111";end case;end process;duanxuan<=seg;end Behavioral;测试文件：LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;ENTITY multi_test_vhd ISEND multi_test_vhd;ARCHITECTURE behavior OF multi_test_vhd IS-- Component Declaration for the Unit Under Test (UUT)COMPONENT multiPORT(clk : IN std_logic;counter1 : IN std_logic_vector(3 downto 0);counter2 : IN std_logic_vector(3 downto 0);counter3 : IN std_logic_vector(3 downto 0);counter4 : IN std_logic_vector(3 downto 0);counter5 : IN std_logic_vector(3 downto 0);counter6 : IN std_logic_vector(3 downto 0);di : OUT std_logic;sel : OUT std_logic_vector(2 downto 0);duanxuan : OUT std_logic_vector(7 downto 0));END COMPONENT;--InputsSIGNAL clk : std_logic := '0';SIGNAL counter1 : std_logic_vector(3 downto 0) := "0000";SIGNAL counter2 : std_logic_vector(3 downto 0) := "0001";SIGNAL counter3 : std_logic_vector(3 downto 0) := "0010";SIGNAL counter4 : std_logic_vector(3 downto 0) := "0011";SIGNAL counter5 : std_logic_vector(3 downto 0) := "0100";SIGNAL counter6 : std_logic_vector(3 downto 0) := "1001";--OutputsSIGNAL di : std_logic;SIGNAL sel : std_logic_vector(2 downto 0);SIGNAL duanxuan : std_logic_vector(7 downto 0); BEGIN-- Instantiate the Unit Under Test (UUT)uut: multi PORT MAP(clk => clk,counter1 => counter1,counter2 => counter2,counter3 => counter3,counter4 => counter4,counter5 => counter5,counter6 => counter6,di => di,sel => sel,duanxuan => duanxuan );tb : PROCESSBEGINclk<='0';wait for 100 ps;clk<='1';wait for 100 ps;END PROCESS;END;测试结果：整体电路图：测试文件：LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;LIBRARY UNISIM;USE UNISIM.Vcomponents.ALL;ENTITY paobiao_schemtic_paobiao_schemtic_sch_tb ISEND paobiao_schemtic_paobiao_schemtic_sch_tb;ARCHITECTURE behavioral OF paobiao_schemtic_paobiao_schemtic_sch_tb IS COMPONENT paobiao_schemticPORT( clear : IN STD_LOGIC;clk : IN STD_LOGIC;enable : IN STD_LOGIC;jiedi : OUT STD_LOGIC;weixuan : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);duanxuan : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));END COMPONENT;SIGNAL clear : STD_LOGIC:='1';SIGNAL clk : STD_LOGIC;SIGNAL enable : STD_LOGIC:='1';SIGNAL jiedi : STD_LOGIC;SIGNAL weixuan : STD_LOGIC_VECTOR (2 DOWNTO 0);SIGNAL duanxuan :STD_LOGIC_VECTOR (7 DOWNTO 0);BEGINUUT: paobiao_schemtic PORT MAP(clear => clear,clk => clk,enable => enable,jiedi => jiedi,weixuan => weixuan,duanxuan => duanxuan);-- *** Test Bench - User Defined Section ***tb : PROCESSBEGINclk<='0';wait for 10 ns;clk<='1';wait for 10 ns;END PROCESS;-- *** End Test Bench - User Defined Section ***END;仿真结果图：结果分析首先对数字跑表进行了分析，将其分成了几个模块，然后对每个模块进行单独设计，仿真，由以上仿真结果可以看出，对应的每个模块都能实现其功能。