基于AD7819的ad测试板设计(附原理图和源代码)

NET BUSYLOC = B6 | IOSTANDARD = "LVCMOS33"; ## 6
NET RD LOC = A7 | IOSTANDARD = "LVCMOS33"; ## 8
NET CS LOC = A8 | IOSTANDARD = "LVCMOS33"; ## 10
NET CONVST LOC = A9 | IOSTANDARD = "LVCMOS33"; ## 12
NET DATAIN<7> LOC = E11 | IOSTANDARD = "LVCMOS33"; ## 28
实物图如下：
连接在开发板上之后，AD芯片即开始工作。使用示波器分别发出不同频率的信号，同时使用chipscope抓取波形，再输出数据到matlab中，经FFT后可得如下频谱：
测试程序为：
clear;clc;
NET DATAIN<4> LOC = B16 | IOSTANDARD = "LVCMOS33"; ## 22
NET DATAIN<5> LOC = C16 | IOSTANDARD = "LVCMOS33"; ## 24
NET DATAIN<6> LOC = E15 | IOSTANDARD = "LVCMOS33"; ## 26
if (ctrl_clk_r == t_power_up1)
begin
ctrl_state <= 4'd1;
CONVST_r <= 1'd0;
ctrl_clk_r <= 9'd0;
end
else
begin
ctrl_state <= 4'd0;
ctrl_clk_r <= ctrl_clk_r + 9'd1;
//reg[3:0] ctrl_state;
reg[8:0] ctrl_clk_r;
reg[7:0] data_in_r;
reg[8:0] chip_clk_cnt;
reg chip_clk;
always @(posedge CLK or negedge RSTn) //处于测试需要，选择了AD手册上的136k的采样频率。
begin chip_clk <= 1; chip_clk_cnt<= 9'd0; end
else
chip_clk_cnt<= chip_clk_cnt + 1;
end
always @(posedge CLK or negedge RSTn)
if (!RSTn)
begin
CONVST_r <= 1'd0; //按照芯片收测，要先置零
assign TRIG0[12]=CONVST;
assign TRIG0[13]=CS;
assign TRIG0[14]=RD;
//assign TRIG0[15]=Busy_r;
assign TRIG0[15]=BUSY;
//assign TRIG0[16]=Done_sig;
endmodule
UCF如下：
end
end
1: begin
if (ctrl_clk_r == t_wait) //t1
begin
ctrl_state <= 4'd2;
ctrl_clk_r <= 9'd0;
end
else
begin
ctrl_clk_r <= ctrl_clk_r + 9'd1;
ctrl_state <= 4'd1;
);
reg Busy_r;
reg Done_sig_r; assign Done_sig = Done_sig_r;
reg CONVST_r; assign CONVST = CONVST_r;
reg CS_r; assign CS = CS_r;
reg RD_r; assign RD = RD_r;
module AD_ctrl(
input CLK,
input RSTn,
input BUSY,
input [7:0] DATAIN,
//input Start_sig,
output RD,
output CS,
output CONVST,
output reg[3:0] ctrl_state,
output Done_sig
NET CLKLOC = T8 | IOSTANDARD = "LVCMOS33"; ## system CLK
#DA相关引脚(J3)
##
NET RSTn LOC = L3 | IOSTANDARD = "LVCMOS33"; ## Reset Button
##
NET DATAIN<0> LOC = B5 | IOSTANDARD = "LVCMOS33"; ## 4
CS_r <= 1'd1;
RD_r <= 1'd1;
ctrl_state <= 4'd0;
data_in_r <= 8'd0;
Busy_r <= 1'd0;
ctrl_clk_r <= 9'd0;
end
else
case (ctrl_state)
0: //1.5μs的power_up
begin
CONVST_r <= 1'd1;
fs = 136000;
N = 1024;
Y = fft(DATA);
P2 = abs(Y/N);
P1 = P2(1:N/2+1);
P1(2:end-1) = 2*P1(2:end-1);
f = fs*(0:(N/2))/N;
dout_db = 20*log10(P1);
plot(f,dout_db);
xlLoadChipScopeData('data.prn');
DATA = (DATA-127.5)./127.5; %归一化处理后，才可以使用FFT。DATA为chipscope中采样信号bus的名称。
%%function [f,dout_db] = fft_test(fin,fs,N,y)
fin = 4001;
// .CLK(dma_clk), // IN
.CLK(chip_clk), // IN
.TRIG0(TRIG0) // IN BUS [255:0]
//.TRIG_OUT(TRIG_OUT0)
);
assign TRIG0[7:0]=data_in_r;
assign TRIG0[11:8]=ctrl_state;
// Company:
// Engineer:
//
// Create Date: 18:33:57 03/12/2017
// Design Name:
// Module Name: AD_ctrl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
NET DATAIN<1> LOC = A12 | IOSTANDARD = "LVCMOS33"; ## 16
NET DATAIN<2> LOC = A13 | IOSTANDARD = "LVCMOS33"; ## 18
NET DATAIN<3> LOC = B14 | IOSTANDARD = "LVCMOS33"; ## 20
//处于测试需要，选择了AD手册上的136k的采样频率。总的周期数为368，去除t_power_up和t_relinquish，t_relinquish可取322。
parameter t_power_up1 = 9'd40; // (1.5μs对应的时钟数为75，由于使用mode2，所以选择了较小的40个周期。
axis([0 fs/2 -150 0]);
title(sprintf('%g -Samples FFT Spectrum\nfs = %g MSps, fin = %g MHz', ...
N,fs/1000000,fin/1000000));
xlabel('Frequency [Hz]');
ylabel('Power [dB]');
ctrl_state <= 4'd4;
else
begin
ctrl_state <= 4'd3;
ctrl_clk_r <= ctrl_clk_r + 9'd1;
end
end
4:begin
ctrl_state <= 4'd0;
ctrl_clk_r <= 9'd0;
end
default: ctrl_state <= 4'd0;
频谱分析结果如下：
5khz
10khz
15khz
30khz
在输入15khz频率以上时，即发生了很大失真。主要的失真为谐波失真，原因主要是pcb布线、电容摆放的问题等等，需要继续改进！
end
end
2: begin
CS_r <= 1'd0;