第二讲 表面微机械加工技术应用

牺牲层技术刻蚀与选择性etch：To cut into the surface of (glass, for example) by the action of acid.Etching：The art of preparing etched plates, especially metal plates, from which designs and pictures are printed. Corrode：To destroy a metal or alloy gradually, especially by oxidation or chemical action其实刻蚀还包含分解、转化、溶解等一系列含义。

半导体技术的刻蚀并不仅仅局限于金属材料，半导体、化合物、包括有机物薄膜才是刻蚀研究的重点。

Etching还有一个特征：选择性或者局部队有控制刻蚀。

干法刻蚀也是半导体技术赋予Etching的新内涵。

选择性源于化学反应的热力学选择性和刻蚀过程度动力学因素控制。

下面这张表格概括了一些简单物质与常用反应物之间相互作用的规律，其中既有热力学因素控制的结果，也有动力学因素促成。

它们都是湿法反应机制度结果MUMPS工艺概况The MUMPS process is a three-layer polysilicon surface micromachining process derived from work performed at the Berkeley Sensors and Actuators Center (BSAC) at the University of California.Several modifications and enhancements have been made to increase the flexibility and versatility of the process for the multi-user environment. The process flow described below is designed to introduce inexperienced users to polysilicon micromachining. The text is supplemented by detailed drawings that show the process flow in the context of building a typical micromotor.工艺流程详解衬底：100 mm n-type (100) silicon wafers of 1-2 ohm-cm resistivity.低阻硅片1. The surface of the wafers are first heavily doped with phosphorus in a standard diffusion furnace using POCl3 as the dopant source.This helps to reduce or prevent charge feed through to the substrate from electrostatic devices on the surface.2. 600 nm low-stress LPCVD(low pressure chemical vapor deposition) silicon nitride layer is deposited on the wafers as an electrical isolation layer.3. deposition of a 500 nm LPCVD polysilicon film-Poly 0.4. the coating of the wafers with photoresist5. Exposure of the photoresist with the appropriate mask6. Developing the exposed photoresist to create the desired etch mask for subsequent pattern7. Transfer into the underlying layer －The Poly 0 layer is then etched in an RIE system只刻蚀多晶硅而不刻蚀硅，需要细致选择刻蚀剂和刻蚀工艺8. After etch, the photoresist is chemically stripped in a solvent bath.9. A 2.0 µm phosphosilicate glass (PSG) sacrificial layer is then deposited by LPCVD10. coating of the wafers with photoresist11 Exposure of the photoresist with the DIMPLES mask12. Developing the exposed photoresist to create the desired etch mask for subsequent pattern13. the 1st oxide layer is then etched in an RIE system to form dimples14. After etch, the photoresist is chemically stripped in a solvent bath.The depth of the dimples is 750 nm上述五步重复了前一次的过程，是表面微机械加工最典型的工艺循环15.-19 The wafers are then patterned with the third mask layer, ANCHOR1, and reactive ion etched. This step provides anchor holes that will be filled by the Poly 1 layer.第一层牺牲层经历了两次加工，为什么不一次完成？还有其它的技术途径选择吗？20. the first structural layer of polysilicon (Poly 1) is deposited ata thickness of 2.0 µm.21. A thin (200 nm) layer of PSG is deposited over the polysilicondimples 处的高度会有起伏，这里未有表达。

22. the wafer is annealed at 1050°C for 1 hour，The anneal dopes the polysilicon with phosphorus from the PSG layers both above and below it.The anneal also serves to significantly reduce the net stress in the Poly 1 layer.（为什么从两侧同时扩散掺杂？）23－27 The polysilicon (and its PSG masking layer) is lithographically patterned using a mask designed to form the first structural layer POLY1.（涂胶－光刻－显影－RIE刻蚀－去胶）刻蚀PSG和氮化硅的工艺参数不同，且有选择性，尤其应当注意通常PSG充当氮化硅刻蚀的硬掩膜，可以实现良好图形转移效果。

28.以RIE刻蚀清除表面的残余PSG（可以不去吗？）29.The second PSG layer (Second Oxide) is deposited（0.75µm）30－34 The POLY1_POLY2_VIA level provides for etch holes in the Second Oxide down to the Poly 1 layer. This provide a mechanical and electrical connection between the Poly 1 and Poly 2 layers.（部分清除第二层氧化硅以使即将沉积的第二层硅与第一层硅结合，同样经历涂胶－光刻－显影－RIE刻蚀－去胶循环）35-39.同样循环操作开出贯通上下的通孔，为制作固定连接的轴套留出空间（为什么要一次性刻穿第一第二层牺牲层？刻蚀终止于第一层硅可以吗？）40. The second structural layer, Poly 2, is then deposited (1.5 µm thick)41. the deposition of 200 nm PSG. On the top of POLY2(As with Poly 1, the thin PSG layer acts as both an etch mask and dopant source for Poly 2)42 The wafer is annealed for one hour at 1050° C to dope the polysilicon and reduce the residual film stress.43－47.The Poly 2 layer is lithographically patterned with the seventh mask (POLY2) and the PSG and polysilicon layers are etched by RIE using the same processing conditions as for Poly1 48.the masking oxide is removed49－54.The final deposited layer in the MUMPs process is a 0.5 µm metal layer that provides for probing, bonding, electrical routing and highly reflective mirror surfacesthe metal is deposited and patterned using lift-off（涂胶－光刻－显影－沉积金属－剥离光刻胶）55.分片、包装、发送给用户56刻蚀牺牲层（The release is performed by immersing the chip in a bath of 49% HF (room temperature) for 1.5-2 minutes.）57.This is followed by several minutes in DI water and then alcohol to reduce stiction followed by at least 10 minutes in an oven at 110° CSUMMiTSandia Ultra-planar, Multi-level MEMS Technology isA four-layer polycrystalline silicon surfacemicromachining process立意：The challenges associated with additional layers of polysilicon in a surface micromachining fabrication process are significant, and are primarily related to residual film stress and device topography. Fortunately, Sandia's SUMMiT TM Fabrication Process overcomes these challenges. 优势：∙Chemical-mechanical planarization eliminates inter-level interference∙Sandia's ultra-low-stress mechanical polysilicon maintains device integrity.∙Utilizes 1-micron design rulesWhy the another additional layer is important？with a ground plane and one mechanical layer (a so-called two-layer process), an actuating comb drive can be fabricated. With two mechanical layers, mechanisms such as a gear constrained to rotate on a hub, and various types ofmirrors are possible. When a third mechanical layer is added, the possiblities include not just linkages to connect actuators to mechanisms, but also an enormous range of new design possibilities that is staggering in scope.残余应力控制的重要性和结果Residual stress can result in the mechanical layers being bowed out of plane, resulting indifficult-to-calibrate devices, non-reproducible devices, or still worse, non-functioning devices. MEMS foundries, even those dealing with only one or twomechanical layers, often find it a challenge to reproducibly reduce polysilicon stress to an acceptable level. Sandia has developed a proprietary process through which it maintains stress levels at typically less than 5MPa. Meshed gears, each 2000 microns in diameter, have been successfully fabricated and operated.直径2毫米的薄膜齿轮共平面技术：Device topography can make it difficult to pattern and etch subsequent layers of polysilicon. In addition, topography can result in structural artifacts that severely constrain the range of designs that can be successfully implemented. To mitigate the problems caused by topography, Sandia has implemented a proprietary planarization method based on Chemical-Mechanical Polishing (CMP).。