4012 CMOS 双4输入与非门

TL F 5940CD4002M CD4002C Dual 4-Input NOR Gate CD4012M CD4012C Dual 4-Input NAND Gate

March 1988

CD4002M CD4002C Dual 4-Input NOR Gate CD4012M CD4012C Dual 4-Input NAND Gate

General Description

These NOR and NAND gates are monolithic complementa-ry MOS (CMOS)integrated circuits The N-and P-channel enhancement mode transistors provide a symmetrical cir-cuit with output swings essentially equal to the supply volt-age This results in high noise immunity over a wide supply voltage range No DC power other than that caused by leak-age current is consumed during static conditions All inputs are protected against static discharge and latching condi-tions

Features

Y Wide supply voltage range 3 0V to 15V Y Low power

10nW (typ )Y

High noise immunity

0 45V DD (typ )

Applications

Y Automotive Y Alarm system Y Data terminals Y Industrial controls Y Instrumentation Y Remote metering Y

Medical Electronics

Y

Computers

Connection Diagrams

CD4002

Dual-In-Line Package

TL F 5940–1Top View

CD4012

Dual-In-Line Package

TL F 5940–2

Top View

Order Number CD4002or CD4012

C 1995National Semiconductor Corporation RRD-B30M105 Printed in U S A

Absolute Maximum Ratings(Note1)

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin V SS b0 3V to V DD a0 3V Operating Temperature Range

CD4002M CD4012M b55 C to a125 C CD4002C CD4012C b40 C to a85 C Storage Temperature Range(T S)b65 C to a150 C Power Dissipation(P D)

Dual-In-Line700mW Small Outline500mW Operating Range(V DD)V SS a3 0V to V SS a15V Lead Temperature(T L)

(Soldering 10seconds)260 C

DC Electrical Characteristics CD4002M CD4012M

Limits

Symbol Parameter Conditions b55 C a25 C a125 C Units

Min Max Min Typ Max Min Max

I DD Quiescent V DD e5 0V0 050 0010 053 0m A

Device Current V DD e10V0 10 0010 16m A P D Quiescent Device V DD e5 0V0 250 0050 2515m W Dissipation Package V DD e10V1 00 011 060m W V OL Output Voltage V DD e5 0V V I e V DD I O e0A0 0500 050 05V Low Level V DD e10V V I e V DD I O e0A0 0500 050 05V V OH Output Voltage V DD e5 0V V I e V SS I O e0A4 954 955 04 95V High Level V DD e10V V I e V SS I O e0A9 959 95109 95V V NL Noise Immunity V DD e5 0V V O e3 6V I O e0A1 51 52 251 4V (All Inputs)V DD e10V V O e7 2V I O e0A3 03 04 52 9V V NH Noise Immunity V DD e5 0V V O e0 95V I O e0A1 41 52 251 5V (All Inputs)V DD e10V V O e2 9V I O e0A2 93 04 53 0V I D N Output Drive Current V DD e5 0V V O e0 4V V I e V DD0 50 401 00 28mA

N-Channel(4002)V DD e10V V O e0 5V V I e V DD1 10 92 50 65mA (Note2)

I D P Output Drive Current V DD e5 0V V O e2 5V V I e V SS b0 62b0 5b2 0b0 35mA

P-Channel(4002)V DD e10V V O e9 5V V I e V SS b0 62b0 5b1 0b0 35mA (Note2)

I D N Output Drive Current V DD e5 0V V O e0 4V V I e V DD0 310 250 50 175mA

N-Channel(4012)V DD e10V V O e0 5V V I e V DD0 630 50 60 35mA (Note2)

I D P Output Drive Current V DD e5 0V V O e2 5V V I e V SS b0 31b0 25b0 5b0 175mA

P-Channel(4012)V DD e10V V O e9 5V V I e V SS b0 75b0 6b1 2b0 4mA (Note2)

I I Input Current10pA

Note1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed Except for‘‘Operating Temperature Range’’they are not meant to imply that the devices should be operated at these limits The table of‘‘Electrical Characteristics’’provides conditions for actual device operation

Note2 I D N and I D P are tested one output at a time

2