LCD1621(屏驱动)

S E G 15 S E G 14 S E G 13 S E G 12 S E G 11 S E G 10
SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2
SEG 1 SEG 0
CS
1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
HT1621
Unit:mil
Y
-25.29 -18.66 -11.94 -5.31
1.32 7.95 14.58 21.21 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46 59.46
SEG 7 SEG 9 S E G 11 S E G 13 S E G 15 S E G 17 S E G 19 S E G 21 S E G 23 S E G 25 S E G 27 S E G 29 S E G 31 COM 2
3
July 26, 1999
Pad Assignment
HT1621
frequency source input · Selection of 1/2 or 1/3 bias, and selection of
1/2 or 1/3 or 1/4 duty LCD applications · Internal time base frequency sources · Two selectable buzzer frequencies
4
July 26, 1999
Pad Coordinates
Pad No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
X
-55.04 -58.52 -58.52 -58.52 -58.52 -58.52 -58.52 -58.52 -58.52 -58.52 -44.07 -31.58 -20.70 -13.98 -7.05 -0.34
Pad No.
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
X
58.14 58.14 58.14 58.14 58.14 58.14 58.14 58.14 55.55 48.92 42.29 35.66 29.03 22.40 15.77 9.14 2.42 -4.21 -10.84 -17.47 -24.10 -30.73 -38.17 -45.39
Chip selection input with pull-high resistor
When the CS is logic high, the data and command read from or
I
written to the HT1621 are disabled. The serial interface circuit is also reset. But if CS is at logic low level and is input to the CS
instructions · R/W address auto increment · Three data accessing modes · VLCD pin for adjusting LCD operating
voltage
General Description
The HT1621 is a 128 pattern (32´4), memory mapping, and multi-function LCD driver. The S/W configuration feature of the HT1621 makes it suitable for multiple LCD applications including LCD modules and display sub-
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
H T1621 - 48 S S O P
SEG 8 SEG 9 S E G 10 S E G 11 S E G 12 S E G 13 S E G 14 S E G 15 S E G 16 S E G 17 S E G 18 S E G 19 S E G 20 S E G 21 S E G 22 S E G 23 S E G 24 S E G 25 S E G 26 S E G 27 S E G 28 S E G 29 S E G 30 S E G 31
systems. Only three or four lines are required for the interface between the host controller and the HT1621. The HT1621 contains a power down command to reduce power consumption.
HT1621
2
July 26, 1999
Pin Assignment
SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0
CS RD WR D ATA VSS O SCO NC O SCI V D D /V L C D IR Q BZ BZ COM 0 COM 1 COM 2 COM 3
pad, the data and command transmission between the host con-
troller and the HT1621 are all enabled.
READ clock input with pull-high resistor Data in the RAM of the HT1621 are clocked out on the falling I edge of the RD signal. The clocked out data will appear on the DATA line. The host controller can use the next rising edge to latch the clocked out data.
Selection Table
HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
COM
4
4
8
8
8
8
16
16
16
SEG
32
32
32
32
48
64
48
64
64
Built-in Osc.
Ö
Ö
Ö
Ö
Ö
Ö
Crystal Osc. Ö
(2kHz/4kHz) · Power down command reduces power
consumption · Built-in time base generator and WDT · Time base or WDT overflow output
· 8 kinds of time base/WDT clock sources · 32 ´ 4 LCD driver · Built-in 32 ´ 4 bit display RAM · 3-wire serial interface · Internal LCD driving frequency source · Software configuration feature · Data mode and command mode
H T1621B - 4 8 S S O P /D IP
HT1621
SEG 5 SEG 3 SEG 1
CS RD WR D ATA VSS V LC D VDD IR Q BZ COM 0 COM 1
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
H T1621D - 2 8 S k in n y
6.33 12.96 19.59 58.14 58.14 58.14 58.14 58.14
Y
59.46 22.18 15.56 5.36 -4.51 -11.14 -34.76 -41.90 -49.13 -59.08 -59.08 -59.08 -59.08 -59.08 -59.08 -59.08 -59.08 -59.08 -59.08 -58.44 -51.81 -45.18 -38.55 -31.92
S E G 29 S E G 30 S E G 31 COM 3 COM 2 COM 1 COM 0
BZ
BZ
IR Q
ቤተ መጻሕፍቲ ባይዱ
Chip size: 127 ´ 129 (mil)2 * The IC substrate should be connected to VDD in the PCB layout artwork.
RD 2 WR 3
D ATA 4
(0 ,0 )
VSS 5
O SCO 6
O SCI 7 V LC D 8
VDD 9
10
11
12
13 14 15 16 17 18 19
32 S E G 16 31 S E G 17 30 S E G 18 29 S E G 19 28 S E G 20 27 S E G 21 26 S E G 22 25 S E G 23 24 S E G 24 23 S E G 25 22 S E G 26 21 S E G 27 20 S E G 28
48 S E G 8 47 S E G 9 46 S E G 10 45 S E G 11 44 S E G 12 43 S E G 13 42 S E G 14 41 S E G 15 40 S E G 16 39 S E G 17 38 S E G 18 37 S E G 19 36 S E G 20 35 S E G 21 34 S E G 22 33 S E G 23 32 S E G 24 31 S E G 25 30 S E G 26 29 S E G 27 28 S E G 28 27 S E G 29 26 S E G 30 25 S E G 31
HT1621
RAM Mapping 32´4 LCD Controller for I/O mC
Features
· Operating voltage : 2.4V~5.2V · Built-in 256kHz RC oscillator · External 32.768kHz crystal or 256kHz
T o n e F re q u e n c y G e n e ra to r
W a tc h d o g T im e r and
T im e B a s e G e n e r a to r
COM 0 COM 3 SEG 0
S E G 31 V LC D
IR Q
Notes:
CS: Chip selection BZ, BZ: Tone outputs WR, RD, DATA: Serial interface COM0~COM3, SEG0~SEG31: LCD outputs IRQ: Time base or WDT overflow output
SEG 7 1 SEG 6 2 SEG 5 3 SEG 4 4 SEG 3 5 SEG 2 6 SEG 1 7 SEG 0 8
CS 9 R D 10 W R 11 D A TA 12 V S S 13 O S C O 14 O S C I 15 V LC D 16 V D D 17 IR Q 1 8 B Z 19 B Z 20 C O M 0 21 C O M 1 22 C O M 2 23 C O M 3 24
Ö
Ö
Ö
Ö
Ö
Ö
1
July 26, 1999
Block Diagram
O SCO O SCI CS RD WR D ATA
VDD VSS
BZ BZ
C o n tro l and
T im in g C ir c u it
D is p la y R A M
L C D D r iv e r / B ia s C ir c u it
5
July 26, 1999
HT1621
Pad Description
Pad No. Pad Name
1
CS
2
RD
3
WR
4
DATA
5
VSS
7
OSCI
6
OSCO
8 9 10 11, 12 13~16 48~17
VLCD VDD IRQ BZ, BZ COM0~COM3 SEG0~SEG31
I/O
Function