VCS常用命令说明

VCS常用命令说明1、VCS仿真环境：

2、VCS常用编译命令：

vcs source_files [source_or_object_files] options

eg: vcs top.v toil.v -RI +v2k

source_files

The Verilog, OpenVera assertions, or OpenVera testbench source files for your design separated by spaces.

source_or_object_files

Optional C files (.c), object files (.o), or archived libraries (.a). These are DirectC or PLI applications that you want VCS to link into the binary executable file along with the object files from your Verilog source files.

Options

Compile-time options that control how VCS compiles your Verilog source files. Details of Options:

+incdir+directory: Specifies the directory or directories that VCS searches for include files used in the `include compiler directive. More than one directory may be specified, separated by +.

-I: Compiles for interactive use.

-line: Enables source-level debugging tasks such as stepping through the code, displaying the order in which VCS executed lines in your code, and the last statement executed before simulation stopped. Typically you enter this option with a +cli option,

for example: vcs +cli+1 -line

-l filename:Specifies a file where VCS records compilation messages. If you also enter the -R or -RI option, VCS records messages from both compilation and simulation in the same file.

-P pli.tab: Compiles a user-defined PLI definition table file.

-PP: Compiles a VCD file for interactive debugging while minimizing the amount of net data for fast post-processing.

+v2k: Enables new language features in the proposed IEEE 1364-2001 standard. See “Implemented IEEE Std 1364-2001 Language Constructs” on page 2-23.

-v filename:Specifies a Verilog library file. VCS looks in this file for module and UDP definitions for the module and UDP instances that VCS found in your source code when it did not find the corresponding module or UDP definitions in your source code.

+define+macro:Defines a text macro in your source code to a value or character string. You can test for this definition in your Verilog source code using the …ifdef compiler directive.

-f filename: Specifies a filename that contains a list of absolute pathnames for Verilog source files and compile-time options.

+vc: Enables extern declarations of C/C++ functions and calling these functions in your source code.

-vera: Specifies the standard VERA PLI table file and object library.

-comp64: option to compile a design on a 64-bit machine;

3、VCS运行命令

1、Running:

$ simv

2、Save and Restart Example

A simple example of save and restart is given below to demonstrate the basic functionality.

The $save call does not execute a save immediately, but schedules the checkpoint save at the end of the current simulation time just before events scheduled with #0 are processed. Therefore, events delayed with #0 are the first to be processed upon restart. Example:

test.v：

module simple_restart;

initial begin

#10

$display("one");

$save("test.chk");

$display("two");

#0 // make the following occur at restart

$display("three");