复旦计算机08级2010春季期末考试试题A

复旦大学计算机科学技术学院

《计算机原理》期末考试试卷

A卷共 13页

课程代码：INFO130054.01-02 _考试形式：开卷2010年6月（本试卷答卷时间为100分钟，答案必须写在答卷上，做在试卷上无效）

专业学号姓名成绩

Problem 1.

Number Conversion: IEEE 754 single precision 32-bit float standard representation with a little change is illustrated below.

Normalized: (-1)sign * (1.fraction) * 2exponent-127(exp=1 to 254)

Denormalized: (-1)sign * (0.fraction) * 2-126(when exp=0, fraction≠0)

Zero: all 0’s in all 3 fields

1)Convert the number -35.390625 into this changed IEEE 754 FP single precision

representation (in hex).

(-35.390625)10= (0x )16

1

2)With changed 32-bit float representation, what is the equivalent value as a

decimal number?

A: (0011 1111 0001 0000 0000 0000 0000 0000)2

B: (0000 0000 0011 0101 0000 0000 0000 0000)2

3)Calculate the sum of (35.390625)10 and (0011 1111 0001 0000 0000 0000 0000

0000)2using changed 32-bit float representation, and then round the sum (in binary number value, e.g. (1000.11)2for (8.75)10 ) to 4 bits to the right of the binary point by both round-up and round-down. Give your steps detailed.

4)Given three numbers f1, f2 and f3 of this changed 32-bit representation, none of

them equals +∞, -∞or NaN, and x is signed 32-complement representation.

Please tell whether two C expressions below are always true. If yes, give the reason in detail; If no, give a counterexample and show the detail computation steps to get false.

A: x = = (int) (float) x;

B: (f1 > f2) = = ((f1 + f3) > (f2 + f3))

2

Problem 2.

Please read the following C code and assembly code and then fill in the blanks.

The assembly code:

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Please give the reason for the blanks you filled in the assembly code and the result of the printf in main function.

4

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Problem 3.

The following figure illustrates a five stage pipeline processor similar to that in your text book (Figure 4.53, Page 334 in English Book). Notice there are three differences

for this architecture from that in your book.

First difference is that Function Units in Stage E become multi-cycle function units. Now stage E contains three function units, two Adder and one Subtracter. The Subtracter can only handle subtraction operations and takes 3 cycles to completion. The Adder can handle other calculation exception subtraction and takes 2 cycles to completion. Notice one Adder or Substracter can handle only one instruction at a time, that is, other instructions must wait in its Stage D until the expected Adder or Substracter is free.

Second difference is that Memory Units will consume different cycle to complete a memory access. For a cache hit , it takes 1 cycle; for a cache miss , it takes 6 cycles; for a non-memory instruction , it takes 1 cycle to pass Stage M. And only one instruction can occupy the memory units, that is, if two memory instructions are entering the Stage M at the same time, the second instruction will wait the first instruction to complete before retrieve its own memory data.

Third difference is that this architecture is 2-issue in-order pipeline processor. It means the fetch stage can fetch at most two instructions and all the state registers between stages can also store at most two instructions’ states. The fetch units will fetch as many instructions as possible to fill the state registers between Stage F and Stage D.