A3977步进电机驱动芯片中文说明

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A3967SLB中文资料

A3967中文资料A3967SLTB带转换器的微步进驱动芯片特点±750毫安，30 V额定输出Satlington™灌电流驱动器自动电流衰减模式检测/选择3.0 V至5.5 V逻辑电源电压范围混合，快与慢电流衰减模式内部欠压锁定（UVLO）和热关断电路交叉电流保护描述A3967SLB是一个完善的微电机驱动器内置逻辑器。

它的设计操作双极步进电机具有全步进，1/2，1/4，和1/8模式，输出驱动能力30 V和±750毫安。

A3967SLB包括一个固定关断时间的电流调节器，具有慢，快，或混合电流衰减模式的功能。

此电流衰减控制方案可以减少可听到的电流噪音，增加步进精确度，并减少功耗。

A3967SLB的驱动转换非常容易实现，通过简单的“步进”输入中输入一个脉冲电动机将产生一个步骤（全，半，四分，或八分，这取决于两个逻辑输入）。

无需相位顺序表、高频率控制线或复杂的程序。

该A3967SLB是一个理想的适合复杂的微型项目开发的接口驱动芯片。

内部电路保护包括热关机与滞后，电压锁定（UVLO）下和交叉电流保护。

不需要特别的加电排序。

A3967SLB是提供一个24-PIN SOIC封装，能够自由焊接的磨砂100％雾锡引线框架。

选项卡处于接地电位，并且不需要绝缘。

的无铅（100％雾锡引线框架）版本也已经推出。

绝对最大额定值热特性热特性表电气特性在T A = +25°C，V BB = 30 V，V CC = 3.0 V至5.5V（除非另有说明）功能说明设备操作A3967 是一个操作方便、控制线少、完整的微型步进电机驱动器，。

它可用于双极步进电机在全，半，四分和八分模式的操作。

每两个中的电流 H桥输出的调节与固定关断时间脉冲宽度调制（PWM）控制电路。

在每个步骤中的电流由一个外部的值被设置电流检测电阻（R S），一个参考电压（V REF），以及 DAC 的输出电压的输出，通过控制转换。

在上电或复位时，将根据DAC设置和相电流极性初始的内部状态设置转换（见图内部状态情况），并设定的电流调节器两相混合衰减模式。

基于A3977两相步进电机驱动器的应用

成。在每个Ｎ沟道ＤＳ输出的个预先定义的起始状态（ＯＨＭＥ）并关闭所有，
的ＤＳ输出。ＨＯＭＯＭＥ输出为低电平时，有的ＳＥ所ＴＰ输入无效，直到雨丽
示器。
（）ＨＯ３ＭＥ输出：是分配器开始状态的逻辑指它（）ＳＥ４ＴＰ输入：ＴＰ输入的一个上升沿将脉冲ＳＥ分配器转到下一个顺序状态，而且使电机前进一个增量，量的大小由输入的ＭＳ增１和ＭＳ２的状态决定。
（）ＤＲ（向）入：定电机的旋转方向。（）５Ｉ方输决６
１１工作原理．
图１Ａ３７９７内部框图
１２主要引脚功能说明．
（）面１
：在系统不工作时选择睡眠模式，电低
平有效，选择睡眠模式可以减少功耗，当为高电平时进
入正常模式。（）２雨丽（复位）入：电平有效，设定分配输低它
平高或相等，么电流衰减模式将会是慢速的，电流那此衰减模式自动选择将减少由于电动机的反电动势引起
的电流波形扭曲，而改善性能［从２１。
Ａ９７在许多场合就得到了很好的应用。由于其自有３７，
脉冲分配器使控制线最少，易操作，泛用于不适宜容广用微处理器或为了减轻微处理器的负担的系统
个脉冲，电机就走一步，需要相序表、不高频控制线或复杂的程序接Ｉ。最后还介绍了Ａ９７典型应用电路。２＇３７的

电机驱动芯片选型-步进电机和BLDC-Allegro

厂家型号描述Allegro A3901Dual Full Bridge Low Voltage Motor DriverAllegro A3916Dual DMOS Full-Bridge Motor DriverAllegro A3966Dual Full-Bridge PWM Motor DriverAllegro A3967Microstepping Driver with TranslatorAllegro A3977Microstepping DMOS Driver with TranslatorAllegro A3979Microstepping DMOS Driver with TranslatorAllegro A3981K Automotive, Programmable Stepper DriverAllegro A3982DMOS Stepper Motor Driver with TranslatorAllegro A3983DMOS Microstepping Driver with TranslatorAllegro A3984DMOS Microstepping Driver with TranslatorAllegro A3985Digitally Programmable Dual Full-Bridge MOSFET DriverAllegro A3987DMOS Microstepping Driver with TranslatorAllegro A3988Quad DMOS Full Bridge PWM Motor DriverAllegro A3989Bipolar Stepper and High Current DC Motor DriverAllegro A3992DMOS Dual Full-Bridge Microstepping PWM Motor DriverAllegro A3995DMOS Dual Full Bridge PWM Motor DriverAllegro A3998Dual DMOS Full Bridge Motor Driver With Serial Port Control and Allegro A4970Dual Full-Bridge PWM Motor DriverAllegro A4975Full-Bridge PWM Microstepping Motor DriverAllegro A4979Microstepping Programmable Stepper Motor Driver With Stall Dete Allegro A4980K Automotive, Programmable Stepper DriverAllegro A4982DMOS Microstepping Driver with Translator And Overcurrent Prote Allegro A4983DMOS Microstepping Driver with TranslatorAllegro A4984DMOS Microstepping Driver with Translator And Overcurrent Prote Allegro A4985DMOS Microstepping Driver with Translator And Overcurrent Prote Allegro A4986DMOS Dual Full-Bridge PWM Motor Driver With Overcurrent Protect Allegro A4987DMOS Dual Full-Bridge PWM Motor Driver with Overcurrent Protect Allegro A4988DMOS Microstepping Driver with Translator And Overcurrent Prote Allegro A4989Dual Full-Bridge MOSFET Driver with Microstepping Translator Allegro A4990K Automotive Dual Full Bridge DriveAllegro A4992K Automotive Stepper DriverAllegro A4993Automotive Stepper Motor DriverAllegro A5976Microstepping DMOS Driver with TranslatorAllegro A5977Microstepping DMOS Driver with TranslatorAllegro A5979Microstepping DMOS Driver with TranslatorAllegro A5984DMOS Microstepping Driver with Translator And Overcurrent Prote Allegro A5985DMOS Microstepping Driver with Translator And Overcurrent Prote Allegro A5988Bipolar Stepper and High-Current DC Motor DriverAllegro A5989Bipolar Stepper and High-Current DC Motor DriverAllegro A5990Quad DMOS Full-Bridge PWM Motor DriverAllegro AMT49701Quad DMOS Full-Bridge PWM Motor DriverAllegro AMT49702Dual DMOS Full-Bridge Motor Driver后缀“K”表示汽车级产品（通过 AEC-Q100 认证）下列器件已停产：A3986, A3972电桥数量峰值输出电流最大电源电压接口位置反馈最小电源电压Parallel External 2.5 5.50.4Full-Bridge x2 Parallel External 2.7151Full-Bridge x2 PH/EN External 4.75300.75Full-Bridge x2 Translator (Step/DIR)External 4.75300.85Full-Bridge x2 Translator (Step/DIR)External835 2.5Full-Bridge x2 Translator (Step/DIR)External835 2.5Full-Bridge x2 SPI,Translator (Step/DIR)External732 1.4Full-Bridge x2 Translator (Step/DIR)External8352Full-Bridge x2 Translator (Step/DIR)External8352Full-Bridge x2 Translator (Step/DIR)External8352Full-Bridge x2 SPI External1250Full-Bridge x2 Translator (Step/DIR)External850 1.5Full-Bridge x2 Parallel External836 1.2Full-Bridge x4 Parallel,PH/EN External836 1.2Full-Bridge x4 SPI External1550 1.5Full-Bridge x2 PH/EN External836 2.4Full-Bridge x4 SPI External950 1.5Full-Bridge x2 Parallel External7.45451Full-Bridge x2 Parallel External550 1.5Full-Bridge x1 SPI,Translator (Step/DIR)External750 1.5Full-Bridge x2 SPI,Translator (Step/DIR)External 3.332 1.4Full-Bridge x2 Translator (Step/DIR)External8352Full-Bridge x2 Translator (Step/DIR)External835 2.5Full-Bridge x2 Translator (Step/DIR)External8352Full-Bridge x2 Translator (Step/DIR)External8351Full-Bridge x2 Parallel External8352Full-Bridge x2 Parallel External8351Full-Bridge x2 Translator (Step/DIR)External8352Full-Bridge x2 Translator (Step/DIR)External1250 1.2Full-Bridge x2 Parallel External632 1.4Full-Bridge x2 SPI,Translator (Step/DIR)External 3.832 1.4Full-Bridge x2 SPI,Translator (Step/DIR)Open Loop 3.532 1.4Full-Bridge x2 Translator (Step/DIR)External840 2.8Full-Bridge x2 Translator (Step/DIR)External840 2.8Full-Bridge x2 Translator (Step/DIR)External840 2.8Full-Bridge x2 Translator (Step/DIR)External8402Full-Bridge x2 Translator (Step/DIR)External8402Full-Bridge x2 Parallel External840 1.6Full-Bridge x4 Parallel External840 1.6Full-Bridge x4 Parallel External840 1.6Full-Bridge x4 Parallel External4181Full-Bridge x4 Parallel External 3.5151Full-Bridge x2封装DFN Consumer,Industrial QFN Consumer,Industrial SOIC Consumer,Industrial SOIC Consumer,Industrial TSSOP Consumer,Industrial TSSOP Consumer,Industrial TSSOP AutomotiveSOIC Consumer,Industrial TSSOP Consumer,Industrial TSSOP Consumer,Industrial TSSOP Consumer,Industrial TSSOP Consumer,Industrial QFN,LQFP Consumer,Industrial QFN Consumer,Industrial DIP,TSSOP Consumer,Industrial QFN Consumer,Industrial QFN Consumer,Industrial SOIC Consumer,Industrial DIP,SOIC Consumer,Industrial TSSOP Consumer,Industrial TSSOP AutomotiveQFN,TSSOP Consumer,Industrial QFN Consumer,Industrial QFN,TSSOP Consumer,Industrial QFN,TSSOP Consumer,Industrial QFN,TSSOP Consumer,Industrial QFN,TSSOP Consumer,Industrial QFN Consumer,Industrial TSSOP Consumer,Industrial TSSOP AutomotiveTSSOP AutomotiveTSSOP AutomotiveTSSOP Consumer,Industrial TSSOP Consumer,Industrial TSSOP Consumer,Industrial QFN,TSSOP Consumer,Industrial QFN Consumer,Industrial QFN Consumer,Industrial QFN Consumer,Industrial QFN Consumer,Industrial,Of QFN Consumer,Industrial TSSOP AutomotiveFull, Half Step Resolution, Single Supply, Sleep ModeInternal PWM Current Control, Single Supply, OCP Protection, Fault Output, Sleep Mode, Parallel Ope Internal PWM Current Control, Full, Step Resolution, Sleep ModeInternal PWM Current Control, Full, Half, 1/4, 1/8 Step Resolution, Sleep Mode, Automatic Mixed Dec Internal PWM Current Control, Full, Half, 1/4, 1/8 Step Resolution, Sleep Mode, Automatic Mixed Dec Internal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, Sleep Mode, Automatic Mixed De Internal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, OCP Protection, Programable Fa Internal PWM Current Control, Full, Half Step Resolution, Sleep Mode, Automatic Mixed DecayInternal PWM Current Control, Full, Half, 1/4, 1/8 Step Resolution, Sleep Mode, Automatic Mixed Dec Internal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, Sleep Mode, Automatic Mixed De Internal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, Sleep Mode, Mixed Decay Internal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, OCP Protection, Sleep Mode, Au Internal PWM Current Control, Full, Half, 1/4 Step Resolution, Automatic Mixed DecayInternal PWM Current Control, Full, Half, 1/4 Step Resolution, Automatic Mixed DecayInternal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, OCP Protection, Sleep Mode, Mi Internal PWM Current Control, Automatic Mixed DecayInternal PWM Current Control, Full, Half, 1/4, 1/8 Step Resolution, OCP Protection, Sleep Mode, 3.3 Internal PWM Current Control, Full, Half Step Resolution, Sleep ModeInternal PWM Current Control, Full, Half, 1/4, 1/8 Step Resolution, Automatic Mixed DecayInternal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, OCP Protection, Programable Fa Internal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, OCP Protection, Programable Fa Internal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, OCP Protection, Sleep Mode, Au Internal PWM Current Control, Full, Half, 1/4, 1/8, 1/16 Step Resolution, Sleep Mode, Automatic Mix Internal PWM Current Control, Full, Half, 1/4, 1/8 Step Resolution, OCP Protection, Sleep Mode, Aut Internal PWM Current Control, Full, Half, 1/4, 1/8 Step Resolution, OCP Protection, Sleep Mode, Aut Internal PWM Current Control, Full, Half, 1/4 Step Resolution, OCP Protection, Sleep Mode, Mixed De Internal PWM Current Control, Full, Half, 1/4 Step Resolution, OCP Protection, Sleep Mode, Mixed De Internal PWM Current Control, Full, Half, 1/4, 1/8, 1/16 Step Resolution, OCP Protection, Sleep Mod Internal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, Sleep Mode, Mixed Decay Internal PWM Current Control, Full Step Resolution, Single Supply, Sleep ModeInternal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, Single Supply, OCP Protection, Integrated Current Sense, Internal PWM Current Control, 50V Transient compatible, Full, Half, 1/4, Internal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, OCP Protection, Fault Output, Internal PWM Current Control, Full, Half, 1/4, 1/8 Step Resolution, OCP Protection, Sleep Mode, Aut Internal PWM Current Control, Full, Half, 1/4, 1/16 Step Resolution, OCP Protection, Sleep Mode, Au Internal PWM Current Control, Full, Half, 1/4, 1/8, 1/16, 1/32 Step Resolution, Single Supply, OCP Internal PWM Current Control, Full, Half, 1/4, 1/8, 1/16, 1/32 Step Resolution, Single Supply, OCP Internal PWM Current Control, Full, Half, 1/4 Step Resolution, Single Supply, OCP Protection, Sleep Internal PWM Current Control, Full, Half, 1/4 Step Resolution, Single Supply, OCP Protection, Sleep Adaptive Percent fast decay, Adjustable off time, Internal PWM Current Control, Full, Half, 1/4 Ste Internal PWM Current Control, Full, Half, 1/4 Step Resolution, Single Supply, OCP Protection, Sleep Internal PWM Current Control, Half step resolution, Single Supply, OCP Protection, Fault Output, SlParallel OperationAutomatic Mixed DecayAutomatic Mixed Decay, Automatic Mixed Decaytion, Programable Fault Output, Sleep Mode, Advanced DiagnosticsMixed DecayAutomatic Mixed Decay, Automatic Mixed Decay, Mixed Decaytion, Sleep Mode, Automatic Mixed Decaytion, Sleep Mode, Mixed Decayion, Sleep Mode, 3.3/5.0V LDO, Mixed Decayixed Decaytion, Programable Fault Output, Sleep Mode, Advanced Diagnosticstion, Programable Fault Output, Sleep Mode, Advanced Diagnosticstion, Sleep Mode, Automatic Mixed DecayMode, Automatic Mixed Decayion, Sleep Mode, Automatic Mixed Decayion, Sleep Mode, Automatic Mixed DecaySleep Mode, Mixed DecaySleep Mode, Mixed Decayrotection, Sleep Mode, Automatic Mixed Decay, Mixed Decayply, OCP Protection, Programmable Fault Output, Sleep Mode, Mixed Decaye, Full, Half, 1/4, 1/16 Step Resolution, OCP Protection, Programable Fault Output, Sleep Mode, Advanced Dia tion, Fault Output, Sleep Mode, Automatic Mixed Decayion, Sleep Mode, Automatic Mixed Decaytion, Sleep Mode, Automatic Mixed DecaySingle Supply, OCP Protection, Fault Output, Sleep Mode, Adaptive Percent Fast DecaySingle Supply, OCP Protection, Fault Output, Sleep Mode, Adaptive Percent Fast DecayCP Protection, Sleep Mode, Mixed DecayCP Protection, Sleep Mode, Mixed DecayFull, Half, 1/4 Step Resolution, Single Supply, OCP Protection, Sleep Mode, Mixed Decay, diagnostic output CP Protection, Sleep Mode, Mixed Decayon, Fault Output, Sleep Modeep Mode, Advanced Diagnostic d Decay, diagnostic output。

A3967中文资料

A3967SLTB微步进驱动器带转换器负载电源电压，V BB ................ 30 V输出电流，I OUT连续.....................±750毫安的*峰值.................................±850毫安的逻辑电源电压，V CC ........... 7.0 V逻辑输入电压范围，V IN（T W> 30纳秒）............. -0.3 V至+7.0 V（T W <30纳秒）................ -1 V至+7.0 V检测电压，V SENSE ............... 0.68 V参考电压，V REF ................ V CC包装功耗，P D ................................. 见第8页工作温度范围，T A ............................. -20°C至+85°C结温，T J ......... +150°C存储温度范围，T S ......................... -55°C至+150°C*输出电流额定值可能是有限的，占空比，环境温度，和热下沉。

在任何条件下，不超过规定的额定电流或结温度为150℃。

A3967SLB是一个完善的微电机驱动器内置逻辑器。

它的设计操作双极步进电机全，半，季，和第八步模式，输出驱动能力30 V和±750毫安性。

A3967SLB包括一个固定关断时间的电流调节器，有能力在慢，快，或混合电流衰减模式。

此电流衰减控制方案以减少可听到的电流噪音，增加步进精确度，并减少功耗。

A3967SLB通过简单的“步进”输入中输入一个脉冲电动机将产生一个步骤（全，半，四分之一，或八分，这取决于两个逻辑输入）。

有没有相位顺序表、高频率控制线或复杂的界面。

A3977步进集成驱动

Product Information A New Microstepping Motor-Driver IC With Integrated Step and Direction Translator InterfaceAbstractA new series of microstepping motor driver integrated circuits with an integrated step and direction translator interface has been developed specifically to drive bipolar stepper motors. These new ICs incorporate several unique design features, including automatic mixed-mode current decay control, PWM current control, synchronous rectification, low rDS(on) power DMOS outputs, full-, half-, quarter-, eighth-, and sixteenth-step operation, HOME output, sleep mode, and an easy-to-implement step and direction interface.decay mode either slow or mixed decay, which eliminates the need for the user to provide additional control lines. In order to satisfy high-end applications that require low power dissipation, the A3977/79 uses low rDS(on) n-channel power DMOS outputs rated at ±2.5 A and 35 V. Another benefit of the DMOS outputs is the ability to implement synchronous rectification. The A3977/79 synchronous- rectification control circuitry will turn on the appropriate output DMOS device during the current decay and effectively short out the body diodes with the low rDS(on) driver. This results in significantly lower power dissipation and eliminates the need for external Schottky diodes in most applications. The A3977 and A3979 are truly next-generation microstepping motor-driver ICs combining low-power dissipation and high-current outputs, efficient current control, and a simpleto-use interface. These design features and their resulting benefits are discussed in further detail below.IntroductionMost microstepping motor drivers require control lines for DACs to set the reference for the PWM current regulator and PHASE inputs for current polarity control. In more sophisticated drivers there are also inputs required for the PWM current-control mode to operate in slow, fast, or mixed decay. These control lines can quickly add up to eight to twelve inputs depending on the DAC resolution and have to be supplied by the system microprocessor. The requirement of this many control inputs, and complex sequencing tables in the microprocessor will add to the cost and complexity of the system. The A3977 and A3979 (figure 1), solve this problem with its simple two-line STEP and DIRECTION interface and an efficient DMOS output, all in one IC. For each transition in the STEP input the driver sequences one microstep. This is ideal for applications where a complex microprocessor controller is unavailable or overburdened. A stepper motor system will have reduced audible noise if the microstepping driver can switch between slow-decay and mixed-decay mode PWM operation. The A3977 and A3979 include circuitry that automatically sets the currentFunctional DescriptionMicrostepping Translator The A3977/79 translator converts the STEP and DIRECTION inputs into the control signals required to sequence the current in each of the two H-bridge outputs for full-, half-, quarter-, eighth- (3977 only), and sixteenth-step (3979 only) microstepping operation of a bipolar stepper motor. At power up or reset the translator sets the DACs and phase current polarity to the initial HOME state conditions and sets the current regulator for both phases to mixed-decay mode (see table 2 and figures 2 through 5 for home-state conditions). When a step command signal (logic Low-toHigh transition of the STEP input) occurs the translator automatically sequences the DACs to the next level and current polarity. Table 2 shows the current sequence table forSTP01-2-AN, Rev. 1LOGIC SUPPLY VDD REF. SUPPLY REF DAC + RC1 PWM LATCH BLANKING 4 STEP MIXED DECAY PWM TIMER SENSE1 UVLO AND FAULT 2V REGULATOR BANDGAPVREGCP2CP1 VCP LOAD SUPPLYCHARGE PUMPVBB1 DMOS H BRIDGEVCPOUT 1A OUT1BMS 1 MS 2 HOME SLEEP VPFD SRCONTROL LOGICGATE DRIVERESETTRANSLATORDIRSENSE1DMOS H BRIDGE VBB2OUT 2A OUT2BENABLE PWM TIMER PFD RC 2 4 PWM LATCH BLANKING MIXED DECAY+ DAC-SENSE2Dwg. FP-050-2Figure 1. A3977 Functional Block DiagramTable 1 MS1 MS2L L H H HMicrostepping ResolutionFull Step (2 phase) Half Step Quarter Step Sixteenth Step (3979) Eighth Step (3977)motor operation (DIRECTION input logic Low). For the reverse operation the DIRECTION input is set to logic High and the translator reverses the sequence through table 2. The DAC outputs are used by the PWM current regulator to set the trip point of the current output of each phase. The (micro)step resolution is set by inputs MS1 and MS2 as shown in table 1.L H L H HSTP01-2-AN, Rev. 1Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; 2Internal PWM Current Control Each H-bridge is controlled by a fixed-off-time PWM current-control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and the current-sense resistor (RS) as shown in figure 6. When the voltage across RS equals the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off either the source drivers (slow-decay mode) or both the source and sink drivers (fast-decay or mixed-decay modes) and the current recirculates as shown in figure 6. During this recirculation the current decreases until the fixed-off time expires. The appropriate output drivers are enabled again, the motor-winding current again increases, and the PWM cycle is repeated. The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITRIPmax = VREF / (8RS ) The DAC output reduces the VREF output to the current-sense comparator in precise steps (see table 2 for % ITRIPmax at each step). ITRIP = (% ITRIPmax / 100) × ITRIPmax The internal PWM current-control circuitry uses a one shot to control the time the driver(s) remain(s) off. The one shot off-time, toff , is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminals to ground. The off time is approximated by: toff = RTCT In addition to the fixed-off time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry. The comparator output is blanked to prevent false over-current detections due to reverse-recovery currents of the clamp diodes, and / or switching transients related to the capacitance of the load. This blanking feature eliminates the low-pass filter between RS and theFigure 6. Current Pathscurrent-sense comparator that is required on most PWM-current regulators. The blank time, tBLANK , can be approximated by: tBLANK = 1900 CT Mixed-Decay Operation Automatic mixed decay is a key feature of the A3977/79. Automatic mixed-decay operation optimizes the current chopping mode in order to achieve the best sinusoidal current waveform for microstepping. Slow decay (figure 7) has the advantage of minimum current ripple. However, when microstepping at higher step rates, slowdecay chopping may fail to properly regulate current on the falling slope of the sine wave when current is decreasing. This is a result of motor BEMF overriding the voltage applied to the motor, forcing the current to increase during the decay period. Figure 8 is a scope plot of motor current that illustrates the limitations of slow-decay chopping. This distortion in the current will cause increased audible noise in the motor.STP01-2-AN, Rev. 1Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; 3Table 2. Step SequencingHome microstep position at Step Angle 45º; DIR = H; 360° = 4 full steps(A3977 (A3979 only) only) Phase 1 Phase 2 Full 1/2 1/4 1/8 1/16 Current Current Step Step Step Step Step Step [% Itripmax] [% Itripmax] Angle # # # # # (%) (%) (º) 1 1 1 1 100.00 0.00 0.0 2 2 2 3 4 1 2 3 5 6 4 7 8 3 5 9 10 6 11 12 2 4 7 13 14 8 15 16 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 0.00 –9.80 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –92.39 –95.69 –98.08 –99.52 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45.0 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90.0 95.6 101.3 106.9 112.5 118.1 123.8 129.4 135.0 140.6 146.3 151.9 157.5 163.1 168.8 174.4 32 16 31 30 4 8 15 29 28 14 27 26 7 13 25 24 12 23 22 3 6 11 21 20 10 19 18 (A3977 (A3979 only) only) Phase 1 Phase 2 Full 1/2 1/4 1/8 1/16 Current Current Step Step Step Step Step Step [% Itripmax] [% Itripmax] Angle # # # # # (%) (%) (º) 5 9 17 33 –100.00 0.00 180.0 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 –99.52 –98.08 –95.69 –92.39 –88.19 –83.15 –77.30 –70.71 –63.44 –55.56 –47.14 –38.27 –29.03 –19.51 –9.80 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 –9.80 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –92.39 –95.69 –98.08 –99.52 –100.00 –99.52 –98.08 –95.69 –92.39 –88.19 –83.15 –77.30 –70.71 –63.44 –55.56 –47.14 –38.27 –29.03 –19.51 –9.80 185.6 191.3 196.9 202.5 208.1 213.8 219.4 225.0 230.6 236.3 241.9 247.5 253.1 258.8 264.4 270.0 275.6 281.3 286.9 292.5 298.1 303.8 309.4 315.0 320.6 326.3 331.9 337.5 343.1 348.8 354.4STP01-2-AN, Rev. 1Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; 4STEP INPUTHOME OUTPUTSLOW DECAYMIXED DECAYSLOW DECAYMIXED DECAY100% 70.7% 38.3%PHASE 1 CURRENTFigure 2. A3977 Eighth-Step (Microstepping) Operation–38.3% –70.7% –100%MS1 = MS2 = H, DIR = HMIXED DECAYSLOW DECAYMIXED DECAYSLOW DECAY100% 70.7% 38.3%PHASE 2 CURRENT–38.3% –70.7% –100%Dwg. WK-004-12STEP INPUTNOTE – Refer to table 2 for complete phase current level at each step.HOME OUTPUTSLOW DECAYMIXED DECAYSLOW DECAYMIXED DECAY100% 70.7% 38.3%PHASE 1 CURRENTFigure 3. A3977 Quarter-Step Operation–38.3% –70.7% –100%MS1 = L, MS2 = H, DIR = HMIXED DECAYSLOW DECAYMIXED DECAYSLOW DECAY100% 70.7% 38.3%PHASE 2 CURRENT–38.3% –70.7% –100%Dwg. WK-004-13STP01-2-AN, Rev. 1Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; 5STEP INPUTHOME OUTPUTMIXED DECAY SLOW DECAY SLOW DECAY SLOW DECAY MIXED DECAY MIXED DECAY SLOW DECAY MIXED DECAY100% 70.7%PHASE 1 CURRENTFigure 4. A3977 Half-Step OperationMS1 = H, MS2 = L, DIR = H–70.7% –100%SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY MIXED DECAY SLOW DECAY100% 70.7%PHASE 2 CURRENT70.7% –100%Dwg. WK-004-14NOTE – Refer to table 2 for complete phase current level at each step.STEP INPUTHOME OUTPUTSLOW DECAY70.7%PHASE 1 CURRENTFigure 5. A3977 Full-Step OperationMS1 = MS2 = L, DIR = H–70.7%SLOW DECAY70.7%PHASE 2 CURRENT–70.7%Dwg. WK-004-15STP01-2-AN, Rev. 1Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; 6I TRIP SLOW DECAY MIXED DECAY FAST DECAY t FDt OFFDwg. WP-031-4Figure 7. Current-Decay WaveformsFast decay (figure 7) solves the current-regulation problem of slow decay. With almost the full supply across the motor winding it has the ability to quickly get the current out of the winding. The disadvantage of fast decay is the increased current ripple, which in turn causes increased motor heating. Mixed decay (figure 7) splits the fixed-off time of the PWM cycle into fast and then slow decay. When the current reaches ITRIP , the device will go into fast-decay mode until the voltage on the RC terminal decays to the voltage on the PFD terminal (VPFD ). The time that the device operates in fast decay is approximated by: tFD = RTCTln( 0.6VDD / VPFD ) After this fast-decay portion (tFD), the device will switch to slowdecay mode for the remainder of the fixed-off time period. The result is low current ripple, but with increased bandwidth to track the ideal sine wave for microstepping. Although mixed decay improves microstepping performance it will still have higher current ripple than slow decay. The best solution is to use a slow decay on the increasing slope of the sine wave and mixed decay on the falling slope of the sine wave output, which the A3977/97 does automatically. When a step-command signal occurs on the STEP input the translator automatically sequences the DACs to the next level. If the new DAC output level is lower than the previous level then the decay mode for that H-bridge will be set by the voltage level on theFigure 8. Slow-Decay Motor CurrentPFD input (fast, slow, or mixed decay). If the new DAC level is equal or higher to the previous level then the decay mode for that H-bridge will be slow decay (see figures 2 thru 5). Figure 9 is a scope plot of the A3977 motor current with slow decay on the rising slope and mixed decay on the falling slope. For comparison, included is a motor current scope plot (figure 10) of the A3977 set to 100% fast decay on the falling slope of the sine wave and slow decay on the rising slope.Figure 9. Mixed-Decay Motor CurrentSTP01-2-AN, Rev. 1Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; 7VBBDRIVE CURRENT RECIRCULATION (SLOW-DECAY MODE) RECIRCULATION (FAST-DECAY MODE)Dwg. EP-006-52RSFigure 10. Fast-Decay Motor CurrentFigure 11. Current Paths with Synchronous Rectification EnabledSynchronous Rectification When a PWM off cycle is triggered, by a bridge disable command or internal fixed-off time cycle, load current will recirculate according to the decay mode selected by the control logic (figure 6). The A3977/79 synchronous rectification (SR) feature will turn on the appropriate DMOS devices during the current decay and effectively short out the body diodes with the low rDS(on) driver (figure 11). In fastdecay synchronous rectification mode the voltage across RS is monitored to prevent reverse conduction. Just before the recirculation current reaches zero all of the DMOS devices are turned off and current flows through the body diodes. In a typical stepper-motor application the motor driver IC is in current-decay (recirculation) mode for a higher percentage of the PWM cycle compared to the on time. This means that most of the power dissipation is a result of the forward-voltage drop of the internal body diode of the power DMOS. This is illustrated by the first order power calculation of output power dissipation in slowdecay recirculation mode with and without synchronous rectification enabled for the A3979.Assume: I = ILOAD = 1.5 A, and rDS(on) = on resistance of the sink DMOS transistors = 0.22 ohm, and VF = forward voltage drop of the sink DMOS body diodes = 1.4 V. With synchronous rectification enabled: PD = I2 ( rDS(on) + rDS(on) ) = 1.52 (0.22 + 0.22) = 0.99 W. With synchronous rectification disabled: PD = ( IVF ) + ( I2 (rDS(on) ) = (1.5 × 1.4) + (1.52 × 0.22) = 2.595 W. The power dissipation reduction by using the A3977’s synchronous rectification feature can eliminate the need for external Schottky diodes in most stepper-motor applications thereby saving the cost and board space for these components.STP01-2-AN, Rev. 1Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; 8Logic Control The A3977/79 SLEEP input is used to minimize power consumption when not in use. This disables much of the internal circuitry including the output DMOS, regulator, and charge pump. Total logic plus motor supply current in sleep mode is <40 μA. Logic Low will put the device into sleep mode; logic High will allow normal operation and starts up the device in the home position. The A3977/79 sleep-mode feature is critical to new designs requiring low off-state current draw. The ENABLE and RESET inputs turn on or off all of the DMOS outputs. Translator inputs are independent of the ENABLE input state so the outputs can be disabled and then stepped to a defined microstep state and then reenabled in this position. The RESET input resets the translator to the home state. The HOME output is a logic output indicator of the initial state of the translator. At power up, the translator is reset to the home state. (See figures 2 through 5 for home state conditions). The HOME output-current level is common to all four microstepping levels in the A3977/79. It can be used as a control input to indicate that the microstepping resolution can be changed at this step without causing a current and therefore torque disturbance to the motor. Protection Circuitry An under-voltage lockout circuit protects the A3977/79 from potential shoot-through currents when the motor supply voltage is applied before the logic supply voltage. All outputs are disabled until the logic supply voltage is above 2.7 V; the control logic is then able to correctly control the state of the outputs. Thermal protection circuitry turns off all the power outputs if the junction temperature exceeds 165°C. As with most integrated thermal shutdown circuits, this is intended only to protect the A3977/79 from failure due to excessive junction temperature and will not necessarily protect the IC from output short circuits. Normal operation is resumed when the junction temperature has decreased by about 15°C.Packaging The A3977/79 is offered in two power packages, a 44-lead plastic power PLCC package (A3977SED) and a 28-lead TSSOP package with exposed thermal pad (A3977SLP and A3979SLP). The 44-lead PLCC has four copper batwing tabs for maximum heat transfer and a thermal resistance of 32°C/W. The 28-lead TSSOP measures only 9.7 mm × 4.4 mm × 0.9 mm and has a thermal resistance of 38°C/W. The TSSOP package is less than 1/4 the size of the PLCC package yet it can achieve close to the same thermal resistance. This is an important advantage in applications that have extreme space constraints.CONCLUSIONAllegro’s new microstepping motor driver ICs, A3977 and A3979, with integrated step and direction translator interface offers several features resulting in application benefits. The A3977/79 features automatic mixed-mode current-decay control, PWM current control, synchronous rectification, low rDS(on) power DMOS outputs, full-, half-, quarter-, eighth-, and sixteenth-step operation, home output, sleep mode, and an easyto-implement step and direction interface. With the A3977 and A3979, Allegro has produced high performance and cost-effective solutions for the next generation of stepper motor drivers.This paper was originally presented at the PCIM 2001 Conference, PowerSystems World, Rosemont, IL on September 10, 2001. Reprinted by permission. Insertion material regarding the A3979 added August 2010.STP01-2-AN, Rev. 1Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; 9。

L297_L298中文资料

Unit 单位
Vs
Supply voltage 电源电压
10
V
Vi
Input signals 输入信号
7
V
Ptot
Total power dissipation 总功率耗散(Tamb = 70℃)
1
W
Tstg, Tj Storage and junction temperature 储存和结温
-40 to + 150 ℃
Ptot
Total Power Dissipation (Tcase=75℃)总功率耗散(Tcase=75℃)ຫໍສະໝຸດ 25WTop
Junction Operating Temperature 结工作温度
–25 to 130 ℃
Tstg,Tj
Storage and Junction Temperature 储存温度
图 9 L298 引脚图
图 10 L298 内部逻辑图 L298 ABSOLUTE MAXIMUM RATINGS 绝对最大额定值：
Symbol 符号
Parameter 参数
单 Value 数值位
VS
Power Supply 电源
50
V
VSS
Logic Supply Voltage 电源电压
7
Sense B
SEN2 分别为两个 H 桥的电流反馈脚，不用时可以直接接地
2;3 4;5
Out 1; Out 2 1Y1、1Y2 输出端
4
6
VS
功率电源电压,此引脚与地必须连接 100nF 电容器
5;7 7;9
Input
1; 1A1、1A2 输入端，TTL 电平兼容

设计报告

简易自动电阻测试仪设计报告摘要：本系统对于不同的量程分别采用恒流源测阻电路、分压法测阻电路和惠更斯桥I/V 变换测阻电路进行电阻测量，充分的发挥出不同电路不同量程的工作特点，并且在软件上进行了校准。

本自动电阻测试仪恒流源以及稳压电路由CA3140、TL431等元器件实现，由ATmega128高速单片机为主控制器，通过其内部自带10位AD 转换器的A/D 转换，对被测电阻两端电压信号进行采样，把连续信号离散化，然后通过LCD 液晶显示屏显示电阻的大小。

该自动测试仪能够较精确的测量1Ω—10M Ω范围内的电阻，其测量误差为±1%，是一个简单易用的电阻测试仪方案。

该系统有，能够自动换档，筛选电阻，并且绘制电阻变化曲线。

实现了测量准确度为±（1%读数＋2 字）的三位有效数字显示的简易自动电阻测试仪。

通过偏置电源的改进提高了精度，又通过软件算法的改进再次提高了精度，对22个范围在0~10M 电阻的反复测试，证明了该系统测量精度的明显改善（见表3）。

关键词：A Tmega128 稳压源恒流源继电器电阻分压原理1、系统方案：1、1方案描述被测电阻 4.7半周克条电阻步进马达模拟放大电路数据采集系统电源图1 系统硬件图简易自动电阻测试仪由5大部分构成：（如图1）1、电源向检测电路提供+-12V ,+5V 模拟电源和+5V 数字电源，模拟地与数字地被光耦隔离。

2、模拟放大电路有三部分构成，第一部分是100Ω档的恒流源测阻电路，第二部分是1K Ω，10K Ω分压法测阻电路，第三部分是1M Ω.档的惠更斯桥I/V 变换测阻电路。

3、步进马达采用信农200步，每步1.8度。

驱动器采用A3977八细分驱动电路。

4、数据采集系统采用ATMEGA128L 单片机。

5、LCD240641、2比较与选择对于电阻的测试方法，一般可以从以下几个方面入手：1、四线测电阻法：为减少接触电阻对测量结果的影响,用一对线通电流(接触电阻对电流的测量无影响),用另一对线测电位(通过的电流很少,接触电阻对电位的影响可忽略)。

A3977

A3977高性能细分驱动器A3977细分驱动器采用高性能专用微步距电脑控制芯片,开放式微电脑可根据用户要求把控制功能设计到驱动器中,组成最小控制系统。

该控制器适合驱动中小型的任何两相或四相混合式步进电机。

由于采用新型的双极性恒流斩波技术，使电机运行精度高, 振动小, 噪声低,运行平稳。

1. 特点:1.1电源电压15～35VDC1.2斩波频率大于35KHZ1.3输入信号与TTL兼容1.4最大驱动电流2.5A/相1.5可驱动两相或四相混合式步进电机1.6双极性恒流斩波方式1.7光电隔离信号输入1.8细分数可选1、2、4、8。

1.9驱动电流可由电位器或开关设定。

1.10外型尺寸：6.6CM*9.4CM*16CM。

1.11重量：______。

2.引脚说明2.1 +35V，GND端为外接直流电源，直流电压范围为+15V～+35V。

2.2 A1，A2端为电机A相。

2.3 B1，B2端为电机B相。

2.4 STEP电机脉冲输入端。

2.5 RW1(SW1)电机电流选择信号端。

2.6 EN驱动器使能信号端。

2.7 DIR电机正反转信号端。

2.8 COM输入信号端地线。

2.9 FAN强制风冷接口3.0 SL休眠控制3.1 +5V外部电源提供(可选)3.电气特性（Tj=25℃）3.1输入电压+15V-+35V，典型值为+24V。

3.2输出相电流0-2.54A可调。

3.3信号逻辑输入最大电流10mA。

3.4下降沿脉冲时间大于5us。

3.5绝缘电阻大于500MΩ；绝缘强度常温1KV，一分钟。

3.6 在电源接通，且不连接插头条件下，电机处于自由状态。

3.7光耦为共阴极。

输入端地线和输出端的地线隔离；使能端为高电平时，电机驱动器使能。

3.8电流选择信号线为高电平时，电机通大电流，为低电平时，电机通小电流，低电流保持锁定状态。

3.9当驱动器长时间以高于2A的电流工作时，建议更换大一点的散热片或安装风扇。

3.10 为可靠起见，电机连线最好使用直径0.75以上的电缆。

全自动贴片机电动飞达电控模块研制

全自动贴片机电动飞达电控模块研制作者：何善印来源：《科技与创新》2017年第11期摘要：简要阐述了电动飞达在贴片机上的应用优势，介绍了电动飞达的机构，重点论述了飞达电控模块方案，对比采用AVR单片机和ARM7控制方案，分析了2种方案的优缺点及其具体应用注意事项，以期为日后的相关工作提供参考。

关键词：电动飞达；AVR单片机；ARM7；电控模块中图分类号：TM910.6 文献标识码：A DOI：10.15913/ki.kjycx.2017.11.112随着电子工业的飞速发展，贴片设备已被广泛应用于大规模电子产品组装生产上，分为自动和手动2种，而全自动贴片机是电子组装行业的发展方向。

供料器FEEDER（飞达）是贴片机的一个重要部件，目前，供料器基本采用的是气动工作方式，就是行业所说的气动飞达。

随着电子产品的发展，要求贴片机向速度更快、精度更高和柔性连接模块化发展。

气动飞达是纯机械结构，各型号间不能替换，速度和精度都不能满足全自动贴片机发展的要求，而电动飞达就是替代气动飞达的产品。

目前，进口高端贴片机使用电动飞达。

1 电动飞达的优点1.1 提高产能电子马达可以微调进给料距离，解决机械飞达使用中不同步贴装的问题，节约了大量的换料和调机时间。

1.2 节约成本使用机械飞达，容易因磁化、气缸不良等原因引发工作误差。

而电动飞达精度高，能够有效解决贴片机贴片零件翻件、侧立、送料不到位、抛料等问题。

1.3 通用性电动飞达用单片机控制，可以通过调整工作参数用于不同型号的贴片机上。

1.4 高安全性机械飞达加装保护装置，结构复杂、难实现，而电动飞达是电气控制的，容易加装保护装置，能够避免因外部问题而造成的设备维修损失。

1.5 人机对话电动飞达可以实时监控每支飞达的贴装数量，可作为设备数据库分析使用。

2 电动飞达的结构2.1 飞达的主要结构飞达包括变速皮带、马达、齿轮、卷取齿轮、加块和控制电路板等部分。

2.2 飞达端口说明飞达采用14Pin易插式插头与机台连接，端口通讯协议如下：引脚1为（24 V）外部供电24 V；引脚2为（NC）空脚；引脚3为（GND）外部供电0 V；引脚4为（NC）空脚；引脚5为（CHECK）飞达状态指示，上电默认低电平，当自动吐料几个后至为高电平；引脚6为（WRITE）写飞达数据控制，高电平有效，与PLUS同时为高电平时，可修改飞达内部数据；引脚7为（PLUS）进给脉冲，高电平有效；引脚8为（RUN）运行指示，飞达运转中输出低电平，待机时高电平；引脚9为（ALM）故障输出，飞达有故障时输出低电平；引脚10为（CONT）飞达插入确认，连接飞达插入保护开关，插入后与GND短接；引脚11为（GND）外部供电0 V；引脚12为（TXD）串口数据发送，TTL电平，逻辑反向；引脚13为（RXD）串口数据接收，TTL电平，逻辑反向；引脚14为（FG）地线，连接外壳。

A3977SED-T中文资料

元器件交易网
A3977
Microstepping DMOS Driver with Translator
Features and Benefits
▪ ±2.5 A, 35 V output rating ▪ Low rDS(on) outputs, 0.45 Ω source, 0.36 Ω sink typical ▪ Automatic current decay mode detection/selection ▪ 3.0 to 5.5 V logic supply voltage range ▪ Mixed, fast, and slow current decay modes ▪ Home output ▪ Synchronous rectification for low power dissipation ▪ Internal UVLO and thermal shutdown circuitry ▪ Crossover-current protection
Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Range K Range S
MIXED DECAY
4
PWM TIMER
DMOS H BRIDGE
PWM TIMER
4
PWM LATCH
BLANKING
MIXED DECAY

两相混合式步进电机及其驱动技术

▪ 微步距方式旳步距角更小，将使电机运营愈加平稳。 12
▪ 一般称单四拍和双四拍工作方式为整步距方式；单、双八拍工作方式为半步距方式。
▪ 步进电机中定子磁场和转子磁场旳相互作用产生转矩：
▪ 定子磁势IW（安匝），I为相电流，W为绕组匝数。
▪ 转子磁势是由转子磁钢产生旳，它是一种常数。 ▪ 所以当定子线圈匝数、转子磁钢磁性能及定、
ia
AB
BA AB BA
t
ib
t 图6-8
▪ 整步运营时，绕组电流每90°电角度转过一种整步距。
▪ 四细分时电流电角度为 90/4=22.5 °。以22.5°旳角
度递增从0°到360°共有16个电角度；所相应旳cos和
sin值求出并整量化后作成数据表放在存储器中。
31
32
D/A转换器
T1
T2
D1 D2
A0
u D0
B
A1
u D1
A
A2 A3
u D2
B
u D3
A
A4
A4接地时，可选通00H~0FH之间旳十六个地址。该地址空间存
储了循环旳单、双八拍运动方式旳数据表 A4接5V时，可选通10H~1FH 之间旳十六个地址。该地址空间存储了循环旳双四拍运营方式2旳3 数据表。
3）功率放大—单电压驱动方式
T1
Us
T2
D1
D2
电流放大
ia A BAB
t
uA
T3
A
A
T4
uA
ib
D3
D4
t
Vi －
Vg
＋
单稳
图6-6
a
b
c
i
d

雕刻机使用说明

3040雕刻机使用说明2，本机是针对旋转轴比速1:6首先装好MACH3软件,根据以下说明设好参数,然后装上电气箱插上电源.数据线和USB，如果软件装对,打开软件主轴不转,为正确.因为数据受控制,如果打开软件主轴会转说明参数没设对或软件未装好.请客户认真仔细看以下说明.首先要看一下光盘的雕刻机接线图，步进电机从上往下最上是Z轴，中间是X轴，最下是Y轴（在这里特别要说明，长期使用要经常检验，步进电机线不能短路，控制板电源线不要接反，或路板。

机床发货时线都接好的，所以客户只要插上就可以用了,要6孔对6针，插对插正）新手使用时特注意：1.收到雕刻机后先看光盘资料。

2.然后需要一台25针的台式电脑，25针直接从主板上出来的台式机，先装MACH3软件，注意装时有360或杀毒软件的，先把360或杀毒软件的删了，再装MACH3,MACH3具体安装看下面说明。

3.装好后电脑重起，开机过程，先开电脑，后开软件，最后开电气箱，关机刚好相反。

先关电气箱后关软件，最后关电脑。

4.参数全部设好后，新手试机，看是否装对，能手动控制XYZ和主轴，说明装对了，先要学会手动操作，然后学会自动操，手动操作时注意这二处是绿灯才可进行5.平时加工时主轴开到最高速8000转加工，别低速加工。

6,特别注意点，电气箱通电后不要拔插步进电机接头，只有关机后才可以7.习惯，晚上不加工产品睡前把电气箱关了，哈哈，这是我自已的习惯8,XYZ的步进电机都是可以改变方向的，下面参数中有说到，这里我说一下，电机输出那里，674523后面的钩和叉就是改变方向的，很多软件编程出来的Z轴方向刚好相反，客户在用时首先要确认Z轴方向正确了在进行，然后雕刻字时比如阴阳字雕刻也是改变步进电机方向得到的。

注意事项：1.机器使用前应该在滑道光轴和丝杠上滴一些机油，减少磨损延长磨损件的使用寿命。

2.由于该机器是电脑控制机械设备，电机都具有一定的力矩，具有伤害性。

使用时注意安全，刀具要夹紧。

基于AISG2

基于AISG2.0协议的电调天线远程控制单元的设计实现放大器放大器放大器放大器等和射频信号相关的ALD设备。

本系统中的AISG通信接口电路。

由于天线一般都分布在相对较高而且空旷的地带，因而RCU通信接口的防雷功能必不可少。

本通信接口电路的防雷部分包括气体放电管、PTC和TVS三部分。

气体放电管构成第一道防雷保护，PTC和TVS作为第二道防线，进一步保证了通信接口的防雷性能。

考虑到所有的RET控制器都是挂在空中，最后通过基站单点接到大地，不存在大地电位差，因而采用了非隔离的方案。

2.2 电机控制模块电机控制驱动模块的核心是Allegro公司的步进电机驱动芯片A3977。

该芯片具有1/2、1/4及1/8等微步模式。

本系统中通过软件配置使MS1为高电平、MS2为低电平，电机工作在半步模式，MCU每发400个脉冲电机转动一圈。

A3977输出驱动器容量为35 V、2.5 A，内部包括一个固定停机时间电流稳压器，该稳压器可在低、快或混合衰减模式下工作，从而可以有效降低电机噪音，增加步进精确度并减少功率耗散。

2.3 存储模块存储模块主要包括天线相关的参数存储和RCU固件存储。

天线参数存储采用铁电存储器FM24LC16，其中包括产品序列号、天线参数、天线配置数据和移相器配置数据等。

选用铁电存储器的主要原因是：AISG协议中规定，RCU收到基站的命令后，必须在10 ms之内发出回应帧，否则就认为通信超时，这就要求向存储器中写入天线参数的命令必须在10 ms内完成；考虑到执行程序的时间消耗，在天线数据较多的情况下，普通的EEPROM无法满足要求；铁电存储器相比于EEPROM写入速度快，写入过程无需等待，可以满足这一要求。

RCU固件存储则采用了μPSD单片机的内部Flash。

利用μPSD单片机内部特有的Flash结构，将正在执行的固件和更新的固件都存储在单片机的片内Flash中，从而省去了外部存储器，既节省了BOM成本，又提高了产品的可靠性和安全性。

A3972微步电机驱动器说明书

A3972Selection GuidePart Number PackingA3972SB-T15 pieces/tubeAbsolute Maximum RatingsCharacteristic Symbol Notes Rating Units Load Supply Voltage V BB50V Output Current*I OUT±1.5A Logic Supply Voltage V DD7.0V Logic Input Voltage Range V IN–0.3 to V DD + 0.3V Reference Voltage V REF3V Sense Voltage (DC)V S500mV Package Power Dissipation P D 3.1W Operating Ambient Temperature T A Range S–20 to 85ºC Junction Temperature T J150ºC Storage Temperature T stg–55 to 150ºC *Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the speciﬁ ed current rating or a junction temperature of 150°C.FUNCTIONAL BLOCK DIAGRAMELECTRICAL CHARACTERISTICS at T A = +25°C, V BB = 50 V, V DD = 5.0 V, V S = 0.5 V,f PWM < 50 kHz (unless otherwise noted).LimitsMax.Typ.UnitsConditions Min.Characteristic SymbolTestLoad Supply Voltage Range V BB Operating 15 — 50 VDuring sleep mode 0 — 50 VLogic Supply Voltage Range V DD Operating 4.5 5.0 5.5 VLoad Supply Current I BB f PWM < 50 kHz — — 8.0 mAOperating, outputs disabled — — 6.0 mASleep or idle mode — — 20 μALogic Supply Current I DD f PWM < 50 kHz — — 12 mA10—mA—OutputsoffIdle mode (D0 = 1, D18 = 0) — — 1.5 mASleep mode — — 100 μAOutput DriversμAOutput Leakage Current I DSS V OUT = V BB —50<1.0V OUT = 0 V — <-1.0 -50 μAOutput On Resistance r DS(on)Source driver, I OUT = –1.5 A — 0.5 0.55 ΩSink driver, I OUT = 1.5 A — 0.315 0.35 ΩBody Diode Forward Voltage V F Source diode, I F = 1.5 A — — 1.2 VSink diode, I F = 1.5 A — — 1.2 VControl LogicLogic Input Voltage V IN(1) 2.0 — — VV IN(0)— — 0.8 VLogic Input Current I IN(1)V IN = 2.0 V — <1.0 20 μAI IN(0)V IN = 0.8 V — <-2.0 -20 μAOSC Input Frequency Range f OSC Divide by one 2.5 — 6.0 MHz(D0 =1, D13 = 0, D14 = 1)OSC Input Duty Cycle — 40 — 60 %Input Hysterisis ΔV IN0.20 — 0.40 Vcontinued next page ...ELECTRICAL CHARACTERISTICS at T A = +25°C, V BB = 50 V, V DD = 5.0 V, V S = 0.5 V,f PWM < 50 kHz (unless otherwise noted).LimitsMax.Typ.UnitsTestConditions Min.Characteristics SymbolControl Logic (continued)Internal Oscillator f OSC OSC shorted to ground 3.0 4.0 5.0 MHzR OSC = 51 kΩ 3.4 4.0 4.6 MHzDAC Accuracy (total error) E T Relative to DAC reference buffer — ±1/2 — LSBoutput, D0 = 0, D17 = 0Reference Input Voltage Range V REF(EXT) 0.5 — 2.6 V—mV±10 Reference Buffer Offset V OS —Reference Divider Ratio V REF/V S D0 = 0, D18 = 0 — 8.0 — —D0 = 0, D18 = 1 — 4.0 — —Reference Input Current I REF V REF = 2.0 V — — ±0.5 μAInternal Reference Voltage V REF(INT) 1.94 2.0 2.06 VGain (G m) Error (note 3) E G D0 = 0, D17 = 0,D18 = 0, DAC = 63 — 0 ±6 %D18 = 0, DAC = 31 — 0 ±9 %D18 = 1, DAC = 63 — 0 ±6 %D18 = 1, DAC = 15 — 0 ±10 %Comparator Input Offset Voltage V IO V REF = 0 V — ±5.0 — mVPropagation Delay Times t pd50% to 90%:PWM change to source on 500 800 1200 nsPWM change to source off 50 150 350 nsPWM change to sink on 500 800 1200 nsPWM change to sink off 50 150 350 nsCrossover Dead Time t dt300 700 900 nsThermal Shutdown Temperature T J— 165 — °CThermal Shutdown Hysteresis ΔT J— 15 — °C4.2V4.45UVLO Enable Threshold V UVLO IncreasingV DD 3.9UVLO Hysteresis ΔV UVLO0.05 0.10 — VNOTES: 1. Typical Data is for design information only.2. Negative current is deﬁ ned as coming out of (sourcing) the speciﬁ ed device terminal.3. E G = [(V REF/Range) – V S]/(V REF/Range).Serial Interface. The A3972SB is controlled via a 3-wire (clock, data, strobe) serial port. The programmable functions allow maximum ﬂ exibility in con ﬁ guring the PWM to the motor drive requirements. The serial data is written as two19-bit words: 1 bit to select the word and 18 bits of data. The serial data is clocked in starting with D18.Word 0 Bit AssignmentsBit Function D0 Word select = 0 D1 Bridge 1, DAC, LSB D2 Bridge 1, DAC, bit 2 D3 Bridge 1, DAC, bit 3 D4 Bridge 1, DAC, bit 4 D5 Bridge 1, DAC, bit 5 D6 Bridge 1, DAC, MSB D7 Bridge 2, DAC, LSB D8 Bridge 2, DAC, bit 2 D9 Bridge 2, DAC, bit 3 D10 Bridge 2, DAC, bit 4 D11 Bridge 2, DAC, bit 5 D12 Bridge 2, DAC, MSB D13 Bridge 1 phase D14 Bridge 2 phase D15 Bridge 1 mode D16 Bridge 2 mode D17 REF select D18 Range selectD1 – D6 Bridge 1 Linear DAC. Six-bit word sets desired current level for Bridge 1. Setting all six bits to zero disables Bridge 1, with all drivers off (See current regulation section of functional description).D7 – D12 Bridge 2 Linear DAC. Six-bit word sets desired current level for Bridge 2. Setting all six bits to zero disables Bridge 2, with all drivers off (See current regulation section of functional description).FUNCTIONAL DESCRIPTIONcontinued next page ...D13 Bridge 1 Phase. This bit controls the direction of output current for Load 1.D13 OUT 1A OUT 1B0 L H 1 H LD14 Bridge 2 Phase. This bit controls the direction of output current for Load 2.D14 OUT 2A OUT 2B 0 L H1 H L D15 Bridge 1 Mode.D15 Mode 0 Mixed-decay 1 Slow-decay D16 Bridge 2 Mode.D16 Mode 0 Mixed-decay 1 Slow-decayD17 REF Select. This bit determines the reference input for the 6-bit linear DACs. D17 Reference Voltage 0 Internal 2 V1External (3 V max)D18 G m Range Select. This bit determines the scaling factor (4 or 8) used.D18 Divider Load Current 0 1/8 I TRIP = V DAC /8R S 1 1/4 I TRIP = V DAC /4R SFor example, with a master oscillator frequency of 4 MHz, the ﬁ xed off-time will be adjustable from 1.75 μs to 63.75 μs in increments of 2 μs.D8 – D11 Fast Decay Time. These four bits set the fast-decay portion of ﬁ xed off-time for the internal PWM control circuitry. The fast-decay portion is de ﬁ ned by:t fd = [(1 + N) x 8/f OSC ] - 1/f OSC where N = 0 (15)For example, with an oscillator frequency of 4 MHz, the fast-decay time will be adjustable from 1.75 μs to 31.75 μs in incre-ments of 2 μs. For t fd > t off , the device will effectively operate in fast-decay mode.D12 – D13 Oscillator Control. A 4 MHz internal oscillator is used for the timing functions and charge-pump clock. If more precise control is required, an external oscillator can be input to the OSC terminal. To accommodate a wider range of system clocks, an internal divider is provided to generate the desired MO frequency according to the following table: D13 D12 OSC 0 0 4 MHz internal clock 0 1 External clock 1 0 External clock/2 1 1 External clock/4D14 – D15 Synchronous Recti ﬁ cation.D15 D14 Synchronous Recti ﬁ er 0 0 Active 0 1 Disabled 1 0 Passive 1 1 Low side only The different modes of operation are in the synchronous recti ﬁ -cation section of the functional description.D16, D17. These bits are reserved for testing and should be programmed to zero during normal operation.D18 Idle Mode. The device can be placed in a low power “idle” mode by writing a “0” to D18. The outputs will be dis-abled, the charge pump will be turned off, and the device will draw a lower load supply currrent. The undervoltage monitor circuit will remain active. D18 should be programmed high for 1 ms before attempting to enable any output driver.Word 1 Bit AssignmentsBit Function D0 Word select = 1D1 Blank-time LSBD2 Blank-time MSB D3 Off-time LSB D4 Off-time bit 1 D5 Off-time bit 2 D6 Off-time bit 3D7 Off-time MSB D8 Fast-decay time LSB D9 Fast-decay time bit 1 D10 Fast-decay time bit 2 D11 Fast-decay time MSB D12 C0 oscillator control D13 C1 oscillator control D14 SR control bit 1 D15 SR control bit 2 D16 Reserved for testing D17 Reserved for testing D18 Idle modeD1 – D2 Blank Time. These two bits set the blank time for the current-sense comparator. When a source driver turns on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from er-roneously resetting the source-enable latch, the sense comparator is blanked. The blank timer runs after the off-time counter to provide the programmable blanking function. The blank timer is reset when PHASE is changed. D2 D1 Time 0 0 4/f OSC 0 1 6/f OSC 1 0 8/f OSC 1 1 12/f OSCD3 – D7 Fixed Off Time. These ﬁ ve bits set the ﬁ xed off-time for the internal PWM control circuitry. Fixed off-time is de ﬁ ned by:t off = [(1 + N) x 8/f OSC ] - 1/f OSCwhere N = 0 (31)FUNCTIONAL DESCRIPTION (continued)continued next page ...V REG. This internally generated supply voltage is used to run the sink-side DMOS outputs. V REG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. The V REG pin should be decoupled with a 0.22 μF capacitor to ground.Current Regulation. The reference voltage can be set by ana-log input to the REF terminal, or via the internal 2 V precision reference. The choice of reference voltage and sense resistor set the maximum trip current.I TRIPMAX = V REF/(Range x R S) Microstepping current levels are set according to the following equations:I TRIP = V DAC/(Range x R S)V DAC = [(1 + DAC) x V REF]/64where DAC input code equals 1 to 63 and Range is 4 or 8 as selected by Word 0, D18. Programming the DAC input code to zero disables the bridge, and results in minimum load current. PWM Timer Function. The PWM timer is programmable via the serial port to provide ﬁ xed off-time PWM signals to the con-trol block. In mixed-decay mode, the ﬁ rst portion of the off time operates in fast decay, until the fast-decay time count is reached, followed by slow decay for the rest of the ﬁ xed off-time period. If the fast-decay time is set longer than the off-time, the device effectively operates in fast-decay mode.Oscillator. The PWM timer is based on an oscillator input, typically 4 MHz. The A3972SB can be conﬁ gured to select ei-ther a 4 MHz internal oscillator or, if more precision is required, an external clock can be connected to the OSC terminal. If an external clock is used, three internal divider choices are select-able via the serial port to allow ﬂ exibility in choosing f OSC, based on available system clocks. If the internal oscillator op-tion is used, the absolute accuracy is dependent on the process variation of resistance and capacitance. A precision resistor can be connected from the OSC terminal to V DD to further improve the tolerance. The frequency will be:f OSC = 204 x 109/R OSCIf the internal oscillator is used without the external resistor, the OSC terminal should be connected to ground.Sleep Mode. The input terminal SLEEP is dedicated to putting the device into a minimum current draw mode. When pulled low, the serial port will be reset to all zeros and all circuits will be disabled.Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on V CP or V REG, the outputs of the device are disabled until the fault condition is removed. At power up, or in the event of low V DD, the UVLO circuit disables the drivers and resets the data in the serial port to zeros. Synchronous Rectiﬁ cation. When a PWM off-cycle is triggered, either by a bridge disable command or internal ﬁ xed off-time cycle, the load current will recirculate according tothe decay mode selected by the control logic. The A3972SB synchronous rectiﬁ cation feature will turn on the appropriate MOSFET(s) during the current decay and effectively short out the body diodes with the low r DS(on) driver. This will lower power dissipation signiﬁ cantly and can eliminate the need for external Schottky diodes for most applications.Four distinct modes of operation can be conﬁ gured with the two serial port control bits:1. Active Mode. Prevents reversal of load current by turningoff synchronous rectiﬁ cation when a zero current level isdetected.2. Passive Mode. Allows reversal of current but will turnoff the synchronous rectiﬁ er circuit if the load current inver-sion ramps up to the current limit.3. Disabled. MOSFET switching will not occur during loadrecirculation. This setting would only be used with fourexternal clamp diodes per bridge.4. Low Side Only. The low-side MOSFETs will switch onduring the off time to short out the current path throughthe MOSFET body diode. With this setting, the high-sideMOSFETs will not synchronously rectify so four externaldiodes from output to supply are recommended. This mode is intended for use with high-power applications where itis desired to save the expense of two external diodes perbridge. In this mode, the sink-side MOSFETs are chopped during the PWM off time. In all other cases, the source-side MOSFETs are chopped in response to a PWM off com-mand.continued next page ...FUNCTIONAL DESCRIPTION (continued)Current Sensing.To minimize inaccuracies in sensing the IPEAKcurrent level caused by ground-trace IR drops, the senseresistor should have an independent ground return to the ground terminal of the device. For low-value sense resistors, the IR drops in the sense resistor’s PCB traces can be signi ﬁ cant and should be taken into account. The use of sockets should beavoided as they can introduce variation in R S due to their contact resistance.Thermal Protection. Circuitry turns off all drivers when the junction temperature reaches 165°C typically. It is intended only to protect the device from failures due to excessive junction temperature and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C.Serial Port Write Timing Operation. Data is clocked into a shift register on the rising edge of CLOCK signal. Normally, STROBE will be held high, and only will be brought low to initiate a write cycle. The data is written MSB ﬁ rst, followed by the word-select bit. Refer to serial port diagram for timing requirements.APPLICATIONS INFORMATIONA. Minimum Data Setup Time .......................................15 nsB. Minimum Data Hold Time ........................................10 nsC. Minimum Setup Strobe to Clock Rising Edge ........150 nsD. Minimum Clock High Pulse Width ...........................40 nsE. Minimum Clock Low Pulse Width ............................40 nsF. Minimum Setup Clock Rising Edge to Strobe ...........50 ns G . Minimum Strobe Pulse Width .................................150 ns H. Minimum Setup Sleep to Strobe Falling ...................50 μsLayout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. The ground side of R S should have an individual path to the ground pin(s) of the driver. This path should be as short as physically possible and should not have any other components connected to it. The load supply pin, V BB , should be decoupled with an electrolytic capacitor (>47 μF is recommended) placed as close to the driveras is possible.Dwg. WP-038-1B Package, 24-Pin DIPCopyright ©2000-2007, Allegro MicroSystems, Inc.The products described here are manufactured under one or more U.S. patents or U.S. patents pending.Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de p ar t ures from the detail spec i f i c a t ions as may be required to per-mit improvements in the per f or m ance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system.The in f or m a t ion in c lud e d herein is believed to be ac c u r ate and reliable. How e v e r, Allegro MicroSystems, Inc. assumes no re s pon s i b il i t y for its use; nor for any in f ringe m ent of patents or other rights of third parties which may result from its use.For the latest version of this document, visit our website:。

基于A3977--步进电机驱动电路设计

摘要随着微步进电机应用的日益广泛，其驱动电路的发展也相当迅速，各类控制芯片的功能越来越丰富，操作也越来越简便。

A3977 是一种新近开发出来、专门用于双极型步进电机的微步进电机驱动集成电路。

本文的主要内容是以A3977SED芯片为核心，设计一块步进电机驱动电路，利用protel软件设计出原理图及PCB板，最后制作成实物。

关键词：步进电机驱动 A3977 DMOS 转换目录摘要 (1)目录 (2)第一章概述 (3)1.1 步进电机概述 (3)1.2 步进电机驱动技术概述 (3)第二章驱动电路设计 (5)2.1 总体电路 (5)2.2芯片概述 (5)2.2.1 芯片特点 (6)2.2.2外形结构 (6)2.2.3方框图 (7)2.2.4引脚定义及说明 (7)第3章电路图设计 (12)3.1 原理图设计 (12)3.2 PCB板设计 (13)3.3 实验结果 (14)第4章总结+展望 (16)第一章概述1.1 步进电机概述步进电机又称脉冲电机或阶跃电机，国外一般称为Stepper motor、Stepping motor或Stepper 等。

它是一种用电脉冲信号进行控制，并将电脉冲信号转化成相应的角位移或线位移的控制电机。

它可以看作是一种特殊运行方式的同步电动机，由专用电源供给电脉冲，每输入一个脉冲，步进电机就移动一步。

这种电动机的运动形式与普通迅速旋转的电动机有一定的差别，它是步进式运动的，所以称为步进电动机。

又因其绕组上所加的电源式脉冲电压，有时也称它为脉冲电动机。

步进电机受脉冲信号控制，它的直线位移量或角位移量与电脉冲数成正比，所以电机的线速度或转速也与脉冲频率成正比，通过改变脉冲频率的高低就可以在很大的范围内调节电机的转速，并能快速起动、制动和反转。

所以，电机步距角和转速大小都不受电压波动和负载变化的影响，也不受环境条件如温度、气压、冲击和振动等影响。

它每转一周都有固定的步数，在不丢步的情况下运行，其步距误差不会长期积累。

自动窗帘说明

电动窗帘说明1、步进电机控制IC选用A3977ED，A3977ED有如下特点：A3977 是完整的微步电动机驱动器，具有内置转换器。

该产品设计可在全、半、1/4 及1/8 步进模式时操作双极步进电动机，输出驱动器可为35 V 及±2.5 A。

A3977 包括一个固定停机时间电流稳压器，该稳压器可在慢、快或混合衰减模式下工作。

此电流衰减控制方案能减少可听到的电动机噪音、增加步进精确度并减少功率耗散。

转换器是A3977的关键。

只需在一个步进输入Step一个脉冲即可驱动电动机一个步进（两个逻辑输入MS1、MS2确定是否处于全、半、1/4 或1/8 步进模式）。

该芯片中没有相位顺序表、高频率控制行或复杂的操作。

A3977尤其适用于复杂的的应用。

内部同步整流控制电路用来改善脉宽调制(PWM) 操作时的功率消耗。

内部电流保护包括滞后过热关机、欠压锁定(UVLO) 及交叉电流保护。

不需要特别的加电排序。

外形图接线图3、光敏电阻光敏电阻又称光导管，常用的制作材料为硫化镉，另外还有硒、硫化铝、硫化铅和硫化铋等材料。

这些制作材料具有在特定波长的光照射下，其阻值迅速减小的特性。

这是由于光照产生的载流子都参与导电，在外加电场的作用下作漂移运动，电子奔向电源的正极，空穴奔向电源的负极，从而使光敏电阻器的阻值迅速下降。

电路中选用深圳龙信达科技生产的CdS光敏电阻系列中的LXD25549光敏电阻外形尺寸4、干簧管开关选择干簧管是一种磁敏的特殊开关。

它通常由两个或三个既导磁又导电材料做成的簧片触点，被封装在充有惰性气体(如氮、氦等)或真空的玻璃管里，玻璃管内管内平行封装的簧片端部重叠，并留有一定间隙或相互接触以构成开关的常开或常闭接点。

当永久磁铁靠近干簧管时，或者由绕在干簧管上面的线圈通电后形成磁场使簧片磁化时，簧片的接点就会感应出极性相反的磁极。

由于磁极极性相反而相互吸引，当吸引的磁力超过簧片的抗力时，分开的接点便会吸合;当磁力减小到一定值时，在簧片抗力的作用下接点又恢复到初始状态。

A3977SLP中文资料

元器件交易网3977A3977xED(PLCC)LOAD SUPPLY 1 SENSE 1 ENABLE OUT 1A HOME GND GND GND SLEEP OUT 1BMICROSTEPPING DMOS DRIVER WITH TRANSLATORThe A3977xED and A3977xLP are complete microstepping motor drivers with built-in translator. They are designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 35 V and ±2.5 A. The A3977 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This currentdecay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A3977. By simply inputting one pulse on the STEP input the motor will take one step (full, half, quarter, or eighth depending on two logic inputs). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The A3977 interface is an ideal fit for applications where a complex µP is unavailable or over-burdened. Internal synchronous-rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, under-voltage lockout (UVLO) and crossover-current protection. Special power-up sequencing is not required. The A3977 is supplied in a choice of two power packages, a 44-pin plastic PLCC with copper batwing tabs (suffix ED), and a thin (<1.2 mm), 28pin TSSOP with an exposed thermal pad (suffix LP). The SLP package is available in a lead-free version (100% matte tin leadframe).Data Sheet 26184.22DDIR6543214443 VBB1424140NC NC PFD7CHARGE PUMP39 NC 38 CP2 37 CP1 36 VCP 35 GND 34 GND 33 GND REG 32 VREG8 9 PWM TIMERRC1 10 GND 11 GND 12 GND 13 REF 14 RC2 15 LOGIC SUPPLY 16 NC 17 VBB2 18OUT 2A TRANSLATOR & CONTROL LOGIC÷831 STEP VDD 30 NC 29 NC19MS 220MS121SENSE 222GND23GND24GND25SUPPLY LOAD 226SR27RESET28OUT 2BDwg. PP-075-1ABSOLUTE MAXIMUM RATINGS at TA = +25°CLoad Supply Voltage, VBB ............. 35 V Output Current, IOUT .................. ±2.5 A* Logic Supply Voltage, VDD ........... 7.0 V Logic Input Voltage Range, VIN (tw >30 ns) ..... -0.3 V to VDD + 0.3 V (tw <30 ns) ........... -1 V to VDD + 1 V Sense Voltage, VSENSE ................. 0.5 V Reference Voltage, VREF ................ VDD Package Power Dissipation, PD ................................. See page 3 Operating Temperature Range, TA (A3977Kx) ............ -40°C to +125°C (A3977Sx) .............. -20°C to +85°C Junction Temperature, TJ ......... +150°C Storage Temperature Range, TS ......................... -55°C to +150°C* Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C.FEATURES■ ■ ■ ■ ■ ■ ■ ■ ■ ±2.5 A, 35 V Output Rating Low rDS(on) Outputs, 0.45 Ω Source, 0.36 Ω Sink Typical Automatic Current Decay Mode Detection/Selection 3.0 V to 5.5 V Logic Supply Voltage Range Mixed, Fast, and Slow Current Decay Modes Home Output Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal Shutdown Circuitry Crossover-Current ProtectionAlways order by complete part number:Part Number A3977KED A3977KLP A3977SED A3977SED-T A3977SLP A3977SLP-T Package 44-pin PLCC 28-pin TSSOP 44-pin PLCC 44-pin PLCC; Lead-free 28-pin TSSOP 28-pin TSSOP; Lead-free元器件交易网3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATORFUNCTIONAL BLOCK DIAGRAMLOGIC SUPPLY VDD REF. SUPPLY REF UVLO AND FAULT 2V REGULATOR BANDGAPVREGCP2 CHARGE PUMPCP1 VCPLOAD SUPPLYVBB1DMOS H BRIDGEDAC + -SENSE1VCPRC1PWM LATCH BLANKING MIXED DECAYOUT1A OUT1B4 STEPPWM TIMERMS1 MS2 HOME SLEEP VPFD SRCONTROL LOGICGATE DRIVERESETTRANSLATORDIRSENSE1DMOS H BRIDGEVBB2OUT2A OUT2BENABLE PWM TIMER PFD 4PWM LATCH BLANKING MIXED DECAYRC2 DAC+-SENSE2Dwg. FP-050-22115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2002, 2003 Allegro MicroSystems, Inc.元器件交易网3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATORA3977xLPALLOWABLE PACKAGE POWER DISSIPATION IN WATTS(TSSOP)SENSE1 HOME DIR OUT1A PFD RC1 AGND REF RC2 LOGIC SUPPLY OUT2A MS2 MS1 SENSE2 1 2 3 4 VBB1 28 27 26 25 LOAD SUPPLY1 SLEEP ENABLE OUT1B CP2 CP1 VCP PGND VREG STEP OUT2B RESET SR LOAD SUPPLY2Dwg. PP-0755.0SUFFIX '–LP', RθJA = 28°C/W*4.0SUFFIX '–ED', RθJA = 32°C/W†PWM TIMERCHARGE PUMP5 6 7 8 9 10 11 12 13 1424 23 22 213.0SUFFIX '–LP', RθJA = 33°C/W†TRANSLATOR & CONTROL LOGIC2.0÷8REG20 19 18 17 16VDD1.0SUFFIX 'S–' SUFFIX 'K–'0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150VBB215Dwg. GP-018-2APackage Thermal Resistance, RθJA A3977xLP ......................... 28°C/W* A3977xED ........................ 32°C/W† A3977xLP ......................... 33°C/W†* Measured on JEDEC standard “High-K” four-layer board. † Measured on typical two-sided PCB with three square inches (1935 mm2) copper ground area.Table 1. Microstep Resolution Truth Table MS1 L H L H MS2 L L H H Resolution Full step (2 phase) Half step Quarter step Eighth step3元器件交易网3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATORELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Limits Characteristic Output Drivers Load Supply Voltage Range VBB Operating During sleep mode Output Leakage Current IDSS VOUT = VBB VOUT = 0 V Output On Resistance rDS(on) Source driver, IOUT = -2.5 A Sink driver, IOUT = 2.5 A Body Diode Forward Voltage VF Source diode, IF = -2.5 A Sink diode, IF = 2.5 A Motor Supply Current IBB fPWM < 50 kHz Operating, outputs disabled Sleep mode Control Logic Logic Supply Voltage Range Logic Input Voltage VDD VIN(1) VIN(0) Logic Input Current IIN(1) IIN(0) Maximum STEP Frequency HOME Output Voltage fSTEP VOH VOL Blank Time Fixed Off Time tBLANK toff IOH = -200 µA IOL = 200 µA Rt = 56 kΩ, Ct = 680 pF Rt = 56 kΩ, Ct = 680 pF VIN = 0.7VDD VIN = 0.3VDD Operating 3.0 0.7VDD – -20 -20 500* 0.7VDD – 700 30 5.0 – – <1.0 <1.0 – – – 950 38 5.5 – 0.3VDD 20 20 – – 0.3VDD 1200 46 V V V µA µA kHz V V ns µs 8.0 0 – – – – – – – – – – – <1.0 <1.0 0.45 0.36 – – – – – 35 35 20 -20 0.57 0.43 1.4 1.4 8.0 6.0 20 V V µA µA Ω Ω V V mA mA µA Symbol Test Conditions Min. Typ. Max. Unitscontinued next page …4115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000元器件交易网3977 MICROSTEPPPING DMOS DRIVER WITH TRANSLATORELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted)Limits Characteristic Control Logic (cont’d) Mixed Decay Trip Point Symbol Test Conditions Min. Typ. Max. – – VDD ±3.0 ±10 ±5.0 ±5.0 800 – – 2.95 – 12 10 20 Units V V V µA % % % ns °C °C V V mA mA µAPFDH – 0.6VDD PFDL – 0.21VDD Ref. Input Voltage Range VREF Operating 0 – Reference Input Current IREF – 0 EG VREF = 2 V, Phase Current = 38.27% – – Gain (Gm) Error VREF = 2 V, Phase Current = 70.71% – – (note 3) – – VREF = 2 V, Phase Current = 100.00% Crossover Dead Time tDT SR enabled 100 475 – 165 Thermal Shutdown Temp. TJ Thermal Shutdown Hysteresis ∆TJ – 15 2.45 2.7 UVLO Enable Threshold VUVLO Increasing VDD UVLO Hysteresis ∆VUVLO 0.05 0.10 Logic Supply Current IDD fPWM < 50 kHz – – Outputs off – – Sleep mode – – * Operation at a step frequency greater than the speciﬁed minimum value is possible but not warranteed. NOTES: 1. Typical Data is for design information only. 2. Negative current is deﬁned as coming out of (sourcing) the speciﬁed device terminal. 3. EG = ([VREF/8] – VSENSE)/(VREF/8)5元器件交易网3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATORFunctional DescriptionDevice Operation. The A3977 is a complete microstepping motor driver with built in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarterand eighth-step modes. The current in each of the two output H-bridges, all n-channel DMOS, is regulated with fixed off time pulse-width modulated (PWM) control circuitry. The H-bridge current at each step is set by the value of an external current sense resistor (RS), a reference voltage (VREF), and the DAC’s output voltage controlled by the output of the translator. At power up, or reset, the translator sets the DACs and phase current polarity to initial home state (see figures for home-state conditions), and sets the current regulator for both phases to mixed-decay mode. When a step command signal occurs on the STEP input the translator automatically sequences the DACs to the next level (see table 2 for the current level sequence and current polarity). The microstep resolution is set by inputs MS1 and MS2 as shown in table 1. If the new DAC output level is lower than the previous level the decay mode for that H-bridge will be set by the PFD input (fast, slow or mixed decay). If the new DAC level is higher or equal to the previous level then the decay mode for that H-bridge will be slow decay. This automatic current-decay selection will improve microstepping performance by reducing the distortion of the current waveform due to the motor BEMF. Reset Input (RESET). The RESET input (active low) sets the translator to a predefined home state (see figures for home state conditions) and turns off all of the DMOS outputs. The HOME output goes low and all STEP inputs are ignored until the RESET input goes high. Home Output (HOME). The HOME output is a logic output indicator of the initial state of the translator. At power up the translator is reset to the home state (see figures for home state conditions). Step Input (STEP). A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the state of inputs MS1 and MS2 (see table 1). Microstep Select (MS1 and MS2). Input terminals MS1 and MS2 select the microstepping format per table 1. Changes to these inputs do not take effect until the STEP command (see figure). Direction Input (DIR). The state of the DIRECTION input will determine the direction of rotation of the motor. Internal PWM Current Control. Each H-bridge is controlled by a fixed off time PWM current-control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and RS. When the voltage across the current-sense resistor equals the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off the source driver (slow-decay mode) or the sink and source drivers (fast- or mixed-decay modes). The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITRIPmax = VREF/8RS The DAC output reduces the VREF output to the current-sense comparator in precise steps (see table 2 for % ITRIPmax at each step). ITRIP = (% ITRIPmax/100) x ITRIPmax It is critical to ensure that the maximum rating (0.5 V) on the SENSE terminal is not exceeded. For full-step mode, VREF can be applied up to the maximum rating of VDD, because the peak sense value is 0.707 x VREF/8. In all other modes VREF should not exceed 4 V.6115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000元器件交易网3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATORFunctional Description (cont’d)Fixed Off-Time. The internal PWM current-control circuitry uses a one shot to control the time the driver(s) remain(s) off. The one shot off-time, toff, is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminal to ground. The off time, over a range of values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ is approximated by: toff = RTCT RC Blanking. In addition to the fixed off time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry. The comparator output is blanked to prevent false over-current detection due to reverse recovery currents of the clamp diodes, and/ or switching transients related to the capacitance of the load. The blank time tBLANK can be approximated by: tBLANK = 1400CT Charge Pump. (CP1 and CP2). The charge pump is used to generate a gate supply greater than VBB to drive the source-side DMOS gates. A 0.22 µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 µF ceramic capacitor is required between VCP and VBB to act as a reservoir to operate the high-side DMOS devices. VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 µF capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Enable Input (ENABLE). This active-low input enables all of the DMOS outputs. When logic high the outputs are disabled. Inputs to the translator (STEP, DIRECTION, MS1, MS2) are all active independent of the ENABLE input state. Shutdown. In the event of a fault (excessive junction temperature, or low voltage on VCP) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the undervoltage lockout (UVLO) circuit disables the drivers and resets the translator to the HOME state. Sleep Mode (SLEEP). An active-low control input used to minimize power consumption when not in use. This disables much of the internal circuitry including the output DMOS, regulator, and charge pump. A logic high allows normal operation and startup of the device in the home position. When coming out of sleep mode, wait 1 ms before issuing a STEP command to allow the charge pump (gate drive) to stabilize. Percent Fast Decay Input (PFD). When a STEP input signal commands a lower output current from the previous step, it switches the output current decay to either slow-, fast-, or mixed-decay depending on the voltage level at the PFD input. If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. This terminal should be decoupled with a 0.1 µF capacitor. Mixed Decay Operation. If the voltage on the PFD input is between 0.6VDD and 0.21VDD, the bridge will operate in mixed-decay mode depending on the step sequence (see figures). As the trip point is reached, the device will go into fast-decay mode until the voltage on the RC terminal decays to the voltage applied to the PFD terminal. The time that the device operates in fast decay is approximated by: tFD = RTCTIn (0.6VDD/VPFD) After this fast decay portion, tFD, the device will switch to slow-decay mode for the remainder of the fixed off-time period.7元器件交易网3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATORFunctional Description (cont’d)Synchronous Rectification. When a PWM off cycle is triggered by an internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3977 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay and effectively short out the body diodes with the low rDS(on) driver. This will reduce power dissipation significantly and eliminate the need for external Schottky diodes for most applications. The synchronous rectification can be set in either active mode or disabled mode. Active Mode. When the SR input is logic low, active mode is enabled and synchronous rectification will occur. This mode prevents reversal of the load current by turning off synchronous rectification when a zero current level is detected. This prevents the motor winding from conducting in the reverse direction. Disabled Mode. When the SR input is logic high, synchronous rectification is disabled. This mode is typically used when external diodes are required to transfer power dissipation from the A3977 package to the external diodes.Timing Requirements (TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground)STEP50%C A BDMS1/MS2/ DIR/RESETESLEEPDwg. WP-042A. Minimum Command Active Time Before Step Pulse (Data Set-Up Time) ..... 200 ns B. Minimum Command Active Time After Step Pulse (Data Hold Time) ............ 200 ns C. Minimum STEP Pulse Width ...................... 1.0 µs D. Minimum STEP Low Time ......................... 1.0 µs E. Maximum Wake-Up Time ......................... 1.0 ms8115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000元器件交易网3977 MICROSTEPPING DMOS DRIVER WITH TRANSLATORApplications InformationLayout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. The load supply terminal, VBB, should be decoupled with an electrolytic capacitor (>47 µF is recommended) placed as close to the device as possible. To avoid problems due to capacitive coupling of the high dv/dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. Always drive the logic inputs with a low source impedance to increase noise immunity. Grounding. A star ground system located close to the driver is recommended. The 44-lead PLCC has the analog ground and the power ground internally bonded to the power tabs of the package (leads 44, 1, 2, 11 – 13, 22 – 24, and 33 – 35). On the 28-lead TSSOP package, the analog ground (lead 7) and the power ground (lead 21) must be connected together externally. The copper ground plane located under the exposed thermal pad is typically used as the star ground. Current Sensing. To minimize inaccuracies caused by ground-trace IR drops in sensing the output current level, the current-sense resistor (RS) should have an independent ground return to the star ground of the device. This path should be as short as possible. For low-value sense resistors the IR drops in the printed wiring board sense resistor’s traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. Allegro MicroSystems recommends a value of RS given by RS = 0.5/ITRIPmax Thermal Protection. Circuitry turns off all drivers when the junction temperature reaches 165°C, typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C.9元器件交易网3977 MICROSTEPPPING DMOS DRIVER WITH TRANSLATORTable 2. Step Sequencing Home State = 45º Step Angle, DIR = HFull Step Half Step 1 ¼ Step 1 ⅛ Step 1 2 2 3 4 1 2 3 5 6 4 7 8 3 5 9 10 6 11 12 2 4 7 13 14 8 15 16 5 9 17 18 10 19 20 3 6 11 21 22 12 23 24 7 13 25 26 14 27 28 4 8 15 29 30 16 31 32 Phase 1 Current (%Itripmax) (%) 100.00 98.08 92.39 83.15 70.71 55.56 38.27 19.51 0.00 –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –98.08 –100.00 –98.08 –92.39 –83.15 –70.71 –55.56 –38.27 –19.51 0.00 19.51 38.27 55.56 70.71 83.15 92.39 98.08 Phase 2 Current (%Itripmax) (%) 0.00 19.51 38.27 55.56 70.71 83.15 92.39 98.08 100.00 98.08 92.39 83.15 70.71 55.56 38.27 19.51 0.00 –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –98.08 –100.00 –98.08 –92.39 –83.15 –70.71 –55.56 –38.27 –19.51 Step Angle (º) 0.0 11.3 22.5 33.8 45.0 56.3 67.5 78.8 90.0 101.3 112.5 123.8 135.0 146.3 157.5 168.8 180.0 191.3 202.5 213.8 225.0 236.3 247.5 258.8 270.0 281.3 292.5 303.8 315.0 326.3 337.5 348.810115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000Full-Step OperationMS1 = MS2 = L, DIR = HThe vector addition of the output currents at any step is100%.Half-Step OperationMS1 = H, MS2 = L, DIR = HThe mixed-decay mode is controlled by the percent fastdecay voltage (V PFD). If the voltage at the PFD input isgreater than 0.6V DD then slow-decay mode is selected. Ifthe voltage on the PFD input is less than 0.21V DD thenfast-decay mode is selected. Mixed decay is betweenthese two levels.Quarter-Step OperationMS1 = L, MS2 = H, DIR = HThe mixed-decay mode is controlled by the percent fastdecay voltage (V PFD). If the voltage at the PFD input isgreater than 0.6V DD then slow-decay mode is selected. Ifthe voltage on the PFD input is less than 0.21V DD thenfast-decay mode is selected. Mixed decay is betweenthese two levels.8 Microstep/Step OperationMS1 = MS2 = H, DIR = HThe mixed-decay mode is controlled by the percent fastdecay voltage (V PFD). If the voltage at the PFD input isgreater than 0.6V DD then slow-decay mode is selected. Ifthe voltage on the PFD input is less than 0.21V DD thenfast-decay mode is selected. Mixed decay is betweenthese two levels.Terminal ListTerminal A3977xLP A3977xED Name Terminal Description(TSSOP)(PLCC) GND Analog and power ground–44, 1, 2 SENSE1Sense resistor for bridge 113 HOME Logic output24DIR Logic Input35 OUT1A DMOS H bridge 1 output A46NC No (internal) connection–7, 8 PFD Mixed decay setting59RC1Analog Input for fixed offtime – bridge 1610 GND Analog and power ground–11, 12, 13 AGND Analog ground7*–REF Gm reference input814RC2Analog input for fixed offtime – bridge 2915 LOGIC SUPPLY V DD, the logic supply voltage1016NC No (internal) connection–17 OUT2A DMOS H bridge 2 output A1118MS2Logic input1219MS1Logic input1320 SENSE2Sense resistor for bridge 21421 GND Analog and power ground–22, 23, 24 LOAD SUPPLY2V BB2, the load supply for bridge 21525SR Logic input1626 RESET Logic input1727 OUT2B DMOS H bridge 2 output B1828NC No (internal) connection–29, 30 STEP Logic input1931V REG Regulator decoupling2032 PGND Power ground21*–GND Analog and power ground–33, 34, 35 V CP Reservoir capacitor2236CP1Charge pump capacitor2337CP2Charge pump capacitor2438NC No (internal) connection–39 OUT1B DMOS H bridge 1 output B2540 ENABLE Logic input2641 SLEEP Logic input2742 LOAD SUPPLY1V BB1, the load supply for bridge 12843* AGND and PGND on the TSSOP package must be connected together externally.A3977xEDNOTES:1.Exact body and lead configuration at vendor ’s option within limits shown.2.Lead spacing tolerance is non-cumulative.3.Webbed lead frame. Terminals 1, 2, 11, 12, 13, 22, 23, 24, 33, 34, 35, and 44 are internally one piece.4.Supplied in standard sticks/tubes of 27 devices or add “TR ” to part number for tape and reel.0.0210.013400.5330.331Dimensions in Inches (controlling dimensions)(for reference only)NOTES:1.Exact body and lead configuration at vendor ’s option within limits shown.2.Lead spacing tolerance is non-cumulative.3.Supplied in standard sticks/tubes of 49 devices or add “TR ” to part number for tape and reel.0.00790.0035GAUGE PLANE INDEX AREA0.09GAUGE PLANE SEATING PLANEINDEX AREADimensions in Inches(for reference only)(controlling dimensions)The products described here are manufactured under one or more U.S. patents or U.S. patents pending.Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi-bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.。

A3977步进电机驱动芯片中文说明

1 引言随着微步进电机应用的日益广泛，其驱动电路的发展也相当迅速，各类控制芯片的功能越来越丰富，操作也越来越简便。

A3977是一种新近开发出来、专门用于双极型步进电机的微步进电机驱动集成电路，其内部集成了步进和直接译码接口、正反转控制电路、双H桥驱动，电流输出2．5A，最大输出功率可接近90W。

它主要的设计功能包括：自动混合模式电流衰减控制，PWM电流控制，同步整流，低输出阻抗的DMOS电源输出，全、半、1／4及1／8步进操作，HOME输出，休眠模式以及易实现的步进和方向接口等。

其应用电路结构简单、使用及控制方便，有着极其广泛的应用价值。

2 A3977工作特点大多数微步进电机驱动器都需要一些额外的控制线，通过D／A转换器为PWM电流调节器设置参考值以及通过相输入完成电流极性控制等。

许多改进型驱动器仍然需要一些输入来调整PWM电流控制模式使其工作在慢、快或混合衰减模式。

这就需要系统的微处理器额外负担8～12个需依靠D／A变换处理的输入端。

如果一个系统需要如此多的控制输入，而且其微处理器还要存储实现其控制的时序表，这就增加了系统的成本和复杂程度。

A3977可以通过其特有的译码器来使这些功能实现简单化，如图1所示，其最简单的步进输入只需“STEP”（步进）和“DIR”（方向）2条输入线，输出由DMOS的双H桥完成。

通过“STEP”脚简单的输入1个脉冲就可以使电机完成1次步进，省去了相序表，高频控制线及复杂的编程接口。

这使其更适于应用在没有复杂的微处理器或微处理器负担过重的场合。

同时A3977的内部电路可以自动地控制其PWM操作工作在快、慢及混合衰减模式。

这不但降低了电机工作时产生的噪声，也同时省去了一些额外的控制线。

另外，其内部低输出阻抗的N沟道功率DMOS输出结构，可以使其输出达到2．5A，35V。

这一结构的另一优点是，使它能完成同步整流功能。

由于有同步整流流功能，既降低了系统的功耗，又可以在应用时省去外加的肖特基二极管。

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1 引言随着微步进电机应用的日益广泛，其驱动电路的发展也相当迅速，各类控制芯片的功能越来越丰富，操作也越来越简便。

其应用电路结构简单、使用及控制方便，有着极其广泛的应用价值。

2 A3977工作特点大多数微步进电机驱动器都需要一些额外的控制线，通过D／A转换器为PWM电流调节器设置参考值以及通过相输入完成电流极性控制等。

许多改进型驱动器仍然需要一些输入来调整PWM电流控制模式使其工作在慢、快或混合衰减模式。

这就需要系统的微处理器额外负担8～12个需依靠D／A变换处理的输入端。

如果一个系统需要如此多的控制输入，而且其微处理器还要存储实现其控制的时序表，这就增加了系统的成本和复杂程度。

通过“STEP”脚简单的输入1个脉冲就可以使电机完成1次步进，省去了相序表，高频控制线及复杂的编程接口。

这使其更适于应用在没有复杂的微处理器或微处理器负担过重的场合。

同时A3977的内部电路可以自动地控制其PWM操作工作在快、慢及混合衰减模式。

这不但降低了电机工作时产生的噪声，也同时省去了一些额外的控制线。

另外，其内部低输出阻抗的N沟道功率DMOS输出结构，可以使其输出达到2．5A，35V。

这一结构的另一优点是，使它能完成同步整流功能。

由于有同步整流流功能，既降低了系统的功耗，又可以在应用时省去外加的肖特基二极管。

A3977的休眠功能可以使系统不工作时的功耗达到最低。

休眠时芯片的大部分内部电路，如输出DMOS、比较器及电荷泵等都将停止工作。

从而在休眠模式时，包括电机驱动电流在内的总电流消耗在40μA以内。

此外，内部保护电路还有利用磁滞实现的热停车、低压关断及换流保护等功能。

集成电路的主要特点：（1）额定输出为：±2．5A，35V。

（2）低输出阻抗，源端0．45Ω，接收端0．36Ω。

（3）自动电流衰减检测并选择混合、快和慢等电流衰减模式。

（4）逻辑电平范围为3．0～5．5V。

（5）HOME输出。

（6）降低功耗的同步整流功能。

（7）内部低压关断、热停车电路及环流保护。

3 A3977引脚说明A3977有两种封装：一种是44引脚铜标塑封（后缀为ED，A3977SED），另一种是28引脚带散热衬垫的塑封（后缀为LP，A3977SLP），其引脚功能说明如表1所示。

电荷泵CP1、CP2可以产生一个高于VBB的门电平，用来驱动DMOS源端的门。

其实现方法是在CP1和CP2之间接一个0．22μF的陶瓷电容。

同时VCP和VBB间也需要一个0．22μF的陶瓷电容作为一个蓄能器，用来操作DMOS的高端设备。

VREG是由系统内部产生，用于对DMOS漏端输出进行操作。

VREG引脚须对地加一个0．22μF的陶瓷电容作为一个蓄能器，用来操作DMOS的高端设备。

VREG是由系统内部产生，用于对DMOS漏端输出进行操作。

VREG引脚须对地加一个0．22μF的电容去耦。

VREG是受内部的电平调节器控制的，发生故障时其输出是被禁止的。

RC1和RC2引脚是为内部PWM电路提供固定截止时间的。

A3977的内部PWM控制电路是用一个脉冲来控制器件的截止时间的。

而这个脉冲的—84—截止时间toff就是由RC1和RC2引脚对地所接的电阻RT和电容CT决定的，即：toff＝RT CT式中，电阻RT和电容CT的取值范围分别为12～100kΩ及470～1 500pF〉另外，除了可以为内部PWM控制提供截止时间外，CT还为比较器提供了关断时间tBLANK。

A3977的设计要求当其输出由内部电流控制电路切换时，电路取样比较器的输出是被禁止的。

从而可以防止对过电流检测作出误判断。

tBLANK的取值为：tBLANK＝1400CTENABLE输入为低电平有效，它是DMOS输出的使能控制信号。

RESET输入也是低电平有效，当其为低电平时，DMOS的输出将被关断，所有的步进逻辑输入也将被忽略直至其输入变高为止。

4 基本功能说明及应用电路由于采用了内置译码器技术，A3977可以很容易的使用最少的控制线对步进电机实施微步进控制。

具体功能实现如下：（1）步进控制：步进控制信号有步进输入（STEP）、步进模式逻辑输入（MS1，MS2）以及方向控制信号（DIR）。

每一次上电或复位（RESET＝0）后，在内置译码器的作用下将H桥的输出预置到HOME输入所对应的输出状态，然后当STEP输入的上升沿到来后，内置译码器将根据步进逻辑的输入值（步进模式见表2）控制H桥的输出，使电机在当前步进模式下产生1次步进。

步进的方向由DIR的输入逻辑控制，其高、低电平分别控制双相电机正反转。

注：①全步进转过的角度为45°。

（2）内部PWM电流控制：每一个H桥都有一个有固定截止时间的PWM电流控制电路，以限制其负载电流在一个设计值。

初始时，对角线上的一对源接收DMOS（一对上下桥臂）处于输出状态，电流流经电机绕组和SENCE脚所接的电流取样电阻（见图1）。

当取样电阻上的压降等于D／A的输出电压时，电流取样比较器将PWM锁存器复位，从而关断源驱动器（上桥臂），进入慢衰减模式；或同时关断源接收驱动器（上下桥臂）进入快或混合衰减模式，使产生环流或电流回流至源端。

该环流或回流将持续衰减至固定截止时间结束为止。

然后，正确的输出桥臂被再次启动，电机绕组电流再次增加，整个PWM循环完成。

其中，最大限流Imax是由取样电阻RS和电流取样比较器的输入电平VREF控制的：Imax＝VREF／8RS固定截止时间toff的计算如上所述。

（3）电流衰减模式控制：A3977具有自动检测电流衰减及选择电流衰减模式功能，从而能给微步进提供最佳的正弦电流输出。

电流衰减模式由PFD的输入进行控制，其输入电平的高低控制输出电流处于慢、快及混合衰减模式。

如果PFD的输入电压高于0．6VDD，则选择慢衰减模式。

如果PFD的输入电压低于0．21VDD，则选择快衰减模式。

处于二者之间的PFD电平值将选择混合衰减模式。

其中混合衰减模式将一个PWM周期的固定截止时间分为快、慢两个衰减部分。

当电流达到最大限流Imax 后，系统将进入快衰减模式直至SENCE上的取样电压衰减至PFD的端电压VPFD。

经过tFD的快衰减后，器件将切换至慢衰减模式直至固定截止时间结束。

其中，器件工作在快衰减模式的时间tFD为：tFD＝RTCrln（0．6VPFD／VPFD）（4）同步整流控制：同步整流控制是由SR的逻辑输入控制的。

当SR输入为低电平时，同步整流功能将被启动。

此期间，当检测到电流为零值时，可通过关闭同步整流功能来防止负载电流反向，从而防止了电机绕组反方向导通。

而当SR输入为高电平时，同步整流将被禁止。

（5）休眠模式：当SLEEP引脚输入为低电平时，器件将进入休眠模式，从而大大降低器件空闲的功耗。

进入休眠模式后器件的大部分内部电路包括DMOS输出电路、调节器及电荷泵等都将停止工作。

当其输入为高电平时，系统恢复到正常的操作状态并将器件的输出预置到HOME状态。

（6）典型应用电路：其典型应用电路如图1所示，可见其应用电路是非常简单的，其正常工作时仅需5个逻辑输入即可。

5 应用注意事项（1）PFD引入端应加一个0．1μF的电容去耦。

（2）布线时应布一个较厚的地层，最好在本器件周围布上星形地。

（3）最好将芯片直接焊接在线路板上。

（4）为VBB引脚加一个大于47μF的电解电容去耦（越靠近芯片越好）。

（5）为保证输出电流取样的精确，最好使取样电阻有自己单独的地，并将其连到器件周围的星形地上，而且引线越短越好。

（6）当系统由休眠模式退出后，最少要延迟1ms才可以输入步进命令，从而为驱动DMOS的电荷泵复位提供充裕的时间主要特点及应用:(1)额定输出为:±2．5A,35V.(2)低输出阻抗,源端0．45Ω,接收端0．36Ω.(3)自动电流衰减检测并选择混合、快和慢等电流衰减模式.(4)逻辑电平范围为3．0~5．5V.(5)HOME输出.(6)降低功耗的同步整流功能.(7)内部低压关断、热停车电路及环流保护.A3977带转换器的微步 DMOS 驱动器特点•±2.5 安培 35 伏特输出率•低 r DS(ON)输出（一般为 0.45 欧源极，0.36 欧灌电流）•自驱电流衰减模式检测/选择• 3.0 至 5.5 伏特逻辑电源电压范围•混合、快与慢电流-衰减模式•自动导向输出•对低功率耗散同步整流•内部欠压锁定 (UVLO) 及过热关机电路•交叉电流保护转换器是 A3977 易于实施的关键。

通过简单的在"步进"输入中输入一个脉冲，电动机会产生步进（完整、1/2、1/4 或 1/8 步进，根据两个逻辑输入的情况而定）。

该程序中没有相位顺序表、高频率控制行或复杂的界面。

A3977 界面非常适合复杂的µP 不可用或过载的应用。

内部同步整流控制电路用来改善脉宽调制 (PWM) 操作时的功率消耗。

内部电路保护包括因滞后引起的过热关机、欠压锁定 (UVLO) 及交叉电流保护。

不需要特别的加电排序。

A3977 具有两种功率封装可供选择，即带铜质蝙蝠翼状片的 44 引脚塑料 PLCC 以及带外露隔热盘的（后缀为 LP）的较薄（<1.2 毫米）28 引脚 TSSOP。

该 SLP 封装是无铅产品，且引脚框采用 100% 雾锡电镀。

功能方框图完整型号型号封装类型RoHS符合性温度A3977SED44-铅 PLCC否-20 °C 至 85 °CA3977SED-T44-铅 PLCC是-20 °C 至 85 °CA3977SEDTR44-铅 PLCC否-20 °C 至 85 °CA3977SEDTR-T44-铅 PLCC是-20 °C 至 85 °CA3977SLP28-铅 TSSOP否-20 °C 至 85 °CA3977SLP-T28-铅 TSSOP是-20 °C 至 85 °CA3977SLPTR28-铅 TSSOP否-20 °C 至 85 °CA3977SLPTR-T28-铅 TSSOP是-20 °C 至 85 °CA3977KED-T44-铅 PLCC是-40 °C 至 125 °CA3977KEDTR-T44-铅 PLCC是-40 °C 至 125 °CA3977KLP-T28-铅 TSSOP是-40 °C 至 125 °CA3977KLPTR-T28-铅 TSSOP是-40 °C 至 125 °C特点及注意事项：A3977是一种新近开发出来、专门用于双极型步进电机的微步进电机驱动集成电路,其内部集成了步进和直接译码接口、正反转控制电路、双H桥驱动,电流输出2．5A,最大输出功率可接近90W.它主要的设计功能包括:自动混合模式电流衰减控制,PWM电流控制,同步整流,低输出阻抗的DMOS电源输出,全、半、1/4及1/8步进操作,HOME输出,休眠模式以及易实现的步进和方向接口等.其应用电路结构简单、使用及控制方便,有着极其广泛的应用价值.A3977工作特点大多数微步进电机驱动器都需要一些额外的控制线,通过D/A转换器为PWM电流调节器设置参考值以及通过相输入完成电流极性控制等.许多改进型驱动器仍然需要一些输入来调整PWM电流控制模式使其工作在慢、快或混合衰减模式.这就需要系统的微处理器额外负担8~12个需依靠D/A变换处理的输入端.如果一个系统需要如此多的控制输入,而且其微处理器还要存储实现其控制的时序表,这就增加了系统的成本和复杂程度.A3977可以通过其特有的译码器来使这些功能实现简单化,如图1所示,其最简单的步进输入只需“STEP”(步进)和“DIR”(方向)2条输入线,输出由DMOS的双H桥完成.通过“STEP”脚简单的输入1个脉冲就可以使电机完成1次步进,省去了相序表,高频控制线及复杂的编程接口.这使其更适于应用在没有复杂的微处理器或微处理器负担过重的场合.同时A3977的内部电路可以自动地控制其PWM 操作工作在快、慢及混合衰减模式.这不但降低了电机工作时产生的噪声,也同时省去了一些额外的控制线.另外,其内部低输出阻抗的N沟道功率DMOS输出结构,可以使其输出达到2．5A,35V.这一结构的另一优点是,使它能完成同步整流功能.由于有同步整流流功能,既降低了系统的功耗,又可以在应用时省去外加的肖特基二极管.A3977的休眠功能可以使系统不工作时的功耗达到最低.休眠时芯片的大部分内部电路,如输出DMOS、比较器及电荷泵等都将停止工作.从而在休眠模式时,包括电机驱动电流在内的总电流消耗在40μA以内.此外,内部保护电路还有利用磁滞实现的热停车、低压关断及换流保护等功能.集成电路的主要特点:(1)额定输出为:±2．5A,35V.(2)低输出阻抗,源端0．45Ω,接收端0．36Ω.(3)自动电流衰减检测并选择混合、快和慢等电流衰减模式.(4)逻辑电平范围为3．0~5．5V.(5)HOME输出.(6)降低功耗的同步整流功能.(7)内部低压关断、热停车电路及环流保护.应用注意事项(1)PFD引入端应加一个0．1μF的电容去耦.(2)布线时应布一个较厚的地层,最好在本器件周围布上星形地.(3)最好将芯片直接焊接在线路板上.(4)为VBB引脚加一个大于47μF的电解电容去耦(越靠近芯片越好).(5)为保证输出电流取样的精确,最好使取样电阻有自己单独的地,并将其连到器件周围的星形地上,而且引线越短越好.(6)当系统由休眠模式退出后,最少要延迟1ms才可以输入步进命令,从而为驱动DMOS的电荷泵复位提供充裕的时间.关于步进电机驱动芯片A3977常见问题的解答Q1，问：能否提供A3977的应用笔记？答：是的，请参看应用笔记STP01-2“一种新型的集成步进和方向控制译码器的细分步进电机驱动芯片”。