EDA技术及应用朱正伟三四五章部分课后题答案

第三章

3-5设计一个4选1多路选择器，当选择输入信号分别取“00”、“01”、“10”和“11”时，输出信号分别与一路输入信号相连。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MAX4_1 IS

PORT(A,B,C,D,S1,S2 : IN STD_LOGIC;

Y : OUT STD_LOGIC);

END ENTITY MAX4_1;

ARCHITECTURE HF1 OF MAX4_1 IS

SIGNAL SS : STD_LOGIC_VECTOR (0 TO 1);

BEGIN

SS<=S2&S1;

PROCESS(SS)

BEGIN

CASE SS IS

WHEN "00" => Y<=A;

WHEN "01" => Y<=B;

WHEN "10" => Y<=C;

WHEN "11" => Y<=D;

WHEN OTHERS => NULL;

END CASE;

END PROCESS;

END HF1;

3-6设计一个7人表决电路，参加表决者7人，同意为1，不同意为0，同意者过半则表决通过，绿指示灯亮；表决不通过则红指示灯亮。设计思路：根据7人表决电路设计要求，7人中至少有4个通过才可以表决通过，故可以在程序中设置一个变量TEMP，使其在表决电路中遇1则加1，遇0则加0（设计中1表示通过，0表示不通过）。当TEMP>=4时，表示表决通过，当TEMP<4时表决不通过。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY VOTE7 IS

PORT (MEN:IN STD_LOGIC_VECTOR(6 DOWNTO 0);

OUTPUT: OUT BIT);

END VOTE7;

ARCHITECTURE BEHA VE OF VOTE7 IS

BEGIN

PROCESS(MEN)

V ARIABLE TEMP: INTEGERRANGE 0 TO 7;

BEGIN

TEMP:=0;

FOR I IN 0 TO 6 LOOP

IF(MEN(I)='1')THEN

TEMP:=TEMP+1;

ELSE

TEMP:=TEMP;

END IF;

END LOOP;

CASE TEMP IS

WHEN 0 TO 3 =>OUTPUT<='0';

WHEN 4 TO 7 =>OUTPUT<='1';

END CASE ;

END PROCESS;

END BEHA VE;

第四章

4-6试写出4选1多路选择器VHDL描述。选择控制信号为S1和S0,输入信号为A，B，C，D，输出信号为Y。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41A IS

PORT (A,B,C,D,S0,S1:IN STD_LOGIC; --输入信号

Y:OUT STD_LOGIC); --输出信号

END ENTITY MUX41A;

ARCHITECTURE ONE OF MUX41A IS

SIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0);

BEGIN

S<=S0&S1; --并置操作，获得二维矢量数据类型

PROCESS(S0,S1,A,B,C,D) --敏感信号

BEGIN

CASE S IS

WHEN"00"=> Y<=A;

WHEN"01"=> Y<=B;

WHEN"10"=> Y<=C;

WHEN"11"=> Y<=D;

WHEN OTHERS=>NULL; --其它情况为空值

END CASE; --CASE语句结束

END PROCESS; --PROCESS进程语句结束

END ARCHITECTURE ONE;

4-7使给出1位全减器的VHDL描述,要求:首先设计1位半减器,然后用例化语句将它们连接起来。设X为被减数，Y为减数，SUB_IN是借位输入，DIFF是输出差,SUB_OUT是借位输出。

(1.1)：实现1位半减器H_SUBER(DIFF=X-Y；S_OUT=1,X

LIBRARY IEEE; --半减器描述(1):布尔方程描述方法

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_SUBER IS

PORT( X,Y: IN STD_LOGIC;

DIFF,S_OUT: OUT STD_LOGIC);

END ENTITY H_SUBER;

ARCHITECTURE HS1 OF H_SUBER IS

BEGIN

DIFF <= X XOR (NOT Y);

S_OUT <= (NOT X) AND Y;

END ARCHITECTURE HS1;

--解(1.2)：采用例化实现图4-20的1位全减器

LIBRARY IEEE; --1位二进制全减器顺层设计描述

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY F_SUBER IS

PORT(XIN,YIN,SUB_IN: IN STD_LOGIC;

SUB_OUT,DIFF_OUT: OUT STD_LOGIC);

END ENTITY F_SUBER;

ARCHITECTURE FS1 OF F_SUBER IS

COMPONENT H_SUBER --调用半减器声明语句

PORT(X, Y: IN STD_LOGIC;

DIFF,S_OUT: OUT STD_LOGIC);

END COMPONENT;

SIGNAL A,B,C: STD_LOGIC; --定义1个信号作为内部的连接线。

BEGIN

U1:H_SUBERPORT MAP(X=>XIN,Y=>YIN, DIFF=>A, S_OUT=>B); U2:H_SUBERPORT MAP(X=>A, Y=>SUB_IN, DIFF=>DIFF_OUT,S_OUT=>C);

SUB_OUT <= C OR B;

END ARCHITECTURE FS1;

二进制全加器，元件声明与元件例化（COMPONENT,PORT MAP）

//或门LIBRARY IEEE; ；

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY OR2A IS

PORT(A,B : IN STD_LOGIC;

C : OUT STD_LOGIC);

END OR2A;

ARCHITECTURE ART1 OF OR2A IS

BEGIN

C<=A OR B;

END ART1;

//半加器；

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_ADDER IS

PORT(A,B : IN STD_LOGIC;

CO,SO: OUT STD_LOGIC);

END H_ADDER;

ARCHITECTURE ART2 OF H_ADDER IS