单片机AT89C2051中英文说明书
at89c52单片机简介中英文对照外文翻译文献
at89c52单片机简介中英文对照外文翻译文献中英文资料对照外文翻译A T89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。
Storage RAM immediately﹑memoy read ROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。
Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。
AT89C2051单片机)
2．1 AT89C2051单片机及其引脚说明
AT89C2051说明
89C2051是由ATMEL公司推出的一种小型单片机。
95年出现在中国市场。
其主要特点为采用Flash存贮器技术，降低了制造成本，其软件、硬件与MCS-51完全兼容，可以很快被中国广大用户接受，其程序的电可擦写特性，使得开发与试验比较容易。
1 引脚
89C2051共有20条引脚，详见图1.从图中可见，2051继承了8031最重要引脚：P1口共8脚，准双向端口。
P3.0～P3.6共7脚，准双向端口，并且保留了全部的P3的第二功能，如P3.0、P3..1的串行通讯功能，P3.2、P3..3的中断输入功能，P3.4、P3.5的定时器输入功能。
在引脚的驱动能力上面，89C2051具有很强的下拉能力，P1,P3口的下拉能力均
可达到20mA.相比之下，89C51/87C51的端口下拉能力每脚最大
为15mA。
但是限定9脚电流之和小于71mA.这样，引脚的平均
电流只9mA。
89C2051驱动能力的增强，使得它可以直接驱动
LED数码管。
为了增加对模拟量的输入功能，2051在内部构造了一个模拟信
号比较器，其输入端连到P1.0和P1.1口，比较结果存入P3.6
对应寄存器，（P3.6在2051外部无引脚），原理见图2。
对于一些不大复杂的控制电路我们就可以增加少量元件来实
现，例如，对温度的控制，过压的控制等。
图3为测量示意图。
其中，R用于测量门限的调节，IN端接输
入模拟信号。
AT89C2051中文资料
AT89C205189C2051是由ATMEL公司推出的一种小型单片机。
95年出现在中国市场。
其主要特点为采用Flash存贮器技术，降低了制造成本，其软件、硬件与MCS-51完全兼容，可以很快被中国广大用户接受，其程序的电可擦写特性，使得开发与试验比较容易。
89C2051共有20条引脚，详见图1.从图中可见，2051继承了8031最重要引脚：P1口共8脚，准双向端口。
P3.0～P3.6共7脚，准双向端口，并且保留了全部的P3的第二功能，如P3.0、P3..1的串行通讯功能，P3.2、P3..3的中断输入功能,P3.4、P3.5的定时器输入功能。
在引脚的驱动能力上面，89C2051具有很强的下拉能力，P1,P3口的下拉能力均可达到20mA.相比之下，89C51/87C51的端口下拉能力每脚最大为15mA。
但是限定9脚电流之和小于71mA.这样，引脚的平均电流只9mA。
89C2051驱动能力的增强，使得它可以直接驱动LED数码管。
为了增加对模拟量的输入功能，2051在内部构造了一个模拟信号比较器，其输入端连到P1.0和P1.1口，比较结果存入P3.6对应寄存器，（P3.6在2051外部无引脚），原理见图2。
对于一些不大复杂的控制电路我们就可以增加少量元件来实现，例如，对温度的控制，过压的控制等。
图3为测量示意图。
其中，R用于测量门限的调节，IN端接输入模拟信号。
2 电源89C2051有很宽的工作电源电压，可为2.7～6V,当工作在3V时，电流相当于6V工作时的1/4。
89C2051工作于12Hz时，动态电流为5.5mA，空闲态为1mA,掉电态仅为20nA。
这样小的功耗很适合于电池供电的小型控制系统。
3 存储器89C2051片内含有2k字节的Flash程序存储器，128字节的片内RAM,与80C31内部完全类似。
由于2051内部设计全静态工作，所以允许工作的时钟为0～20MHz,也就是说，允许在低速工作时，不破坏RAM内容。
单片机AT89C2051中英文说明书
AT89C2051主要性能参数：与MCS-51产品指令系统完全兼容1．2k字节可重擦写闪速存储器2.1000次擦写周期3.2.7—6V的工作电压范围4.全静态操作：OHz—24MHz5.两级加密程序存储器6.128x8字节内部RAM7.15个可编程I/O口线8.两个16位定时/计数器9.6个中断源10.可编程串行UART通道11.可直接驱动LED的输出端口12.内置一个模拟比较器13.低功耗空闲和掉电模式功能特性概述A T89C2051提供以下标准的功能：2k字节Flash闪速存储器，128字节内部RAM,15个I/O 口线，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，内置一个精密比较器，片内振荡器及时钟电路。
同时，AT89C2051可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。
空闲方式停止CPU的工作，但振荡器停止工作并禁止其他所有部件工作直到下一个硬件复位。
方框图引脚功能说明：Vcc:电源电压GND: 地P1口：p1口是一组8位双向I/O口，P1.2~P1.7提供内部上拉电阻，P1.0和p1.1内部无上拉电阻，主要考虑他们分别是内部精密比较器的相同输入器（AINO）和反相输入端（AINI）,如果需要应在外部接上拉电阻。
P1口输入缓冲器可吸收20mA电流并可直接驱动LED当P1口引脚写入“1”时可作输入端，当引脚P1.2~P1.7用作输入并被外部拉低时，他们将因为内部的上拉电阻位输出电流（In）。
P1口还在flash闪速编程及程序校验时接收代码数据。
P3口：P3口的P3.0~P3.5、P3.7是带有内部上拉电阻的7个双向I/O口。
P3.6没有引出，它作为一个通用的I/O口淡并不可以访问，但可以作为固定输入片内比较器的输出信号，P3.口缓冲器可吸收20mA电流。
当P3口写入“1”时，他们被内部上拉电阻拉高并可作为输入端口。
作为输入端是，被外部拉低的P3口将用上拉电阻输出电流（In）。
关于AT89C51单片机的中英翻译
The Introduction of AT 89C51 DescriptionMicrocontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system tocontinue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin Description·VCC: Supply voltage.·GND: Ground.·Port 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification.·Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 1 also receives the low-order address bytes during Flash programming and verification.·Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory andduring accesses to external data memory that uses 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.·Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups.Port 3 also serves the functions of various special features of the AT89C51 as listed below。
51单片机AT89C51 AT89C2051中文资料
51单片机AT89C51/AT89C2051中文资料--------------------------------------------------------------------------------51单片机AT89C51/AT89C2051中文资料AT89C51是一种带4K字节闪烁可编程可擦除只读存储器（FPEROM—Falsh Programmable and Erasable Read Only Memory）的低电压，高性能CMOS8位微处理器，俗称单片机。
AT89C2051是一种带2K字节闪烁可编程可擦除只读存储器的单片机。
单片机的可擦除只读存储器可以反复擦除100次。
该器件采用ATMEL高密度非易失存储器制造技术制造，与工业标准的MCS-51指令集和输出管脚相兼容。
由于将多功能8位CPU和闪烁存储器组合在单个芯片中，ATMEL的A T89C51是一种高效微控制器，AT89C2051是它的一种精简版本。
AT89C单片机为很多嵌入式控制系统提供了一种灵活性高且价廉的方案。
1．主要特性：·与MCS-51 兼容·4K字节可编程闪烁存储器寿命：1000写/擦循环数据保留时间：10年·全静态工作：0Hz-24Hz·三级程序存储器锁定·128*8位内部RAM·32可编程I/O线·两个16位定时器/计数器·5个中断源·可编程串行通道·低功耗的闲置和掉电模式·片内振荡器和时钟电路2．管脚说明：VCC：供电电压。
GND：接地。
P0口：P0口为一个8位漏级开路双向I/O口，每脚可吸收8TTL门电流。
当P1口的管脚第一次写1时，被定义为高阻输入。
P0能够用于外部程序数据存储器，它可以被定义为数据/地址的第八位。
在FIASH编程时，P0 口作为原码输入口，当FIASH进行校验时，P0输出原码，此时P0外部必须被拉高。
AT89C2051中文资料
AT89C2051中文资料特性：·与MCS－51产品兼容·2K字节可重编程闪存－耐久性：1000次读/写周期·工作电压2.7V至V·全静态运行：0Hz至24MHz·两级程序锁存·128×8位内部RAM·15个可编程I/O口·两个16位定时器/计数器·六个中断源·可编程串行UART（= Universal Asynchronous Receiver Transmitter通用异步收发器）通道·可直接驱动LED的输出·芯片级模仿比较器·低功耗空闲模式和微功耗模式（Power-down mode）说明A T89C2051是一种低电压、高性能的8位CMOS微型计算机。
带2K字节的闪存和可擦可编程只读存储器（EPROM）。
该器件应用爱特美尔（Atmel）的高密度非易失性技术生产，与工业级MCS51架构组相兼容。
将一片通用的8位CPU与闪存集成在单块芯片上，爱特美尔A T89C2051是一种功能强盛的微型计算机。
它为许多嵌入式控制提供了高灵活性低成本的解决方案。
A T89C2051的标准特性如下：2K字节闪存，128字节RAM，15个I/O口，两个16位定时器/计数器，一个五失量两级中断结构，一个全双工串行通信口，一个精准模拟比较器，芯片级振荡器和时钟电路。
另外，A T89C2051用静态逻辑设计，可在低至零频下工作，支持两种软件可选节能模式。
空闲模式下CPU不工作，而RAM，定时器/计数器，串口和中断系统继承工作。
微功耗模式（power-down mode)下保存RAM的内容，但冻结振荡器，禁止其它所有的芯片功能直到下一个硬件复位到来。
特定指令的限制A T89C2051是爱特美尔微控制器家族中经济划算的一款产品。
它包含2K字节的闪速程度存储器。
它与MCS-51架构完全兼容，并且可以使用MCS-51指令组来编程。
AT89S52单片机中英文对照外文翻译文献
(文档含英文原文和中文翻译)中英文资料对照外文翻译英文原文：The Description of MCUMCU DescriptionSCM is also known as micro-controller (Microcontroller Unit), commonly used letters of the acronym MCU MCU that it was first used in industrial control. Only a single chip by the CPU chip developed from a dedicated processor. The first design is by a large number of peripherals and CPU on a chip in the computer system, smaller, more easily integrated into a complex and demanding on the volume control device which. INTEL's Z80 is the first designed in accordance with this idea processor, then on the development of microcontroller and dedicated processors have parted ways.Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performance was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, because the cost is not satisfactory but have not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been the rapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90's dedicated processor, while the average model prices fall to one U.S. dollars, the most high-end [1] model only 10 dollars. Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems.SCM is more suitable than the specific processor used in embedded systems, so it was up to the application. In fact the number of SCM is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will be integrated single chip. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse with a 1-2 in both the Department of SCM. Personal computer will have a large number of SCM in the work. General car with more than 40 SCM, complex industrial control systems may even have hundreds of SCM in the same time work! SCM is not only far exceeds the number of PC and other computing the sum, or even more than the number of human beingsSingle chip, also known as single-chip microcontroller, it is not complete a certain logic chips, but to a computer system integrated into a chip. Equivalent to a micro-computer, and computer than just the lack of a microcontroller I / O devices. General talk: a chip becomes a computer. Its small size, light weight, cheap, for the study, application and development of facilities provided. At the same time, learning to use the MCU is to understand the principle and structure of the computer the best choice.SCM and the computer functions internally with similar modules, such as CPU, memory, parallel bus, the same effect as well, and hard disk memory devices, and different is its performance of these components were relatively weak many of our home computer, but the price is low , usually not more than 10 yuan you can do with it ...... some control for a class is not very complicated electrical work is enough of. We are using automatic drum washing machine, smoke hood, VCD and so on appliances which could see its shadow! ...... It is primarily as a control section of the core componentsIt is an online real-time control computer, control-line is that the scene is needed is a stronger anti-jamming ability, low cost, and this is, and off-line computer (such as home PC), the main difference.Single chipMCU is through running, and can be modified. Through different procedures to achieve different functions, in particular special unique features, this is another device much effort needs to be done, some great efforts are very difficult to do. A not very complex functions if the 50's with the United States developed 74 series, or the 60's CD4000 series of these pure hardware buttoned, then the circuit must be a large PCB board! But if the United States if the 70's with a series of successful SCM market, the result will be a drastic change! Just because you are prepared by microcomputer programs can achieve high intelligence, high efficiency and high reliability!As the microcontroller on the cost-sensitive, so now the dominant software or the lowest level assembly language, which is the lowest level in addition to more than binary machine code language, and as so low why is the use? Many high-level language has reached the level of visual programming Why is not it? The reason is simply that there is no home computer as a single chip CPU, not as hard as a mass storage device. A visualization of small high-level language program which even if only one button, will reach tens of K of size! For the home PC's hard drive in terms of nothing, but in terms of the MCU is not acceptable. SCM in the utilization of hardware resources to be very high for the job so although the original is still in the compilation of a lot of use. The same token, if the giant computer operating system and applications run up to get home PC, home PC, also can not afford to.Can be said that the twentieth century across the three "power" era, that is, the age of electricity, the electronic age and has entered into the computer age. However, this computer, usually refers to the personal computer, referred to as PC. It consists of thehost, keyboard, monitor and other components. Another type of computer, most people do not know how. This computer is to give all kinds of intelligent machines single chip (also known as micro-controller). As the name suggests, this computer system took only a minimal integrated circuit, can be a simple operation and control. Because it is small, usually hidden in the charged mechanical "stomach" in. It is in the device, like the human brain plays a role, it goes wrong, the whole plant was paralyzed. Now, this microcontroller has a very broad field of use, such as smart meters, real-time industrial control, communications equipment, navigation systems, and household appliances. Once all kinds of products were using SCM, can serve to upgrade the effectiveness of products, often in the product name preceded by the adjective - "intelligent," such as intelligent washing machines. Now some technical personnel of factories or other amateur electronics developers to engage in out of certain products, not the circuit is too complicated, that function is too simple and can easily be copied. The reason may be stuck in the product did not use a microcontroller or other programmable logic device.SCM historySCM was born in the late 20th century, 70, experienced SCM, MCU, SoC three stages.First model1.SCM the single chip microcomputer (Single Chip Microcomputer) stage, mainly seeking the best of the best single form of embedded systems architecture. "Innovation model" success, laying the SCM and general computer completely different path of development. In the open road of independent development of embedded systems, Intel Corporation contributed.2.MCU the micro-controller (Micro Controller Unit) stage, the main direction of technology development: expanding to meet the embedded applications, the target system requirements for the various peripheral circuits and interface circuits, highlight the object of intelligent control. It involves the areas associated with the object system, therefore, the development of MCU's responsibility inevitably falls on electrical, electronics manufacturers. From this point of view, Intel faded MCU development has its objective factors. In the development of MCU, the most famous manufacturers as the number of Philips Corporation.Philips company in embedded applications, its great advantage, the MCS-51 single-chip micro-computer from the rapid development of the micro-controller. Therefore, when we look back at the path of development of embedded systems, do notforget Intel and Philips in History.Embedded SystemsEmbedded system microcontroller is an independent development path, the MCU important factor in the development stage, is seeking applications to maximize the solution on the chip; Therefore, the development of dedicated single chip SoC trend of the natural form. As the microelectronics, IC design, EDA tools development, application system based on MCU SoC design have greater development. Therefore, the understanding of the microcontroller chip microcomputer can be, extended to the single-chip micro-controller applications.MCU applicationsSCM now permeate all areas of our lives, which is almost difficult to find traces of the field without SCM. Missile navigation equipment, aircraft, all types of instrument control, computer network communications and data transmission, industrial automation, real-time process control and data processing, extensive use of various smart IC card, civilian luxury car security system, video recorder, camera, fully automatic washing machine control, and program-controlled toys, electronic pet, etc., which are inseparable from the microcontroller. Not to mention the area of robot control, intelligent instruments, medical equipment was. Therefore, the MCU learning, development and application of the large number of computer applications and intelligent control of the scientists, engineers.The single-chip microcomputer AT89S52 MCU as an example, the pair for further description:AT89S52 MCUFeatures• Compatible with MCS-51 Products• 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 10,000 Write/Erase Cycles• 4.0V to 5.5V Operating Range• Fully Static Operation: 0 Hz to 33 MHz• Three-level Program Memory Lock• 256 x 8-bit Internal RAM• 32 Programmable I/O Lines• Three 16-bit Timer/Counters• Eight Interrupt Sources• Full Duplex UART Serial Channel• Low-power Idle and Power-down Modes• Interrupt Recov ery from Power-down Mode• Watchdog Timer • Dual Data Pointer• Power-off Flag • Fast Programming Time• Flexible ISP Programming (Byte and Page Mode)• Green (Pb/Halide-free) Packaging Option1.DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.2.Pin DescriptionVCC ：Supply voltage.GND ：Ground.Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, eachpin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX@ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing orclocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to exter-nal data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.3.Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.3.1 Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.3.2 Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.4.Watchdog Timer (One-time Enabled with Reset-out)The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.4.1 Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse dura-tion is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.4.2 WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.5. UARTThe UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, please click on the document link below:/dyn/resources/prod_documents/DOC4316.PDF6. Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below:/dyn/resources/prod_documents/DOC4316.PDF7. Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-lator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.7.1 Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi-tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.7.2 Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD . Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-2. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.8. Baud Rate GeneratorTimer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the fol -lowing equation.The Timer can be configured for either timer or counter operation. In most applications, it is con-figured for timer operation (CP/T2 = 0). The timer operation is Timer 2 Overflow Rate Modes 1 and 3 Baud Rates = 16different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter-rupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.9. Programmable Clock OutA 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency). To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate gen-erator and a clock generator simultaneously. Note, however, Modes 1 and 3Oscillator Frequency Baud Rate 32[65536-RCAP2H,RCAP2L]=⨯Oscilator Frequency Clock-Out Frequency=4[65536-(RCAP2H,RCAP2L)]⨯。
AT_89C51中英文翻译资料
The Introduction of AT 89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used ashighimpedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current, because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also- 2 -serves the functions of variousspecial features of the AT89C51 as listed below:RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice each- 3 -machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Out put from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.- 4 -- 5 -Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function- 6 -Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operatinglevel and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can beprogrammed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH)and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage(VCC) program enable signal. Thelow-voltage programming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming theAT89C51, the address, data and control signals should beset up according to the Flash programming mode table. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.- 7 -Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes:The sign ature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 andP3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.- 8 -AT89C51的介绍述AT89C51是一个 电压，高性能CMOS8 单片机带有4K 节的 复擦写的程序 储器 PENROM 和128 节的 数据 储器 RAM ， 种器件采用ATMEL公 的高密度 容易丢失 储技术生产，并 能够 MCS-51系列的单片- 9 -机兼容 片内含有8 中央处理器和闪烁 储单元，有较强的 能的AT89C51单片机能够被 用到 制领域中能特性AT89C51提供 的 能标准：4K 节闪烁 储器，128 节随机 数据 储器，32个I/O口，2个16 定时/计数器，1个5向 级中断结构，1个串行通信口，片内震荡器和时钟电路 另外，AT89C51 进行0HZ的静态逻辑操作，并支持 种 件的节电模式 闲散方式停 中央处理器的工作，能够允许随机 数据 储器 定时/计数器 串行通信口及中断系统继续工作 掉电方式保 随机 数据 储器中的内容，但震荡器停 工作并禁 其它所有部件的工作直到 一个复引脚 述VCC：电源电压GND：地P0口：P0口是一组8 漏极开路 向I/O口，即地址/数据总线复用口 作为输出口时， 一个管脚都能够驱动8个TTL电路 当“1”被写入P0口时， 个管脚都能够作为高阻抗输入端 P0口 能够在 问外部数据 储器或程序 储器时，转换地址和数据总线复用，并在 时激活内部的 拉电阻 P0口在闪烁编程时，P0口接收指 ，在程序校验时，输出指 ，需要接电阻P1口：P1口一个带内部 拉电阻的8 向I/O口，P1的输出缓冲级 驱动4个TTL 电路 对端口写“1”，通过内部的电阻把端口拉到高电 ， 时 作为输入口 因为内部有电阻，某个引脚被外部信 拉 时输出一个电流 闪烁编程时和程序校验时，P1口接收 8 地址P2口：- 10 -P2口是一个内部带有 拉电阻的8 向I/O口，P2的输出缓冲级 驱动4个TTL电路 对端口写“1”，通过内部的电阻把端口拉到高电 ， 时， 作为输入口 因为内部有电阻，某个引脚被外部信 拉 时会输出一个电流 在 问外部程序 储器或16 地址的外部数据 储器时，P2口 出高8 地址数据 在 问8 地址的外部数据 储器时，P2口线 的内容在整个运行期间 闪烁编程或校验时，P2口接收高 地址和其它 制信P3口：P3口是一组带有内部电阻的8 向I/O口，P3口输出缓冲故 驱动4个TTL 电路 对P3口写如“1”时，它们被内部电阻拉到高电 并 作为输入端时，被外部拉 的P3口将用电阻输出电流P3口除了作为一般的I/O口外，更重要的用途是它的第 能，如 表所示：端口引脚第 能P3.0 RXDP3.1 TXDP3.2 INT0P3.3 INT1P3.4 T0P3.5 T1P3.6 WRP3.7 RDP3口 接收一些用于闪烁 储器编程和程序校验的 制信RST：复 输入 当震荡器工作时，RET引脚出现 个机器周期 的高电 将使单片机复ALE/PROG：当 问外部程序 储器或数据 储器时，ALE输出脉冲用于锁 地址的 8 节 即使 问外部 储器，ALE 时钟震荡频率的1/16输出固定的 脉冲信 ，因 它 对输出时钟或用于定时目的 要注意的是： 当 问外部数据 储器时将跳过一个ALE脉冲时，闪烁 储器编程时， 个引脚 用于输入编程脉冲 如果 要， 对特殊寄 器区中的8EH单元的D0 置禁 ALE操作 个 置 只有一条MOVX和MOVC指 ALE才会被 用 外， 个引脚会微弱拉高，单片机执行外部程序时， 置ALE无效PSEN：程序储 允许输出是外部程序 储器的读选通信 ，当AT89C51由外部程序 储器读 指 时， 个机器周期 次PSEN 有效，即输出 个脉冲 在 期间，当 问外部数据 储器时， 次有效的PSEN 信 出现EA/VPP：外部 问允许 欲使中央处理器仅 问外部程序 储器，EA端 须保持 电 需要注意的是：如果 密 LBI被编程，复 时内部会锁 EA端状态 如EA端为高电 ，CPU则执行内部程序 储器中的指 闪烁 储器编程时，该引脚 +12V 的编程允许电压VPP，当然 须是该器件是使用12V编程电压VPPXTAL1：震荡器 相放大器及内部时钟发生器的输入端XTAL2：震荡器 相放大器的输出端时钟震荡器AT89C51中有一个用于构 内部震荡器的高增益 相放大器，引脚XTAL1和XTAL2 别是该放大器的输入端和输出端 个放大器 作为 馈元件的片外石英晶体或陶瓷谐振器一起构 自然震荡器 外接石英晶体及电容C1，C2接在放大器的 馈回路中构 并联震荡电路 对外接电容C1，C2虽然没有十 格的要求，但电容容 的大小会轻微影响震荡频率的高 震荡器工作的稳定性 起振的难易程序及温度稳定性 如果使用石英晶体， 们 荐电容使用30PF±10PF，而如果使用陶瓷振荡器建议选择40PF±10PF 用户也 采用外部时钟 采用外部时钟的电路如图示 种情况 ，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空 由于外部时钟信 是通过一个2 频触发器 作为内部时钟信 的，所 对外部时钟信 的占空比没有特殊要求，但最小高电 持续时间和最大的 电 持续时间 符合产品技术条件的要求内部振荡电路外部振荡电路闲散节电模式AT89C51有 种 用 件编程的省电模式，它们是闲散模式和掉电工作模式 种方式是 制 用寄 器PCON中的PD和IDL 来实现的 PD是掉电模式，当PD=1时，激活掉电工作模式，单片机进入掉电工作状态 IDL是闲散等待方式，当IDL=1，激活闲散工作状态，单片机进入睡 状态 如需要 时进入 种工作模式，即PD和IDL 时为1，则先激活掉电模式 在闲散工作模式状态，中央处理器CPU 保持睡 状态，而所有片内的外 保持激活状态， 种方式由 件产生 时，片内随机 数据 储器和所有特殊 能寄 器的内容保持 闲散模式 由任何允许的中断请求或硬件复 终 终 闲散工作模式的方法有 种，一是任何一条被允许中断的 件被激活，IDL被硬件清除，即刻终 闲散工作模式 程序会首先影响中断，进入中断服 程序，执行完中断服 程序，并紧随RETI指 ， 一条要执行的指 就是使单片机进入闲散工作模式，那条指 面的一条指 是通过硬件复 也 将闲散工作模式终 需要注意的是：当由硬件复 来终 闲散工作模式时，中央处理器CPU通常是 激活空闲模式那条指 的 一条开始继续执行程序的，要完 内部复 操作，硬件复 脉冲要保持 个机器周期有效，在 种情况 ，内部禁中央处理器CPU 问片内RAM，而允许 问其他端口，为了避免 能对端口产生的意外写入：激活闲散模式的那条指 面的一条指 是一条对端口或外部 储器的写入指掉电模式在掉电模式 ，振荡器停 工作，进入掉电模式的指 是最 一条被执行的指 ，片内RAM和特殊 能寄 器的内容在中指掉电模式前被冻结 出掉电模式的唯一方法是硬件复 ，复 将 新定义全部特殊 能寄 器但 改 RAM中的内容，在VCC恢复到 常工作电 前，复 无效 须保持一定时间 使振荡器 新启动并稳定工作闲散和掉电模式外部引脚状态程序 储器的 密AT89C51 使用对芯片 的 个 密 LB1，LB2，LB3进行编程 P 或 编程 U 得到如 表所示的 能：程序 密 保护类型1 U U U 没有程序保护 能2 P U U 禁 外部程序 储器中执行MOVC指 读 内部程序 储器的内容3 P P U 除 表 能外， 禁 程序校验4 P P P 除 能外， 时禁 外部执行当LB1被编程时，在复 期间，EA端的电 被锁 ，如果单片机 电 一直没有复 ，锁 起来的初始值是一个 确定数， 个 确定数会一直保 到 复 置 为了使单片机 常工作，被锁 的EA电 个引脚当前辑电 一 机密 只能通过整片擦除的方法清除编程的F真且shF真且sh通常是在AT89C51的出货 片 闪 内 阵列中删除状态 即内容=快跳频 并随时准备进行编程 编程接口 接 一个高电压 12伏 或 电压 虚拟通道连接 计划使信 .在 电压编程模式提供了一个方便的方法的程序AT89C51单片机在用户的系统，而高电压编程模式是符合常规的第 方Flash或 擦写 编程只读 储器程序员 该AT89C51单片机随 无论是高电压或 电压编程模式 AT89C51单片机 码的编程 储器阵列 节在 种编程模式 编程任何nonblank 节的片 闪 ，整个记 体 须清除使用芯片擦除模式规划算法：在编程AT89C51单片机，地址，数据和 制信 立 据Flash编程模式表 到程序的AT89C51单片机，采 面的 骤1 输入所需的内 置的地址线2 输入相 的数据 节的数据线3 激活的 确组合的 制信4 提高电子艺界/ VPP 12V的高电压编程模式5 脉冲进修/孕酮一次计划中的一个 节闪 阵列或锁定 节写周期自 通常需要的时间和 超过1.5毫秒 重复 骤1到5 ，更改地址和数据为整个阵列或到 ，对象文件达 共识数据 询：该AT89C51的数据 询 能说明结束了写周期 在写周期，一个试图读 最 节书面将导 补充书面资料 PO.7 一旦写周期已 完 ， 的数据是有效的所有输出， 一个周期开始 数据 询 开始任何时候在写周期已 开始 准备/忙：进展 节编程也 被监测的RDY /天空电视 的输出信 P3.4被拉高进修 用编程期间说明忙碌的 P3.4被拉高时再次编程 做表明准备程序验证：如果锁定 LB1和LB2尚未编程，编程 码 读 数据备份通过地址和数据线进行 查 锁定 无法验证直接 验证锁 是所 得的观测，其 能已启用 芯片擦除：整个闪 阵列抹去电通过 当的组合和 制信 举 进修/孕酮 了10毫秒 数组的 码写入 所有“ 1 ” 该芯片擦除操作 须得到执行之前的 码 储器 重新编程读 节的签 ：签 节宣读了相 的程序作为一个 常的 查工作地点030H ，031H ，并032H ，但P3.6和P3.7 须 出一个逻辑 返回的值是如030H = 1EH表明制造商031H = 51H表明基于89C51032H =快跳频表明12V的编程032H = 05H显示5V的编程编程接口一个 节的 码在闪 阵列 书面和整个阵列 被删除，使用 当的组合的 制信 写入操作周期一旦启动，将自动时间本身完。
89c51单片机英语文献翻译
有关AT89C51的介绍英文原文DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolat ile memory technology and is compatible with the industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Block DiagramVCC Supply voltage.GND Ground. Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL ) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In thisapplication it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high onthis pin for two machinecycles while the oscillator isrunning resets the device.Port pin alternate functionsP3.0 rxd (serial input port)P3.1 txd (serial output port)P3.2 ^int0 (external interrupt0)P3.3 ^int1 (external interrupt1)P3.4 t0 (timer0 external input)P3.5 t1 (timer1 external input)P3.6 ^WR (external data memory write strobe)P3.7 ^rd (external data memory read strobe)ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin orto external memory.Status of External Pins During Idle and Power Down Modesmode Program memory ALE ^psen Port0 Port1 Port2 Port3idle internal 1 1 data data data DataIdle External 1 1 float Data data Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 float data Data data Power Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:Lock Bit Protection ModesProgram lock bits Protection typeLb1 Lb2 Lb31 U U U No program lock features2 P U U Movc instructions executed from external program memory aredisable from fetching code bytes from internal memory, ^ea issampled and latched on reset, and further programming of the flashdisabled3 P P U Same as mode 2, also verify is disable.4 P P P Same as mode 3, also external execution is disabled.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that valueuntil reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash：The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.Vpp=12v Vpp=5vTop-side mark AT89C51xxxxyyww AT89C51 xxxx-5 yywwsignature (030H)=1EH(031H)=51H(032H)=FFH (030H)=1EH (031H)=51H (032H)=05HThe AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: T he entire Flash Programmable and Erasable Read Only Memory array is erasedelectrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated,will automatically time itself to completion.Table 1 Flash Programming Modesmode RST ^PSEN ALE/^PROG ^EA/Vpp P2.6 P2.7 P3.6 P3.7 Write code data H L H/12V L H H HRead code data H L H H L L H HWrite lock Bit-1 H L H/12V H H H H Bit-2 H L H/12V H H L L Bit-3 H L H/12V H L H LChip erase H L H/12V H L L L Read signature syte H L H H L L L LNote: 1.chip erase requires a 10-ms PROG pulseFigure 3. Programming the Flash Figure 4. Verifying the FlashFlash Programming and Verification CharacteristicsTA = 0°C to 70°C, VCC = 5.0 10%Symbol parameter min max Units Vpp⑴Programming enable voltage 11.5 12.5 V Ipp⑴Programming enable current 1.0 mA 1/Tclcl Oscillator frequency 3 24 MHZ Tavgl Address setup to ^PSEN low 48TclclTghax Address hole after ^PSEN 48TclclTdvgl Data setup to ^PSEN low 48TclclTghdx Data hole after ^PSEN 48TclclTehsh P2.7(^enable)high to Vpp 48TclclTshgl Vpp setup to ^PSEN low 10 us Tghsl⑴Vpp hole after ^PSEN 10 us Tglgh ^PSEN width 1 110 us Tavqv Address to data valid 48TclclTelqv ^enable low to data valid 48TclclTehqz Data float after ^enable 0 48TclclTghbl ^PSEN high to ^busy low 1.0 us Twc Byte write cycle time 2.0 ms Note: 1. Only used in 12-volt programming mode.Flash Programming and Verification Waveforms - High Voltage Mode (VPP = 12V)Flash Programming and Verification Waveforms - Low Voltage Mode (VPP = 5V)Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°CStorage Temperature ..................................... -65°C to +150°CVoltage on Any Pinwith Respect to Ground .....................................-1.0V to +7.0VMaximum Operating Voltage............................................. 6.6VDC Output Current...................................................... 15.0 mADC CharacteristicsTA = -40°C to 85°C, VCC = 5.0V 20% (unless otherwise n oted)symbo l parameter condition min max unitsVil Input low voltage (except ^EA) -0.5 0.2Vcc-0.V1Vil1 Input low voltage(^EA) -0.5 0.2Vcc-0.3VVih Input high voltage Except XTAL1,XTAL2 0.2Vcc+0.9Vcc+0.5 V Vih1 Input high voltage (XTAL1,RST) 0.7Vcc Vcc+0.5 V Vol Output low voltage⑴(ports1,2,3 )Iol=1.6mA 0.45 VVol1 Output lowvoltage⑴(port0,ALE,^PSEN) Ioh=3.2mA 0.45 V Ioh=-60uA,Vcc=-5V+10% 2.4Ioh=-25uA 0.75VccVoh Output high voltage⑴(ports1,2,3 )Ioh=-60uA,Vcc=5V+10% 0.9Vcc VVoh1 Output lowvoltage⑴(port0,ALE,^PSEN) Ioh=-800UA,Vcc=5V+10%2.4 V Ioh=-300uA, 0.75Vcc V Ioh=-80uA 0.9Vcc VIil Logical 0 input current(ports1,2,3)Vin=0.45V -50 uAItl Logical 1 to 0 transitioncurrent(ports 1,2,3)Vin=2V,Vcc=5V+10% -650 uAIli Input leakagecurrent(port 0, ^EA)0.45<Vin<Vcc 50 +10 uARRST Reset pulldown resistor 300 kom Cio Pin capacitance Testfreq=1MHZ,TA=25℃10 pF Icc Power supply current Active mode, 12MHZ 20 mAIdle mode,12MHZ 5 mA Power down mode⑵Vcc=6V 100 uAVcc=3V 40 uA Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mAMaximum IOL per 8-bit port: Port 0: 26 mAPorts 1, 2, 3: 15 mAMaximum total IOL for all output pins: 71 mA2. Minimum VCC for Power Down is 2V.AC Characteristics(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF;Load Capacitance for all other outputs = 80 pF)External Program and Data Memory CharacteristicsSymbol Parameter 12MHzOscillator16to 24 MHz Oscillator UnitsMin Max Min Max1/T CLCL Oscillator Frequency024MHz T LHLL ALE Pulse Width 127 2T CLCL-40 ns T AVLL Address Valid to ALE Low 43 T CLCL-13 ns T LLAX Address Hold After ALE Low 48 T CLCL-20 ns T LLIV ALE Low to Valid Instruction In 233 4T CLCL-65 ns T LLPL ALE Low to PSEN Low 43 T CLCL-13 ns T PLPH PSEN Pulse Width 205 3T CLCL-20 ns T PLIV PSEN Low toValid Instruction In 145 3T CLCL-45 ns T PXIX InputInstructionHold After PSEN 0 0 ns T PXIZ InputInstructionFloat AfterPSEN 59 T CLCL-10 ns T PXAV PSEN to Address Valid 75 T CLCL-8 ns T AVIV Address to Valid Instruction In 312 5T CLCL-55 ns T PLAZ PSEN Low to Address Float 10 10 ns T RLRH RD Pulse Width 400 6T CLCL-100 ns T WLWH WR Pulse Width 400 6T CLCL-100 ns T RLDV RD Low to Valid Data In 252 5T CLCL-90 ns T RHDX Data Hold After RD 0 0 ns T RHDZ Data Float After RD 97 2T CLCL-28 ns T LLDV ALE Low to Valid Data In 517 8T CLCL-150 ns T AVDV Address to Valid Data In 585 9T CLCL-165 ns T LLWL ALE Low to RD or WR Low 200 300 3T CLCL-50 3T CLCL+50 ns T AVWL Address to RD or WR Low 203 4T CLCL-75 ns T QVWX Data Valid to WR Transition 23 T CLCL-20 ns T QVWH Data Valid to WR High 433 7T CLCL-120 ns T WHQX Data Hold After WR 33 T CLCL-20 ns T RLAZ RD Low to Address Float 0 0 ns T WHLH RD or WR High to ALE High 43 123 T CLCL-20 T CLCL+25 ns External Program Memory Read CycleExternal Data Memory Read CycleExternal Data Memory Write CycleExternal Clock Drive WaveformsExternal Clock Drive符号参数最小值最大值单位1/T CLCL Oscillator024MHz FrequencyT CLCL Clock Period41.6nsT CHCX High Time15nsT CLCX Low Time15nsT CLCH Rise Time20nsT CHCL Fall Time20nsSerial Port Timing: Shift Register Mode Test Conditions(VCC = 5.0 V 20%; Load Capacitance = 80 pF)符号参数12 MHz Osc VariableOscillator UnitsMi nMaxMin MaxT XLXL Serial Port Clock CycleTime期1.0 12T CLCL usT QVXH Output Data Setup toClock Rising Edge 700 10T CLCL-133nsT XHQX Output Data Hold AfterClock Rising Edge50 2T CLCL-117 nsT XHDX Input Data Hold AfterClock Rising Edge0 0 nsT XHDV Clock Rising Edge toInput Data Valid700 10T CLCL-133 ns Shift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1)Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.Float Waveforms(1)Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH/VOL level occurs.Ordering InformationSpeed(MHz) PowerSupply Ordering Code Package Operation Range125V+20%AT89C51-12ACAT89C51-12JCAT89C51-12PCAT89C51-12QC 44A44J40P644QCommercial(0C to 70C)AT89C51-12AI AT89C51-12JI AT89C51-12PI AT89C51-12QI 44A44J40P644QIndustrial(-40C to 85C)16 5V +20%AT89C51-16ACAT89C51-16JCAT89C51-16PCAT89C51-16QC 44A44J40P644QCommercial(0C to 70C)AT89C51-16AI AT89C51-16JI AT89C51-16PI AT89C51-16QI 44A44J40P644QIndustrial(-40C to 85C)20 5V +20%AT89C51-20ACAT89C51-20JCAT89C51-20PCAT89C51-20QC 44A44J40P644QCommercial(0C to 70C)AT89C51-20AI AT89C51-20JI AT89C51-20PI AT89C51-20QI 44A44J40P644QIndustrial(-40C to 85C)24 5V +20%AT89C51-24ACAT89C51-24JCAT89C51-24PCAT89C51-24QC 44A44J40P644QCommercial(0C to 70C)AT89C51-24AI AT89C51-24JI AT89C51-24PI AT89C51-24QI 44A44J40P644QIndustrial(-40C to 85C)Package Type44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC)40P6 40 Lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)44Q 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP)P89C51 Special Function RegistersSYMBOL DESCRIPTION BYTESADDRESSBIT ADDRESS, SYMBOLACC Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 DPH Data Pointer High 83HDPL Data Pointer Low 82HIE Interrupt Enable A8H AF –- –- AC AB AA A9 A8EA ES ET1 EX1 ET0 EX0 IP* Interrupt Priority B8H –- –- –- BC BB BA B9 B8–- –- –- PS PT1 PX1 PT0 PX0 P0* Port 0 80H 87 86 85 84 83 82 81 80P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1* Port 1 90H 97 96 95 94 93 92 91 90P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0P2* Port 2 A0H A7 A6 A5 A4 A3 A2 A1 A0P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P3* Port 3 B0H B7 B6 B5 B4 B3 B2 B1 B0P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 PCON Power Control 87H 8D –- –- –- –- –- –- –-SMODPSW* Program StatusWord D0H D7 D6 D5 D4 D3 D2 D1 D0 CY AC F0 RS1 RS0 OV –- PSBUF Serial Data Buffer 99HSCON* Serial Control 98H 9F 9E 9D 9C 9B 9A 99 98SM0 SM1 SM2 REN TB8 RB8 TI RI SP Stack Pointer 81HTCON* Timer ControlControl 88H 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0TH0 Timer High 0 8CHTH1 Timer High 1 8DHTL0 Timer Low 0 8AHTL1 Timer Low 1 8BHTMOD Timer Mode 89H GATE C/^T M1 M0 GATE C/^T M1 M0 * SFRs are bit addressable.– Reserved bits.. Reset value depends on reset source.有关AT89C51的介绍描述AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
AT89C2051单片机及其引脚图的详细说明
AT89C2051单片机及其引脚图的详细说明默认分类2011-02-07 11:40:41 阅读529 评论0字号：大中小订阅AT89C2051单片机是51系列单片机的一个成员，是8051单片机的简化版。
内部自带2K字节可编程FLASH存储器的低电压、高性能COMS八位微处理器，与Intel MCS-51系列单片机的指令和输出管脚相兼容。
由于将多功能八位CPU和闪速存储器结合在单个芯片中，因此，AT89C2051构成的单片机系统是具有结构最简单、造价最低廉、效率最高的微控制系统，省去了外部的RAM、ROM和接口器件，减少了硬件开销，节省了成本，提高了系统的性价比。
AT89C2051是一个有20个引脚的芯片，引脚配置如图3所示。
与8051相比，AT89C2051减少了两个对外端口（即P0、P2口），使它最大可能地减少了对外引脚下，因而芯片尺寸有所减小。
AT89C2051芯片的20个引脚功能为：VCC 电源电压。
GND 接地。
RST 复位输入。
当RST变为高电平并保持2个机器周期时，所有I/O引脚复位至“1”。
XTAL1 反向振荡放大器的输入及内部时钟工作电路的输入。
XTAL2 来自反向振荡放大器的输出。
P1口8位双向I/O口。
引脚P1.2～P1.7提供内部上拉，当作为输入并被外部下拉为低电平时，它们将输出电流，这是因内部上拉的缘故。
P1.0和P1.1需要外部上拉，可用作片内精确模拟比较器的正向输入（AIN0）和反向输入（AIN1），P1口输出缓冲器能接收20mA电流，并能直接驱动LED显示器；P1口引脚写入“1”后，可用作输入。
在闪速编程与编程校验期间，P1口也可接收编码数据。
P3口引脚P3.0～P3.5与P3.7为7个带内部上拉的双向I/0引脚。
P3.6在内部已与片内比较器输出相连，不能作为通用I/O引脚访问。
P3口的输出缓冲器能接收20mA的灌电流；P3口写入“1”后，内部上拉，可用输入。
P3口也可用作特殊功能口，其功能见表1。
单片机AT89C2051中文资料
单片机AT89C2051中文资料（1）2007-04-05 09:52AT89C205189C2051是由ATMEL 公司推出的一种小型单片机。
95年出现在中国市场。
其 主要特点为采用Flash 存贮器技术，降低了制造成本，其软件、硬件与 MCS-51 完全兼容，可以很快被中国广大用户接受，其程序的电可擦写特性，使得开发 与试验比较容易。
1引脚89C2051共有20条引脚，详见图1.从图中可见，2051继承了 8031最重要引脚：rill ®tS06H1W>iP1 口共8脚，准双向端口。
P3.0〜P3.6共7脚，准双向端口，并且保留了全部的 P3的第二功能，如P3.0、 P3..1的串行通讯功能，P3.2、P3..3的中断输入功能，P3.4、P3.5的定时器输入功 能。
在引脚的驱动能力上面，89C2051具有很强的下拉能力，P1,P3 口的下拉能力均 可达到20mA.相比之下，89C51/87C51的端口下拉能力每脚最大为 15mA 。
但是 限定9脚电流之和小于71mA.这样，引脚的平均电流只 9mA 。
89C2051驱动能 力的增强，使得它可以直接驱动 LED 数码管。
为了增加对模拟量的输入功能，2051在内部构造了一个模拟信号比较器，其输 入端连到P1.0和P1.1 口，比较结果存入 P3.6对应寄存器，（P3.6在2051外部 无引脚），原理见图2。
对于一些不大复杂的控制电路我们就可以增加少量元件来实现，例如，对温度 的控制，过压的控制等。
图3为测量示意图。
其中，R 用于测量门限的调节，IN 端接输入模拟信号。
2电源89C2051有很宽的工作电源电压，可为2.7〜6V,当工作在3V 时，电流相当于6V 工作时的1/4。
89C2051工作于12Hz 时，动态电流为 5.5mA ，空闲态为1mA, 掉电态仅为20nA 。
这样小的功耗很适合于电池供电的小型控制系统。
3存储器89C2051片内含有2k 字节的Flash 程序存储器，128字节的片内RAM,与80C31 内部完全类似。
AT 89C51中英文翻译资料
The Introduction of AT 89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used ashighimpedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current, because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also- 2 -serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each- 3 -machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Out put from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.- 4 -Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function- 5 -Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH)and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage(VCC) program enable signal. The- 6 -low-voltage programming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming theAT89C51, the address, data and control signals should beset up according to the Flash programming mode table. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.- 7 -Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written w ith all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes:The sign ature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 andP3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.- 8 -AT89C51的介绍描述AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。
AT89C2051单片机及其引脚图的详细说明
AT89C2051单片机及其引脚图的详细说明默认分类2011-02-07 11:40:41 阅读529 评论0字号：大中小订阅AT89C2051单片机是51系列单片机的一个成员，是8051单片机的简化版。
内部自带2K字节可编程FLASH存储器的低电压、高性能COMS八位微处理器，与Intel MCS-51系列单片机的指令和输出管脚相兼容。
由于将多功能八位CPU和闪速存储器结合在单个芯片中，因此，AT89C2051构成的单片机系统是具有结构最简单、造价最低廉、效率最高的微控制系统，省去了外部的RAM、ROM和接口器件，减少了硬件开销，节省了成本，提高了系统的性价比。
AT89C2051是一个有20个引脚的芯片，引脚配置如图3所示。
与8051相比，AT89C2051减少了两个对外端口（即P0、P2口），使它最大可能地减少了对外引脚下，因而芯片尺寸有所减小。
AT89C2051芯片的20个引脚功能为：VCC 电源电压。
GND 接地。
RST 复位输入。
当RST变为高电平并保持2个机器周期时，所有I/O引脚复位至“1”。
XTAL1 反向振荡放大器的输入及内部时钟工作电路的输入。
XTAL2 来自反向振荡放大器的输出。
P1口8位双向I/O口。
引脚P1.2～P1.7提供内部上拉，当作为输入并被外部下拉为低电平时，它们将输出电流，这是因内部上拉的缘故。
P1.0和P1.1需要外部上拉，可用作片内精确模拟比较器的正向输入（AIN0）和反向输入（AIN1），P1口输出缓冲器能接收20mA电流，并能直接驱动LED显示器；P1口引脚写入“1”后，可用作输入。
在闪速编程与编程校验期间，P1口也可接收编码数据。
P3口引脚P3.0～P3.5与P3.7为7个带内部上拉的双向I/0引脚。
P3.6在内部已与片内比较器输出相连，不能作为通用I/O引脚访问。
P3口的输出缓冲器能接收20mA的灌电流；P3口写入“1”后，内部上拉，可用输入。
P3口也可用作特殊功能口，其功能见表1。
中英文翻译 AT89C52 单片机
AT89C2051AT89C2051 Reference Manual AT89C2051 is made in the ATMEL Corporation, which is the low-voltage, high-performance CMOS8-bit microcontroller.Tablets containing repeated 2k bytes of program memory erasable read-only (PEROM) and random 128bytes data memory (RAM), device using ATMEL's high density, non-volatile memory technology, Compatible with the standard of MCS-51 instruction set, built-chip 8-bit general-purpose central processing unit and repeatedly write the Flash memory, which can effectively reduce the development costs. AT89C2051 features a powerful single-chip can provide cost-effective in many Applications.AT89C2051 MCU MCU is a series of 51 members, is the 8051 version of SCM. Internal comes with a programmable EPROM 2 k bytes of high-performance microcontrollers. With the industry standard MCS-51 orders and pin-compatible, so it is a powerful micro-controllers, many embedded control applications, it provides a highly flexible and effective solutions. AT89C2051 has the following characteristics: 2 k bytes EPROM, 128 bytes RAM, 15 I / O lines, two 16 regular / counter, two five vector interrupt structure, a full two-way serial port, and includes Precision analog comparator and on-chip oscillator, a 4.25 V to 5.5 V voltage scope of work and 12 MHz/24MHz frequency, and also offers the encryption array of two program memory locking, power-down and the clock circuit. In addition, AT89C2051 also supports two kinds of software-selectable power-saving mode power supply. During my free time, CPU stop and let RAM, timing / counter, serial port and interrupt system to continue to work. Power-down can preserve the contents of RAM, but will stop oscillator chip-to prohibit all the other functions until the next hardware reset.AT89C2051 have two 16 time / counter register Timer0t Timer1. As a timer, each machine cycle register an increase, such registers to counting machine cycle. Because a machine cycle is 12 oscillator cycles, the count rate is the frequency oscillator 1 / 12. As a counter, the register in the corresponding external input pin P3.4/T0 and P3.5/T1 emerged from the 1-0 when the changes by 1. Two machine cycle because of the need to identify a 1-0 change, the largest count rate is the frequency oscillator 1 / 24, the external input P3.2/INT0 and P3.3/INT1 programming, for Measuring the pulse width of the door.Therefore, AT89C2051 constitute the SCM system is a simple structure, the costof the cheapest, most efficient micro-control system, eliminating the external RAM, ROM and interface devices, reducing hardware costs, cost savings, improved The cost-effective system.Clock circuitMCU clock signal used to provide various micro-chip microcontroller operation of the benchmark time, the clock signal is usually used by the form of two circuits: the internal and external shocks oscillation. MCS-51 has a microcontroller internal oscillator for a reverse of the high-gain amplifier, pin XTALl and XTAL2 are here to enlarge the electrical inputs and outputs, as in-house approach, a simple circuit, from the clock Signal relatively stable, and actually used often in this way, as shown in Figure 3-1 in its external crystal oscillator (crystal) or ceramic resonator constituted an internal oscillation, on-chip high-gain amplifier and a reverse Feedback components of the chip quartz crystal or ceramic resonator together to form a self oscillator and generate oscillation clock pulse. Figure 3-1 in the external crystal and capacitors C1 and C2 constitute a parallel resonant circuits, their stability from the oscillation frequency, rapid start-up role, and its value are about 33 PF, crystal frequency of elections 12 MHz.Reset CircuitIn order to initialize the internal MCU some special function register to be reset by the way, will reset after the CPU and system components identified in the initial state, and from the initial state began work properly. MCU is reset on the circuit to achieve, in the normal operation of circumstances, as long as the RST-pin on a two machine cycle time over the high, can cause system reset, but if sustained for the RST-pin HIGH, in a circle on the MCU reset state. After the system will reset input / output (I / 0) home port register for the FFH, stack pointer SP home for 07 H, SBUF built-in value for the indefinite, all the rest of the register-0, the status of internal RAM from the impact of reduction, On the system, when the contents of RAM is volatile. Reset operation There are two situations in which a power-on reset and manual (switch) reduction. The system uses a power-on reset mode. Figure 3-1 in the R0 and C0 formed a power-on reset circuit, and its value for R for 8.2 K, C for the 10 uF.Main features:Compatible the MCS51 command system;Contains the 2KB memory re-programming FLASH (1000);Picture one the pin of AT89C2051AT89C2051’s functional description:VCC: Power Supply V oltageGND: landP1 port: P1 mouth is a group of 8-bit bi-directional I / O interface, P1.2 ~ P1.7 provide internal pull-up resistor,P1.0 and P1.1 internal supreme pull-up resistor. P1 mouth output buffer can absorb the current 20mA and direct-drive LED.When Programming and calibration, P1 mouth as the eighth address receive.P3 mouth: P3 port P3.0 ~ P3.5, P3.7 is the internal pull-up resistor with the seven bi-directional I / O interface. Did not bring out the P3.6，It as a generic I / O port, but can not visit. Can be used as a fixed-chip input comparator output signal. when P3 write 1, they were highed the internal pull-up resistor can be raised as an input port.P3 port special function as shown in table 1:Table 1 P3 mouth’s special featuresPIN functional characteristics20191817161514131211GND P3.5P3.4P3.3P3.2XTAL1XTAL2P3.1P3.0RST P3.7P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7VCC 12345678910RST：Reset output. When the oscillator device reset, RST pin to maintain the high level of two machine cycle time.XTAL1: the RP-oscillator amplifier and internal clock generator input.XTAL2: RP-oscillator output amplifier.TimerOverview of the Timer89C2051 single-chip-chip has two 16-bit timer / counter, That is the timer 0 (T0) and Timer 1 (T1). They all have from time to time and event count function, Can be used for timing control, delay of external events, such as counting and testing occasions. Timer’s T0 and T1—— two 16-bit timers in fact is 16-bit counter plus 1. Among them, T0 compositioned by the two 8-bit special function registers TH0 and TL0; T1 posed by the TH1 and TL1. These functions were controled by the special function registers TMOD and TCONWhen set to the work in the timing, Through the pin count of the external pulse signal. When the input pulse signal generated by the falling edge of 1-0, The value of timer plus 1. At of every machine cycle during the S5P2 sampling pin T0 and T1 the input level, if a machine cycle before sample value of 1, The next machine cycle sampling value is 0, The counter plus 1. Since then during S3P1 of the machine cycle, New value will into the counter.so Detection of a 1-0 transition of the two machine cycles,So The maximum count frequency of oscillation frequency of 1 / 24. In addition to the option of work from time to time or count,Each timer / counter have four kinds of work mode, That is, each of timer circuit kinds of four constitute a structural modelTwo low-power modeIdle modeIn idle mode, CPU to maintain sleep and all-chip peripherals remain active, this way generated in Software, At this point, Chip RAM and all the contents of special function registers remain unchanged. Idle mode was terminated by any interrupt request permission to or hardware reset.P1.0 and P1.1 ,in the non-use of external pull-up resistor on the case should be set to "0", Or in the use of pull-up resistor is set to "1."It should be noted that: when uses of hardware reset Termination idle mode, AT89C2051 is usually stopped from the program until the internal reset control of the two machine cycles before the restore procedure Service. In this case the hardware within the prohibition of the reading and writing of internal RAM, However, to allow access to ports, To eliminate the Hardware reset in the idle mode of port accidents may write, In principle, to enter the idle mode of instruction should not be under the command of a pin or an external memory port for a visit.Power-down modeIn power-down mode, the oscillator to stop working, enter the power-down mode ,Instructions, who was the last one, the implementation of the Directive, Chip RAM and all the contents of special function registers the termination of the previous power-down mode be frozen. To withdraw from power-down mode is the only way to reset the hardware, Reset will redefine all the Special Function Registers but Does not change the contents of RAM before the the Vcc work returned to normal levels Shall be null and void and must be reset to maintain a certain period of time in order to restart and oscillator stabilityP1.0 and P1.1 in the non-use of external pull-up resistor on the case should be set to "0", Or in the use of pull-up resistor is set to "1."OscillatorOscillator connected clientXTAL1: RP-oscillator amplifier and internal clock generator inputXTAL2: RP-oscillator amplifier outputCharacteristics of OscillatorXTAL1, XTAL2 ware the RP-chip oscillator amplifier inputs and outputs, Quartzcrystal can be composed of the clock oscillator or ceramic oscillator, For more information from the external input clock driver AT89C2051, XTAL1 input clock signal from, XTAL2 should be left vacant.As the input to the internal circuit is a 2-flip-flop, Therefore, the external clock signal input without special requirements, However, it must comply with the maximum level and minimum norms and timing中文翻译：AT89C2051AT89C2051数据参考手册AT89C2051是美国ATMEL公司生产的低电压、高性能CMOS8位单片机，片内含2k bytes的可反复擦写的只读程序存储器（PEROM）和128bytes的随机数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51指令系统，片内置通用8位中央处理器和可反复擦写的Flash存储器，可有效地降低开发成本。
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AT89C2051
主要性能参数：
与MCS-51产品指令系统完全兼容
1．2k字节可重擦写闪速存储器
2.1000次擦写周期
3.2.7—6V的工作电压范围
4.全静态操作：OHz—24MHz
5.两级加密程序存储器
6.128x8字节内部RAM
7.15个可编程I/O口线
8.两个16位定时/计数器
9.6个中断源
10.可编程串行UART通道
11.可直接驱动LED的输出端口
12.内置一个模拟比较器
13.低功耗空闲和掉电模式
功能特性概述
A T89C2051提供以下标准的功能：2k字节Flash闪速存储器，128字节内部RAM,15个I/O 口线，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，内置一个精密比较器，片内振荡器及时钟电路。
同时，AT89C2051可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。
空闲方式停止CPU的工作，但振荡器停止工作并禁止其他所有部件工作直到下一个硬件复位。
方框图
引脚功能说明：
Vcc:电源电压
GND: 地
P1口：p1口是一组8位双向I/O口，P1.2~P1.7提供内部上拉电阻，P1.0和p1.1内部无上拉电阻，主要考虑他们分别是内部精密比较器的相同输入器（AINO）和反相输入端（AINI）,如果需要应在外部接上拉电阻。
P1口输入缓冲器可吸收20mA电流并可直接驱动LED当P1口引脚写入“1”时可作输入端，当引脚P1.2~P1.7用作输入并被外部拉低时，他们将因为内部的上拉电阻位输出电流（In）。
P1口还在flash闪速编程及程序校验时接收代码数据。
P3口：P3口的P3.0~P3.5、P3.7是带有内部上拉电阻的7个双向I/O口。
P3.6没有引出，它作为一个通用的I/O口淡并不可以访问，但可以作为固定输入片内比较器的输出信号，P3.口缓冲器可吸收20mA电流。
当P3口写入“1”时，他们被内部上拉电阻拉高并可作为输入端口。
作为输入端是，被外部拉低的P3口将用上拉电阻输出电流（In）。
P3口还用于实现AT89C2051特殊的功，如下表所示：
P3口还接收一些用于flash闪速编程及程序校验的控制信号。
RST:复位输入。
RST引脚一旦变成两个机器周期以上高电平，所有的I/O 口都将复制到“1”（高电平）状态，振荡器正在工作时，持续两个机器周期以上的高电平便可以王城复位，没个机器周期为12个振荡时钟周期。
XTAL1：振荡器反相放大器的内部时钟发生器的输入端。
XTA12：振荡器反相放大器的输出端。
振荡器的特征：
XTAL1、XTAL2为片内振荡器的反相放大器的输入或输出端，如下图所示。
可采用石英晶体或陶瓷振荡器振荡器组成时钟振荡器，如需从外部输入时钟驱动A T89C2051，时钟信号从XTAL1、XTAL2应悬空。
由于输入到内部电路是经过一个2分频触发器，所有输入的外部时钟信号无需特殊要求，但它必须符合电平的最大和最小值及时时序规范。
某些指令的约束条件：
A89C2051是经济型低价位的微控制器，它含有2k字节的flash闪速程序存储器，指令系统与MCS—51完全兼容，可使用MCS—51指令系统对其进行编程。
但是在使用某些有关指令进行编程时程序员须注意一些事项。
和跳转或分支有关的指令有一定的空间约束，使目的地址能安全落在A89C2051的2k 字节的物理程序存储器空间内，程序员必须注意这一点。
对于2K字节存储器的A89C2051来说，LJMP E0H是一条有效指令，而LJMP 900H则无效指令。
1.分支指令
对于LCALL、LJMP、ACALL、AJMP、JMP、MP@+DPTR等指令，只要程序员记住这些分支指令的目的地址在程序存储器大小的物理范围内，这些无条件分支指令就会正确执行，超出物理空间的限制会出现不可预知的程序出错。
JZ、NZ、CJB 等这些条件转移指令的使用与上述原则一样。
2 . 与MOVX相关的指令，数据存储器
A89C2051包含128字节内部数据存储器，这样，A89C2051的堆深度局限于内部RAM的128字节范围内，它既不支持外部数据存储器的访问，也不支持外部程序存储器的执行，因此程序中不应有MOVX指令。
程序存储器的加密：
A89C2051可使用对芯片上的两个加密位进行编程或不编程得到下表所示功能：
空闲模式：
在空闲模式下，CPU保持睡眠状态而所有片内的外设保持激活状态，这种方式有软件产生。
此时RAM和所有特殊功能寄存器的内容保持不变。
掉电模式：
在掉电模式下，振荡器停止工作，进入点点模式的指令时最后一条指令。
Flash闪速存储器的编程：
在擦出状态下用2k字节的片内PEROM带码存储进行封装微控制器，其程序存储器是可反复编程的。
数据查询：
AT89C2051具有写周期节航速的数据查询功能，在写周期期间，对最后写入的字节尝试读将令P1.7上写入数据的炒作结束。
当写周期完成，全部输出端的数据有效。
编程接口：
Flash闪速中的每一带码字节进行写入切整个存储器可在控制信号的正确组合下进行擦除。
11。