51单片机外文文献
基于51单片机步进电机毕业设计外文资料原文与译文
外文原文Stepping motor application and controlStepping motor is an electrical pulse will be converted into angular displacement of the implementing agencies.Put it in simple language-speaking:When the stepper drive pulse signal to a receiver,it drives stepper motor rotation direction by setting a fixed point of view(and the step angel).You can control the number of pulses to control the amount of angular displacement,so as to achieve the purpose of accurate positioning;At the same time,you can by controlling the pulse frequency to control the motor rotation speed and acceleration,so as to achieve the purpose of speed.Stepping motor directly from the AC-DC power supply,and must use special equipment-stepper motor drive. Stepping motor drive system performance,in addition to their own performance with the motor on the outside.but also to a large extent depend on the drive is good or bad.A typical stepper motor drivesystem is operated by the stepper motor controller,stepper motor drives and stepper motor body is composed of therr parts. Stepping motor controller stepper pulse and direction signal,each made of a pulse,stepper motor-driven stepper motor drives a rotor rotating step angle,that is,step-by=step further.High or low speed stepper motor,or speed,or deceleration,start or stop pulses are entirely dependent on whether the level or frequency.Decide the direction of the signal controller stepper motor clockwise or counterclockwise rotation. Typically,the stepper motor drive circuit from the logic control,power driver circuit,protection circuit and power components. Stepping motor drive controller,once received from the direction of the signal and step pulse,the control circuit on a pre-determined way of the electrical power-phase stepper motor drive controller,once received from the direction of the signal and step pulse,the control circuit on a pre-determined way of the electrical power=phase stepper motor excitation windings of the conduction or cut-off signal.Control circuit output signal power amplifier,which is stepper motor driven power drive part.Power stepper motor drive circuit to control the input current winding to form a space for rotating magnetic filed excitation,the rotor-driven movement.Protection circuit in the event of short circuit,overload,overheating,such as failure to stop the rapid and motor.Motor is usually for the permanent rotor,when the current flows through the stator windings,the stator windings produce a magnetic field vector.The magnetic field will lead to a rotor angle of rotation,making a pair of rotor and stator magnetic field direction of the magnetic field direction.When the stator rotating magnetic field vector from a different angle.Also as the rotor magnetic field to a point of view,An electrical pulse for each input,the motor rotation angle step,Tts output and input of the angular displacement is proportional to the pulses,with pulse frequency proportional to speed.Power to change the order of winding,the electrical will be reversed.We can,therefore,control the pulse number,frequency and electrical power windings of each phase to control the order of rotation of stepper motor.Stepping motor types:Permanent magnet(PM).Magnetic generally two-phase stepper,torque and are smaller ab=nd generally stepping angle of 7.5 degrees or 15 degrees;put more wind for air-conditioning. Reactive (VR),the domestic general called BF,have a common three-phase reaction,step angle of 1.5 degrees;also have five-phase reaction.Noise,no torque has been set at a large number of out.Hybrid(HB),conmmon two-phase hybrid,five-phase hybrid,therr-phase hybrid,four-phasehybrid,two-phase can be common with the four-phase drive,five-phase ,three-phase must be used with their drives;Two-phase, four-phase hybrid step angle is 1.8 degrees more than a small size,great distance,and low noise;Five-phase hybrid stepping motor is generally 0.72,the motor step angle small,high resolution,but the complexity of drive circuits,wiring problems,such as the 5-phase system of 10 lines.Three-phase hybrid stepping motor step angle of 1.2 degrees,but according to the use of 1.8 degrees,the three-phase hybrid more pole will help electric folder symmetric angle,it can be more than two-phase,five-phase high accuracy,the error even smaller,run more smoothly. Stepper motor to maintain torque:stepper motor power means no rotation,the stator locked rotoe torque.It is a stepper motor,one of the most important parameters,usually in the low-speed stepper motor torque at the time of close to maintain the torque.As the stepper motor output torque increases with the speed of constant attention,the output power also increases with the speed of change,so as to maintain torque on the stepper motor to measure the parameters of one of the most important.For example,when people say that the stepper motor 2N.m,in the absence of special circumstances that means for maintaining the torque of the stepper motor 2N.m.Precision stepper motoes:stepper motor step angle accuracy of 3-5%,not cumulative. Stepper motor to allow the minimum amount of surface temperature: Stepper motor causes the motor remperature is too high the first magnetic demagnetization,resulting in loss of torque dowm even further,so the motor surface temperature should be the maximum allowed depending in the motor demagnetization of magnetic material pints; enerally speaking,the magnetic demagnetization points are above 130 degrees Clesius,and some even as high as 200degrees Celsius,so the stepper motor surface temperature of 80-90 degrees Celsius is normal. Start frequency of no-load:the stepper motor in case of no-load to the normal start of the pulse frequency,if the pulse frequency is higher than the value of motor does not start,possible to lose steps or blocking.In the case of the load,start frequency should be to accelerate the process,that is ,the lower frequency to start,and then rose to a certain acceleration of the desired frequency (motor speed from low rise to high-speed).Step angle:that is to send a pulse,the electrical angle corresponding to rotation.Torque positioning: positioning torque stepper motor does not refer to the case of electricity,locked rotor torque stator.Operating frequency:step-by-step stpper motor can run without losing thehighest frequency. Subdivision Drive: stepper motor drives the main aim is to weaken or eliminate low-frequency vibration of the stepper motor to improve the accuracy of the motor running.Reduce noise.If the step angle is 1.8 degrees(full step) the two-phase hybrid stepping motor,if the breakdown of the breakdown of the number of drives for the 8,then the operation of the electrical pulse for each resolution of 0.072 degrees,the precision of motor can reach or close to 0.225 degrees,also depends on the breakdown of the breakdown of the drive current control accuracy and other factors,the breakdown of the number of the more difficult the greater the precision of control.中文步进电机应用和控制步进电机是将电脉冲转换成角位移的执行机构。
外文文献翻译- 基于单片机的频率计设计本科学位论文
原文：This design take at MCS-51 monolithic integrated circuit as the core full use hardware source design's one kind of frequency meter, this frequency meter will be measured first that signal enlargement reshaping processing, turns satisfies TTL/which the monolithic integrated circuit I/O mouth accepts the CMOS compatible signal from monolithic integrated circuit's T1 input port input direct summation pulse number, the monolithic integrated circuit interior timer fixed time is 1S, by now accumulated the pulse number namely for is measured the signal the frequency. Finally passes through monolithic integrated circuit processing to deliver to the lcd liquid crystal display monitor demonstration.Central Processing Unit DesignsThe CPU is the key component of a digital computer. Its purpose is to decode instruction received from memory and perform transfers, arithmetic, logic, and control operations with data stored in internal registers, memory, or I/O interface units. Externally, the CPU provides one or more buses for transferring instructions, data, and control information to and from components connected to it. In the generic computer at the beginning of chapter 1, the CPU is a part of the processor and is heavily shaded. CPUs, however, may also appear in computers. Small, relatively simple computers called microcontrollers are used in computers and in other digital systems to perform limited or specialized tasks. For example, a microcontroller is present in the keyboard and in the monitor in the generic computer; thus, these components are also shaded. In such microcontrollers, the CPU may be quite different from those discussed in this chapter. The word lengths may be short (say, four or eight bits),the number of registers small, and the instruction sets limited. Performance, relatively speaking, is poor, but adequate for the task. Most important, the cost of these microcontrollers is very low, making their use cost effective.In the following pages, we consider two computer CPUs, one for a complex instruction set computer (CISC) and the other for a reduced instruction set computer (RISC). After a detailed examination of the designs, we compare the performance of the two CPUs and present a brief overview of some methods used to enhance that performance. Finally, we relate the design ideas discussed to general digital system design.1、T he complex instruction set computerThe first design we present is for a complex instruction set computer with a non-pipelined datapath and microprogrammed control unit. We begin by describing the instruction set architecture, including the CPU register set, instruction formats, and addressing modes. TheCISC nature of the instruction set architecture is demonstrated by its memory-to-memory access for data manipulation instructions, eight addressing modes, two instruction format lengths, and instructions that require significant sequences of operations for their execution.We design a datapath for implementing the CISC architecture. The datapath is based on the one initially described in Section 7-9 and incorporated into a CPU in section 8-10. modifications are made to the register file, the function unit, and the buses to support the present instruction set architecture.Once the datapath has been specified, a control unit is designed to complete the implementation of the instruction set architecture. The design of the control unit must involve a coordinated definition of both the hardware organization and the microprogram organization. In particular , dividing the microprogram into microroutines, while at the same time designing the sequencer with which they interact, is a key part of the design. Even the instruction fields and opposed are tied to this coordinated effort. Following the definition of the hardware and microcode organizations, we detail essential parts of the microcode and the microroutines for representative operations.Instruction set architectureFigure 10-1 shows the CISC register set accessible to the programmer. All registers have 16 bits. The register file has eight registers, R0 though R7.R0 is a special register that always supplies the value zero when it is used as a source and discards the result when it is used as a destination.In additional to the register file, there is a program counter PC and stack pointer SP. The presence of a stack pointer indicates that a memory stack is a part of the architecture . the final register is the processor status register PSR, which contains information only in its rightmost the five bits; the remainder of the register is assumed to contain zero. The PSR contains thefour stored status bit values Z,N,C,and V in positions 3 through 0, respectively. In additional, a stored interrupt enable bit EI appears in position 4.Table 10-1 contains the 42 operations performed by the instructions. Each operation has a mnemonic and a carefully selected oppose. The operations are divided into four groups based on the number of explicit operands and whether the operation is branch. In addition, the status bits affected by the operation are listed.Figure 10-2 gives the instruction formats for the CPU. The generic instruction format has five fields. The first, OPCODE, specifies of the operation. The next two, MODE and S , are used to determine the addresses of the operands. The last two fields, SRC and DST, are the 3-bit source register and destination register address fields, respectively. In addition, there is an optional second word W that appears with some instructions as an operand or an address, but not with others.The first two bits of OPCODE, IR(15:14), determine the number of explicit operands and how the fields of the format are used. When these bits are 00,either no operand is required or the location of the operand is implied by OPCODE. Only the OPCODE field is needed, as shown in figure 2(b).the four rightmost OPCODE bits can specify up to 16 operands or with implied operand addresses.If IR(15:14) is 01, the instruction has one operand and is a data transfer or data manipulation instruction. Since there is an operand, the MODE field specifies the addressing mode for obtaining it. The single address may involve the DST register address in its formation, so the DST field is also present. The S field and SRC field relate to the presence of two operands and so are not used for the typical single operand instructions. but, the shift instructions require a shift amount to indicate how many bits to shift. For maximum flexibility,this shift amount is treated just like a source operand. As a consequence, the SHA and S fields is a full 16-bit operand, but only values 0 through 15 are meaningful. There are sufficient OPCODE bits for 16 instructions with a single operand.Table 10-2 gives the addressing modes specified by the MODE field. The first two bits of MODE specify four different types of addressing: register, immediate, indexed, and relative to the PC. The third bit of MODE specifies whether the address generated by these modes is used as an indirect address. The one exception to this is direct addressing, which is obtained by applying indirection to the immediate type. Otherwise, if the third bit equals 0, indirect addressing does not apply whereas, if it equals 1, indirect addressing does apply. For the register type of instruction, MONE(2:1)=00 and the W word is not needed. Since the operand or address comes from a register. The third column of the table provides register transfer statements for each of the addressing modes for the one-operand instructions.If IR(15:14) is equal to 10, then the instruction has two addresses used for true operands. All fields of the generic instruction, including S and SRC, are used for this case for all instructions. one of addresses, either the source or the destination, uses the addressing modes. If S=0, then the source uses the addressing mode specified by MODE, and the source is a register. If S=1, then the destination uses the addressing mode, and the source is a register. Register transfer descriptions of the resulting addresses are given in the fourth and fifth columns of Table 2. Again, depending on the contents of the MODE field, the second instruction word W, which is an address or an immediate operand, may or may not be present.Instructions with IR(15:14)=11 are branches. Aside form the S field and the SHA field for shifts, the format is the same as for IR(15:14)=01. For all instructions of this type, the destination address (not the operand) becomes the new address placed in the program counter PC. As a consequence, the register mode is invalid for branch instructions.Before proceeding to the next step, which defines the datapath to support the instruction set architecture, we will briefly note the characteristics of the architecture that define it as CISC or RISC. Most of the operations given in Chapter 9 are included in the instruction set. A number of operations that do not appear are redundant. The same actions can be achieved by using proper addressing modes with instructions that do appear. For example, LD, ST, IN, and OUT can all be achieved by using MOVE instructions in a memory-mapped structure. By looking at the formats for the instructions, we find that most of the instructions can operate directly on operate directly on operands from memory. There are eight addressing modes and two different lengths of instruction formats. In addition, some of the instructions perform complex operations which can be viewed as operations that are likely to take more than one clo ck cycle for the execution step. These characteristics clearly identify this as a CISC architecture.Datapath organizationRather than beginning from scratch, we will reuse the non-pipelined datapath employed with the microprogrammed control in section 8-10, with modifications. That datapath was shown in section 8-10, and the new, modified datapath based on it is given in Figure 10-6. we treat each modification in turn, beginning with the register file.In section 8-10, register R8 was used as a temporary storage location. In the new microprogrammed architecture, there are complex instructions spanning many clock cycles and performing complicated operations. Thus, more temporary storage is needed for use by the microprograms. To meet this need, we expand the register file from 9 registers to 16. the first 8 registers, R0 through R7, are visible to the computer programmer. The second 8 registers, R8 though R15 , are used as temporary storage for the microprogram operands and are hidden from the programmer. Figure 10-3 provides a map of the expanded register file with the temporary registers shaded. As indicated previously, register R0 supplies the constant 0. registers R1 through R7 are available to the programmer for use, and registers R8 through R15 provide general temporary storage for use by microprograms, the last four registers, R12 though R15, have special uses: to keep the microcode simple, standard locations are essential for storing the operands and addresses used by execution microcode for most instructions. thus ,R12 is the location for the source address(SA), R13 for the source data (SD), R14 for the destination address(DA), and R15 for the destination data(DD).We cannot access the eight temporary registers based on the 3-bit register address available in the instruction. To deal with this problem, we provide, first, 4-bit register address from the microinstruction, and second, a microinstruction bit to choose between these addresses and those from the instruction. In addition, the flexibility to allow the register addressed by DST to be a source and by SRC to be a destination is needed to permit results ofoperations to be placed directly in memory. To accomplish these goals, we modify the register file by adding the logic shown in Figure 10-4(a). the instruction set architecture uses two addresses, one for a source a operand and the other for the other source as well as the destination. The register file uses the B address for a source, and the A and D addresses on the file are connected together, giving the same address for the other source and the destination. Although this reduction from three to two addresses is not essential at the mincroinstruction level, it decrease the number of bits needed for register addresses in the microinstruction and matches the use of the register fields in the instruction formats.A quad 2-to-1 multiplexer is attached to each of the two address inputs to the register file, to select between an address from the microinstruction and an address from the instruction. There is a 5-bit field in the microinstruction for the combined destination and source address DSA, in addition to a 5-bit field for theB address SB. The first bit of each of the these fields selects between the register file address in the microinstruction(0) and the register file address in the instruction(1). If an instruction address is selected, whether it is DST or SRC is determined by an additional quad 2-to-1 multiplexer. This multiplexer is controlled by the second bit of the DSA or SB fields, depending on which of them has 1 in the first bit in any microinstruction, thereby ensuring that the proper second bit is used to determine the register address. A 0 is appended to the left of the 3-bit fields DST and SRC to cause them to address R0 through R7. the addition to the first bit, which selects the address source, the addresses from the microinstruction contain four bits so that all 16 registers can be reached. The final change to the register file is to replace the storage elements for R0 in the file with open circuits on the lines that were their inputs and with constant zero valves on the lines that were their outputs. A symbol for the resulting register file is show in Figure 10-4(b).We find that, based on the eight shift instructions provided, the shifter from section 8-10, needs to be modified. The modifications involve the end bits of the shift logic. For logical shifts, a 0 is inserted, as before. For the right arithmetic shift, she sign bit is the incoming bit, and for the left arithmetic shift, 0 is the incoming bit. Rotates require that the bit from the opposite end of the shifter be fed around. Finally, rotates with carry require that the carry flip-flop output be provide as an input on both ends of the shifter.2.SummaryIn this paper．we examined two CPU designs: the CISC and RISC.The CISC control unit includes a stack pointer in addition to the program counter．Control microprograms reside in ROM．and a combination of a multi．plexer and a ROM provides fast instruction decoding．The control unit also has extensive{ump andconditional branching capabilities，including one level of microsubroutines．The microprogram for the control is modularized to permit many microsubroutines to be shared in implementing the microprogram for the instructions．The RISC control unit is pipelined and has special hardware added to deal with branches. Pipelined CPUs have both data and control hazard problems．We examined one of each type of hazard，as well as software and hardware solutions for each．After discussing CISC and RISC performance，we touched on some advanced concepts, including parallel execution units, a combination of microprogrammed control with a pipeline，superpipelined CPUs, superscalar CPUs，and predictive and speculative techniques for high-performance．Finally, we related the design techniques in this paper to more general digital system design．原文翻译：本设计以MCS-51单片机为核心充分利用硬件资源设计的一种频率计，该频率计首先将被测信号放大整形处理，变成满足单片机I/O口接受的TTL/ CMOS 兼容信号从单片机的T1输入口输入直接累加脉冲数，将单片机内部定时器定时为1S，这时累加的脉冲数即为被测信号的频率。
51单片机英文文献及翻译
Data Memory
数据存储器
Te context with microcontrollers,
术语“数据存储器”用于微控制器。
The memory which stores data,i.e.RAM,is called data memory.
用来存储数据的存储器，即RAM，被称作数据存储器
The diffenent versions of 8048 series of microcontrollers microcontrollers contain 64,128.256 bytes of RAM.
8048系列的不同版本的微控制器包含64、128、256字节的RAM。
Data Memory The term data memory is used in the context with microcontrollers,The memory which stores data,i.e.RAM,is called data memory.The diffenent versions of 8048 series of microcontrollers microcontrollers contain 64,128.256 bytes of RAM.The 8048AH,8049AH and 8050AH contain 64,128 and 256 bytes of RAM respectively.64/128/256 bytes of RAM is used either as read/write memory or general-purpose registers.
There is need of cyclical reading (lower than 1 minute periods) of the actual values from the real-time clock and the sensors for pressure and temperature, and to store the read values into the microcontroller’s memory. The communication with the real-time clock and the sensors is possible with the use of I2C interface and the previously defined in the specifications protocols for reading and writing.
基于51单片机的英文论文
the Real-Time Clock Based on AT89S51Author: Class: ; Name:Abstract: Digital clock has become indispensable in people's daily life, it is widely used in public places such as the family and the office, and it gives people great convenience in study, work and entertainment. Due to the development of digital integrated circuit technology and the advanced quartz technology, the digital clock has advantages of accurate, stable performance and easy to carry. It is also used in automatic control, automatic signal and etc. Although the digital clocks are already sold on the market, but the single chip microcomputer timer function also can complete the design of the digital clock circuit. So it is necessary to the design of the digital clock. By single chip microcomputer internal timer timing precision, the four digital tube display year, month, day, time, minutes and seconds. With the keyboard, users can be preset time, display the time, set the content, set time operation mode, etc.Keywords: AT89S51; clock; digital tube; keyboard switch; function Introduction: AT89S51 is a very suitable for the beginners of the single chip microcomputer, it is fully compatible with the traditional instruction system of 8051,8031.Can realize the following functions:1. Use the keyboard switch, show respectively the seconds, minutes, hour, day, month, year;2. Use the keyboard preset year, month, day, time, minutes and seconds;3. Can the countdown, the countdown units for minutes;4. Every second , the four decimal point shine once;5. Timing alarm clock function, a buzzer call reminder.6. The clock error daily is not more than 1 second.Methods:1.The minimum single chip microcomputer systemAT89S51 has the following standard functions: 8 k bytes Flash, 256 bytes RAM, and 32-bit I/O lines, a watchdog timer, two data pointer, three 16 timer/counter, a level 6 vector 2 interrupt structure, full duplex serial port, piece of crystals and the clock circuit . In idle mode, the CPU stops working, allows RAM, timer/counter, serial port and interrupt continue to work. In fall protection mode, RAM content are stored, has been frozen, single chip microcomputer stops all work, until the next interruption or hardware reset.2.The displayDisplay uses the method of dynamic LED digital tube to display, P0 port output characters code to display, position codes are controlled by P2.4 ~ P2.7. The cost of the dynamic display is very low, but the dynamic display occupies more resources of the CPU interface. The design uses 12 lines. In addition by the dynamic display refreshing, which takes part of the work time of the CPU. So for some higher demand control system, we should consider the time taken by the display.3.The keyboardKeyboard uses 4 * 4 matrix keyboard, by P2.0 ~ P2.3 for row line, P1.4 ~ P1.7 for column line, phalanxes of 4 * 4 are made, and using the method of scanning software can determine the key value of each key. In the design, each key can be used to input data and commands.4.The power supplyControl power supply can be provided by DC 12V voltage, the power supply can be used by stepping motor driver, at the same time through the three linear stabilizer 7805 to provide other circuit power supply; If you don't need to use stepper motor, the control system of the DC5V power supply can be collected from ordinary USB interface of the computer, as long as the USB connects a computer USB port, the other connects two core power interface of controller.5.Programming interfaceMicroprocessor uses AT89S51. AT89S51 has ISP online programming function, and P1.5 ~ P1.7 are for the programming interface and software compilation and debugging includes two processes:1. By using keil software programming, input source program, and then compile until no grammar mistakes, using compilation command hex into system files(suffix:hex).2. After connecting the power cord and programming line, start USBASP programming software. Select the chip microprocessors model in the selection of AT89S51. Open and load in the flash. Load in the hex into system files. Use erase commands to erase chip in the original program, with programming command to write new programs in AT89S51. After finished, reset the program running, observing the consequence. If there is any error, it is needed to re-open the Medwin and modify the source program, to create the hex file, and then repeat the above operation, to meet the design requirements.Results:Key:| 1 | 2 | 3 | 分秒|| 4 | 5 | 6 | 时分|| 7 | 8 | 9 | 月日|| 确定| 0 | 倒计时| 年|#include <reg51.h>#include<stdio.h>#define uchar unsigned charsbit P1_3=P1^3;sbit P3_2=P3^2;unsigned char t=0;unsigned char t1=50;unsigned char t2=59;unsigned char t3=23;unsigned char t4=7;unsigned char t5=60;unsigned char t6=60;unsigned char k1=4;uchar i;uchar c;uchar a[10]={0x81,0xED,0x43,0x49,0x2D,0x19,0x11,0xCD,0x01,0x09};uchar p[5];void delay(int MS){int i,j;for( i=0;i<MS;i++)for(j=0;j<1141;j++);}uchar encoder(uchar num) {uchar i;switch(num){case 0x11:i=0x11;break;case 0x12:i=0x12;break;case 0x14:i=0x13;break;case 0x18:i=0x14;break;case 0x21:i=0x15;break;case 0x22:i=0x09;break;case 0x24:i=0x06;break;case 0x28:i=0x03;break;case 0x41:i=0x00;break;case 0x42:i=0x08;break;case 0x44:i=0x05;break;case 0x48:i=0x02;break;case 0x81:i=0x16;break;case 0x82:i=0x07;break;case 0x84:i=0x04;break;case 0x88:i=0x01;break;}return(i);}uchar key_value(){uchar tem,s,t,n;P1&=0x0f;P2|=0x0f;;tem=P2;tem|=0xf0;s=~tem;P2&=0xf0;P1|=0xf0;;tem=P1;tem|=0x0f;t=~tem;s=s+t;n=encoder(s);return(n);}uchar key(void){uchar i;P2|=0x0f;P1&=0x0f;;i=P2;i|=0xf0;i=~i;return(i);}void show1(uchar i,uchar j){P0=a[j];P2=P2&0x0f;P2|=1<<(i+3);}void show(uchar i,uchar j,uchar k,uchar l){uchar a[10]={0x81,0xED,0x43,0x49,0x2D,0x19,0x11,0xCD,0x01,0x09};uchar b,c,d,e;b=a[i];c=a[j];d=a[k];e=a[l];P2&=0x0f;P2=0x1f;P0=b;delay(1);P2&=0x0f;P2=0x2f;P0=c;delay(1);P2=0x4f;P0=d;delay(1);P2=0x8f;P0=e;delay(1);}void year(void){while(key()==0){show1(4,2);delay(1);show1(3,0);delay(1);show1(2,1);delay(1);show1(1,3);delay(1);}}void monthday(void) {TMOD=0X01;TH0=0x4c;TR0=1;IE=0X82;TMOD=0x01;while(key()==0){show1(4,0);delay(1);show1(3,1);delay(1);show1(2,0);delay(1);show1(1,t4%10);delay(1);}}void hourminute(void) {TMOD=0X01;TH0=0x4c;TL0=0x00;TR0=1;IE=0X82;TMOD=0x01;while(key()==0){show1(4,t3/10);delay(1);show1(3,t3%10);delay(1);show1(2,t2/10);delay(1);show1(1,t2%10);delay(1);}}void minutesecond() {TMOD=0X01;TH0=0x4c;TL0=0x00;TR0=1;IE=0X82;while(key()==0){show1(4,t2/10);delay(1);show1(3,t2%10);delay(1);show1(2,t1/10);delay(1);show1(1,t1%10);delay(1);}}void jishi(void){TMOD=0X01;TH0=0x4c;TL0=0x00;TR0=1;IE=0X82;TMOD=0x01;while(key()==0){show1(2,t5/10);delay(1);show1(1,t5%10);delay(1);}}void shuru(void) {--k1;if(k1==0)k1=4; while(key()==0){p[k1]=c;show1(4,c);delay(1);}}void sure(void){while(key()==0){show(p[1],p[2],p[3],p[4]);delay(1);}}void timer0(void) interrupt 1 {t++;if(t==20){t=0;t1++;t5--;if(t5==0){while(key()==0){show1(2,0);delay(1);show1(1,0);delay(1);P3_2=~P3_2;delay(1);P1_3=~P1_3;delay(1);}}t6--;if(t6==0){}if(t1==60){t1=0;t2++;if(t2==60){t2=0;t3++;if(t3==24){t3=1;t4++;if(t4==30)t4==1;}}}}TH0=0x4c;TL0=0x00;}void main(){while(1){i=key();while(i!=0){if(i==key()){uchar k;k=key_value();c=k;if(c==0x11)year();elseif(c==0x12)monthday();elseif(c==0x13)hourminute();elseif(c==0x14)minutesecond();elseif(c==0x15)jishi();elseif(c==0x16)sure();elseif(c==0x00||0x01||0x02||0x03||0x04||0x05||0x06||0x07||0x08||0x09) shuru();else;}elsebreak;}}}Conclusion: Through the single chip microcomputer can accurately realize the accurate per time, can realize the countdown, display determined year, month, day, hour, minutes, seconds, and some other functions.Reference:[1]郭晓林.基于单片机的电子时钟设计[J].中国科技博览，2010，（9).[2]何立民.单片机应用技术选编（11）［M］．北京航天航空大学出版社，2006．[3]刘守义.单片机应用技术［M］．西安电子科技大学出版社，2009.[4]时钟芯片DS1302中文资料，/info/commonIC/0083003.html。
单片机英文文献及翻译)
Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerAbstractWith the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices.Index TermsSingle Event Effects, Hardened-By-Design, microcontroller, radiation effects.I. INTRODUCTIONNASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercialstate-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely,cost-effective, and reliable manner.However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed; what types of tests are required for HBD validation?II. TESTING HBD DEVICES CONSIDERATIONSTest methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices?As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library?Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked.How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived.Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies.The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations.III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required.The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation–hardened 8051, that built their 8051 microcontroller using radiationhardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST DEVICESThree devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively.The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set compatible with the MSC-51 family.V. TEST HARDWAREThe 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other componentsof the DUT computer were removed from the immediate area of the irradiation beam.A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup.VI. TEST SOFTWAREThe 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT.All test programs implemented:• An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.• An external real-time clock for data error tag.•A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary.• A "foul-up" routine to reset program counter if it wanders out of code space.• An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured.Interrupt –This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information.Logic –This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register information.Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted.Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted.Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information.VII. TEST METHODOLOGYThe DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer's memory space). Upon awaking from the reset, the DUT computer again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code.The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itselfor the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the post-test functions. During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this reportceased, the Test Controller knew that a SEFI had occurred. This periodic data was called "telemetry". If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through the serial port describing that error, and continued with the test.VIII.DISCUSSIONA. Single Event LatchupThe main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5, 3.3, and 2.5 Volts, as well as the 0.5 Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity.B. Single Event UpsetThe primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some resultsobtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051.With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) component is sitting on top of a "dc-bias" component –presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold.The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated place-and-route of the combinatorial logic paths may have placed dual sensitive nodes close enough.At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this 0.35 μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at 0.5 Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the per-bit memory upset cross section for the CULPRiT devices and the commercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has become sensitive to upset.IX. SUMMARYA detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the commercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results.This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equivalent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application.ACKNOWLEDGEMENTSThe authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).。
(完整版)MCS-51系列单片机中英文资料对照外文翻译文献综述
MCS-51系列单片机中英文资料对照外文翻译文献综述Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have, such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same.8051 daily representatives-51 serial one-chip computers.A one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve theprocedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031, 8032.(4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control system of the source. (7) One all duplex serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporaries of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loop back ACC with another one. Inaddition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a express in the order. The controller includes the procedure counter, the order is deposited, the order deciphering, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out. Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, using for middle result to deposit operation, the data are stored temporarily and the data are buffered. In RAM of this 128B, there is unit of 32 bytes that can be appointed as the jobregister, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH, 0000H of location, in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM orderspend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O ports, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make data can latch when outputting, data can buffer when making introduction, but four function of pass away these self-same. Expand among the system of memory outside having slice, four ports these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use port correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouth, its output grade draws the resistance supremely. When using it as the mouth in common use, output grade is it leak circuit to turn on, is it urge NMOS draw the resistanceon taking to be outer with it while inputting to go out to fail. When being used as introduction, should write"1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate, can draw the pin to the high level fast; when resistance value is very large, P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw electric current load to offer outwards, draw the resistance on needn't answer and thinking. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end relatively about 20,000 ohms because of load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1.P3 mouth one multi-functional port, mouth getting many than P1 it have "3 doors and 4 buffers". Two parts there, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and" door 3 functions one switch in fact, it determines to be to output data of latch tooutput second signal of function. Act as W=At 1 o'clock, output Q end signal; act as Q=At 1 o'clock, can output W line signal. At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance .It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location to visit to P3 mouth/at not lasting lining, there are inside hardware latch Qs=1. The operation principle of P3 mouth is similar to P1 mouth.Output grade, P3 of mouth, P1 of P1, connect with inside have load resistance of drawing, every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outer. Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially, make the one-chip computer begin to hold the conductprocedure from unit 0000H. Except that the ones that enter the system are initialized normally, as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective, should sustain 24 shake cycle (namely 2 machine cycles) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal inside. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running, should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscilloscope tentatively, push and is restored to the throne the key, the wave form that observes andhas enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.MCS-51系列单片机的功能和结构MSC-51系列单片机具有一个单芯片电脑的结构和功能，它是英特尔公司的系列产品的名称。
51单片机脉宽调制控制器外文文献及翻译
51单片机脉宽调制控制器外文文献及翻译51单片机脉宽调制控制器外文文献及翻译Design of PWM Controller in a MCS-51 Compatible MCU Yue-Li Hu, Wei Wang Microelectronic Research & Development Center,Key Laboratory of Advanced Display and System Applications (Shanghai University), Ministry of Education Campus P.O.B.221, 149 Yanchang Rd, Shanghai 200072, ChinaE-mail: ****************AbstractThis paper presents a design of Pulse-Width Modulated(PWM) controller module in a MCU based on MCS-51structure. The design can generate 2-channel programmable periodic PWM signals. These output PWM signals from MCU can be used for a variety of applications including motor control. The function of the design allows users to select independent or complementary inversion timing relationships between 2 PWM wave forms. The latter mode selection also includes optional dead time function to support driving H-bridges and inverters. Therefore, users can controlthe output PWM signals through setting the duty-cycle registers. After the successful simulation at the front end, practical experiments made on a NIOS development board verify the design.1. IntroductionPWM technology is a kind of voltage regulation method by controlling the switch frequency of DC power with fixed voltage to modify the two-end voltage of load.This technology can be used for a variety of applications including motor control, temperature control and pressure control and so on. In the motor control system shown as Fig. 1, through adjusting the duty cycle of power switch, the speed of motor can be controlled. As shown in Fig. 2, under the control of PWM signal, the average of voltage that controls the speed of motor changes with Duty-cycle ( D = t1/T in this Figure ),thus the motor speed can be increased when motor power turn on, decreased when power turn off.Fig.1 PWM control block diagramFig.2: The Relationship between Voltage of Armature and Duty-cycle Therefore, the motor speed can be controlled with regularly adjusting the time of turn-on and turn-off. There are three methods could achieve the adjustment of duty cycle: (1)Adjust frequency with fixed pulse-width. (2) Adjust both frequency and pulse-width. (3) Adjust pulse-width with fixed frequency.Generally, there are four methods to generate the PWM signals as the following: (1) Generated by the device composed of separate logic components. This method is the original method which now has been discarded. (2) Generated by software. This method need CPU to continuously operate instructions to control I/O pins for generating PWM output signals, so that CPU can not do anything other. Therefore, the method also has been discarded gradually. (3) Generated by ASIC. The ASIC makes a decrease of CPU burden and steady work generally has several functions such as over-current protection, dead-time adjustment and so on. Then the method has been widely used in many kinds of occasion now. (4) Generated byPWM function module of MCU. Through embedding PWM function module in MCU and initializing the function六-维^论'文.网 , PWM pins of MCU can also automatically generate PWM out signals without CPU controlling only when need to change duty-cycle. It is the method that will be implemented in this paper.In this paper, we propose a PWM module embedded in a 8051 microcontroller. The PWM module can support PWM pulse signals by initializing the control register and duty-cycle register with three methods just mentioned above to adjust the duty cycle and several operation modes to add flexibility for user.The following section explains the architecture of the PWM module and the architectures of basic functional blocks.Section3 describes two operation modes. Experimental and simulation results verifying proper system operation are also shown in that section. Depending on mode of operation, the PWM module creates one or more pulse-width modulated signals, whose duty ratios can be independently adjusted.2. Implementation of PWM module in MCU2.1 Overview of the PWM module六-维^论'文.网A block diagram of PWM module is shown in Fig.3. It is clearly from the diagram that the whole module is composed of two sections: PWM signal generator and dead-time generator with channel select logic. The PWM function can be started by the user through implementing some instructions for initializing the PWM module. In particular, the following power and motion control applications are supported:• DC Motor• Uninterruptable Power Supply (UPS)Fig.3 Architecture of PWM ModuleThe PWM module also has the following features:• Two PWM signal outputs with complementary or independent operation• Hardware dead-time generators for complementary mode•Duty cycle updates are configurable to be immediated or synchronized to the PWM2. 2 Details of the architecture2.2.1 PMW generatorThe architecture of the 2-output PWM generator shown in Fig.3 is based on a 16-bit resolution counter which creates a pulse-width modulated signal. The system is synthesized by a system clock signal whose frequency can be divided by 4 times or 12 times through setting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON as shown in Fig.4. To PWM0 generator, the clock to 16-bit counter will be pre-divided by 4 times by default when T3M is set to zero. And the clock will be divided by 12 times when T3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained in detail in T able 1.161551单片机脉宽调制控制器外文文献及翻译第2页Fig .4 Bit Mapping of PWMCONTable 1: The Bit Definition in PWMCONBIT DescriptionTF4 Interrupt Request for PWM0TR4 RUN bit for PWM0TF3 Interrupt Request for PWM1TR3 RUN bit for PWM1PSEL Channel Select inComplementary ModeCPWM Mode SelectT4M Clock Prescaler for PWM1T3M Clock Prescaler for PWM02.2.2 Channel-select logicThe follow Fig. 5 shows the channel-select logic which is useful in Complementary Mode. From this diagram, it is clear to know that signal CP and CPWM control the source of PWMH and PWML. And the details about the two control signals will be discussed in the section 3, and the architecture of dead-time generator will also be discussed in section 3.1 for the continuity of Complementary Mode.Fig. 5 Diagram of Channel-select Logic3. Operation Mode and Simulation ResultsThe design has two operation modes: Independent Mode and Complimentary Mode. By setting the corresponding bit CPWM in register PWMCON shown in Fig. 4, user can select one of the two operation modes. When CPWM is set to zero,PWMmodule will work in Independent Mode, whereas,PWM module will work in Complimentary Mode. In the following of this section, the two operation mode will be explained respectively in detail and the simulation results of the PWM module from the Synoposys VCS EDA platform which verify the design will also be shown.3.1 Independent PWM Output ModeAn Independent PWM Output mode is useful for driving loads such as the one shown in Figure 1. A particular PWM output is in the Independent Output mode when the corresponding CP bit in the PWMCON register is set to zero.In this case, two-channel PWM outputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0 generator, and the signal on pin PWM1/PWML is from PWM0 generator. The separate case is achieved by the channel-select logic shown in Fig. 6. The PWM I/O pins are set to independent mode by default upon advice reset. The dead-time generator is disabled in the Independent mode. The simulation result is shown in Figure 4 as the following Fig.5.Tr4 and tr3 are run bits to PWM0 and PWM1, respectively.Actually, from this diagram, Pin P1[5]/ P1[4] of MCU is used for PWMH/ PWML or normal I/O ,alternatively.Fig.6 the Waveform of PWM Outputs in Independent Mode3.2 Complementary PWM Output ModeThe Complementary Output mode is used to drive inverter loads similar to the one shown in Figure 7. This inverter topology is typical for DC applications. InComplementary Output Mode, the pair of PWM outputs cannot be active simultaneously. The PWM channel and output pin pair are internally configured through channel-select logic as shown in Figure 5. A dead-time may be optionally inserted duringdevice switching where both outputs are inactive for a short period.Authorized licensed use limited to: East China Normal University. Downloaded on January 11, 2009 at 00:36 from IEEE Xplore. Restrictions apply.Proceedings of HDP’07 六-维^论'文.网The Complementary mode is selected for PWM I/O pin pair by setting the appropriate CPWM bit in PWMCON. In this case, PSEL is in effect. PWMH and PWML will come from PWM0 generator when PSEL is set to zero, when the signals from PWM1 generator is useless, whereas PWMH and PWML will come from PWM1 generator when PSEL is set to 1, when the signals from PWM0 generator is useless. In the process of producing the PWM outputs in Complementary Mode, the dead-time will be inserted to be discussed in the following section.Fig 7: Typical Load for Complementary PWM Outputs3.3 Dead-time ControlDead-time generation is automatically enabled when PWM I/O pin pair is operating in the Complementary Output mode. Because the power output devices cannot switchinstantaneously, some amount of time must be provided between the turn-offevent of one PWM output in a complementary pair and the turn-on event of the othertransistor. The 2-output PWM module has one programmable dead-time with 8-bit register.The complementary output pair for the PWM module has an 8-bit down counter that is used to produce the dead-time insertion. As shown in Figure 8, the dead time unit has a rising and falling edge detector connected to PWM signal from one of PWM generator. The dead times is loaded into the timer on the detected PWM edge event. Depending on whether the edge is rising or falling, one of the transitions on the complementary outputs is delayed until the timer counts down to zero. A timing diagram indicating the dead time insertion for the pair of PWM outputs is shown in Figure 8.Fig.8 Dead-time Unit Block DiagramConclusionsIn this paper, we have designed PWM module based on an 8-bit MCU compatible with 8051 family. The design can generate 2-channel programmable periodic PWM signals with two operation mode, Independent Mode and Complementary Mode in which dead-time will be inserted. The simulation results on the EDA platform have proven its correctness andusefulness.AcknowledgmentsThe authors would like to thank Shanghai Leading Academic Discipline Project (Project Number: T0103) for the financial support.51单片机脉宽调制控制器外文文献及翻译第3页Fig. 9 the Waveforms of PWM Outputs in ComplementaryModeReferences1. Xiang hui-fang and Hu yue-li, Computer measurement and control, 14(7) p. 942(2006)2. Hu yue-li and Ding qian, Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, p.267 (2006)3. Yue-Li Hu and Bing Xiong, Proceedings of 2006 Conf. on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP’06), China, p.278(2006).六-维^论'文.网4. Yue-Li Hu, Jia-Lin Cao, Feng Ran and Zhi-Jian Liang,Proceedings of 2004 Conf. on High Density Microsystem Design and Packaging and Component Failure Analysis(HDP'04),China, p.25(2004)5. JING Wei-liang, HU Yue-li, CAO Jia-lin. “Design of 16MB Addr essing Spaces in an MCU Based on the MCS-51 Structure,”The 7th IEEE CPMT Conference on HighDensity Microsystem Design and Packaging and Component Failure Analysis (HDP’05),Shanghai,China,June30-July 3,(2005), pp.509-512.6. Peterchev, A.V, Jinwen Xiao; S anders, S.R, “Architecture and IC implementation of a digital VRM controller,”Power Electronics, IEEE Transactions on Volume 18, Issue 1, Part 2, Jan. 2003 Page(s):356 –364.7. Smith, K.M., Jr.; Lai, Z.; Smedley, K.M.; “A new PWM controller with one-cycle response,” Power Electronics,IEEE Transactions on Volume 14, Issue 1, Jan. 1999Page(s):142 - 150Authorized licensed use limited to: East China Normal University. Downloaded on January 11, 2009 at 00:36 from IEEE Xplore. Restrictions apply.中文译文：基于51单片机兼容的脉宽调制控制器的设计胡越黎王伟微电子研发中心，重点实验室显示器及系统应用（上海大学），教育部校园POB221，149延长路，上海200072，中国摘要：这篇论文描述了脉宽调制控制器模块在微控制器中基于51单片机构造的设计。
毕业设计单片机相关外文文献翻译人工修订精确版
Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers .An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as othercomputers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharingOutput grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth ina normal way . Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially , make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.At present,MCU to infiltrate all areas of our lives, which is almost difficult to find traces of the field without SCM. Missile navigation equipment, aircraft, all types of instrument control, computer network communications and data transmission, industrial automation, real-time process control and data processing, extensive use of various smart IC card, civilian luxury car security system, video recorder, camera, fully automatic washing machine control, and program-controlled toys, electronic pet, etc., which are inseparable from the microcontroller. Not to mention the area of robot control, intelligent instruments, medical equipment was. Therefore, the MCU learning, development and application of the large number of computer applications and intelligent control of the scientists, engineers.SCM is widely used in instruments and meters, household appliances, medical equipment, aerospace, specialized equipment, intelligent management and process control fields, roughly divided into the following several areas:（1）In the application of Intelligent InstrumentsSCM has a small size, low power consumption, controlling function, expansion flexibility, the advantages of miniaturization and ease of use, widely used instrument, combining different types of sensors can be realized Zhuru voltage, power, frequency, humidity, temperature, flow, speed, thickness, angle, length, hardness, elemental, physical pressure measurement. SCM makes use of digital instruments, intelligence, miniaturization, and functionality than electronic or digital circuits more powerful. Such as precision measuring equipment (power meter, oscilloscope, various analytical instrument).（2）In the industrial control applicationWith the MCU can constitute a variety of control systems, data acquisition system. Such as factory assembly line of intelligent control,all kinds of alarm systems,and computer networks constitute a secondary control system.（3）In the Appliance of Household appliancesIt can be said that the appliances are basically using SCM, praise from the electric rice, washing machines, refrigerators, air conditioners, color TV, and other audio video equipment, to the electronic weighing equipment, varied, and omnipresent.（4）In the field of computer networks and communications applicationsMCU general with modern communication interface, can be easy with the computer data communication, networking and communications in computer applications between devices had excellent material conditions, are basically all communication equipment to achieve a controlled by MCU from mobile phone, telephone, mini-program-controlled switchboards, building automated communications call system, train radio communication, to the daily work can be seen everywhere in the mobile phones, trunked mobile radio, walkie-talkies, etc..（5）Microcomputer in the field of medical device applicationsMCU in the use of medical devices is also quite extensive, such as medical respirator, the various analyzers, monitors, ultrasound diagnostic equipment and hospital beds, etc. call system.（6）In a variety of major appliances in the modular applicationsDesigned to achieve some special single specific function to be modular in a variety of circuit applications, without requiring the use of personnel to understand its internal structure. If music integrated single chip, seemingly simple function, miniature electronic chip in the net (the principle is different from the tape machine), you need a computer similar to the principle of the complex. Such as: music signal to digital form stored in memory (like ROM), read by the microcontroller, analog music into electrical signals (similar to the sound card).In large circuits, modular applications that greatly reduce the volume, simplifies thecircuit and reduce the damage, error rate, but also easy to replace.（7）Microcontroller in the application field of automotive equipmentSCM in automotive electronics is widely used, such as a vehicle engine controller, CAN bus-based Intelligent Electronic Control Engine, GPS navigation system, abs anti-lock braking system, brake system, etc..In addition, the MCU in business, finance, research, education, national defense, aerospace and other fields has a very wide range of applications.51系列单片机的结构和功能51系列单片机是英特尔公司生产的具有一定结构和功能的单片机产品。
单片机英文参考文献(精选120个)
我国的单片机起步虽然较晚，但经过几十年的发展，也取得了巨大的成就。
不论是工业生产还是社会生活的各个方面都离不开单片机的使用。
下面是搜素整理的单片机英文参考文献的分享，以供参考。
单片机英文参考文献一： [1]Hui Wang. Optimal Design of Single Chip Microcomputer Multi-machine Serial Communication based on Signal VerificationTechnology[J]. International Journal of Intelligent Information and Management Science,2020,9（1）。
[2]Philip J. Basford,Steven J. Johnston,Colin S. Perkins,Tony Garnock-Jones,Fung Po Tso,Dimitrios Pezaros,Robert D. Mullins,Eiko Yoneki,Jeremy Singer,Simon J. Cox. Performance analysis of single board computer clusters[J]. Future Generation ComputerSystems,2020,102. [3]. Computers; Reports from University of Southampton Describe Recent Advances in Computers （Performance Analysis of Single Board Computer Clusters）[J]. Computers, Networks & Communications,2020. [4]Yunyu Cao,Jinjin Dang,Chenxu Cao. Design of Automobile Digital Tire Pressure Detector[J]. Journal of Scientific Research and Reports,2019. [5]Sudad J. Ashaj,Ergun Er?elebi. Reduce Cost Smart Power Management System by Utilize Single Board Computer Artificial Neural Networks for Smart Systems[J]. International Journal of Computational Intelligence Systems,2019. [6]Hanhong Tan*, Yanfei Teng. Design of PWM Lighting brightness Control based on LAN QIAO Cup single Chip Microcomputer[J]. International Journal of Computational and Engineering,2019,4（3）。
外文翻译--基于51单片机温度报警器的设计(适用于毕业论文外文翻译+中英文对照)
外文翻译--基于51单片机温度报警器的设计(适用于毕业论文外文翻译+中英文对照)XXX: Design of a Temperature Alarm Based on 51 MCUDepartment: n EngineeringMajor: Measurement and Control Technology and nClass:Student ID:Name:Supervisor:Date:A microcontroller。
also known as a single-chip computer system。
XXX its ns being integrated on a small chip。
it has most of the components needed for a complete computer system。
such as CPU。
memory。
internal and external bus systems。
and mostof them also have external storage。
At the same time。
it integrates XXX interfaces。
timers。
real-time clocks。
etc。
The most XXX integrate sound。
image。
ork。
and complex input-output systems on a single chip.XXX used in the industrial control field。
Microcontrollers XXX CPUs inside the chip。
The original design concept was to integrate a large number of peripheral devices and CPUs on a chip to make the computer system XXX's Z80 was the first processor designed according to this concept。
单片机自动化专业论文中英文对照外文翻译文献
中英文对照外文翻译文献Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers .An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chipcomputers, such as 8031 , 8032, 80C ,etc.. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only needouter quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) Inthe slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharingThe circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouths, its output grade draws the resistance supremly. When using it as the mouth in common use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the resistance on taking to be outer with it while inputting togo out to fail. When being used as introduction, should write "1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate , can draw the pin to the high level fast ; When resistance value is very large, P1 mouth, in order to hinder the introduction state high. Output as P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw the resistance on needn't answer and thenning. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end. Relatively about 20,000 ohms because of the load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1. P3 mouth one multi-functional port, mouth getting many than P1 it have "and " 3 door and 4 buffer". Two part these, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and " door 3 function one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W =At 1 o'clock, output Q end signal; Act as Q =At 1 o'clock, can output W line signal . At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance . It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location (the location or the byte ) to visit to P3 mouth /at not lasting lining, there are inside hardware latch Qs =1.The operation principle of P3 mouth is similar to P1 mouth.Output grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially , make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal:Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having onemore , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.MCS -51系列单片机的功能和结构MCS - 51系列单片机具有一个单芯片电脑的结构和功能，它是英特尔公司生产的系列产品的名称。
（完整版）51单片机外文文献
（完整版）51单⽚机外⽂⽂献The Introduction of AT89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel 'hsigh-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one 5 vector two-level interrupt architecture, a full duplex serial port, one-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also be configured to be the multiplexedaddress/data bus during accessesto external program and data memory. In this mode P0 has internal Pull-up resistor . Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during Program verification . External Pull-up resistors are required during Program verification .Port 1Port 1 is an 8-bit bi-directional I/O port with internal Pull-up resistors. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal Pull-up resistors and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal Pull-up resistors. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal Pull-up resistor . The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal Pull-up resistor and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current, because of the internal Pull-up resistor . Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal Pull-up resistor when emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verificati on.Port 3Port 3 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 3 output buffers can sin k/source four TTL in puts. When 1s are writte n to Port 3 pins they are pulled high by the internal Pull-up resistor and can be used as in puts. As in puts, Port 3 pins that are exter nally being pulled low will source curre nt (IIL) because of the Pull-up resistor. Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset in put. A high on this pin for two mach ine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. Withthe bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51is executing code from external program memory, PSENis activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the in put and output, respectively, of an inverting amplifier which can be con figured for use as an on-chip oscillator, as show n in Figure 1.Either a quartz crystal or ceramic reson ator may be used. To drive the device from an exter nal clock source, XTAL2 should be left unconn ected while XTAL1 is drive n asshow n in Figure 2.There are no requireme nts on the duty cycle of the exter nal clock sig nal, since the in put to the internal clock ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Con figurati onC2T ⼘C1NG EXTERNALOSCILLATOR SIGNALftNDXTAL2XTAL1GNDFigure 1. Oscillator Connections Figure 2. External Clock DriveXTAL2X1AL1Idle ModeIn idle mode, the CPU puts itself to sleep while all the on chip peripherals rema in active. The mode is inv oked by software. The content of the on-chip RAM and all the special fun cti ons registers rema in un cha nged duri ng this mode. The idle mode can be term in ated by any en abled in terrupt or by a hardware reset. It should be no ted that whe n idle is termi nated by a hard ware reset, the device no rmally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this eve nt, but access to the port pins is not in hibited. To elimi nate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to exter nal memory.Power-dow n ModeIn the power-dow n mode, the oscillator is stopped, and the in struct ion that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its no rmal operat ing level and must be held active long eno ugh to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.Whe n lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a ran dom value, and holds that value un til reset is activated. It is n ecessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.译⽂:AT89C51的介绍描述AT89C51是⼀个低电压，⾼性能CMOS 8位单⽚机带有4K字节的可反复擦写的程序存储器（PENROM。
MCS-51系列单片机中英文资料对照外文翻译文献综述教学文稿
精品文档MCS-51系列单片机中英文资料对照外文翻译文献综述Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have, such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same.8051 daily representatives-51 serial one-chip computers.A one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3)Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031, 8032.(4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control system of the source. (7) One all duplex serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporaries of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to counttemporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a express in the order. The controller includes the procedure counter, the order is deposited, the order deciphering, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out. Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, using for middle result to deposit operation, the data are stored temporarily and the data are buffered. In RAMof this 128B, there is unit of 32 bytes that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH, 0000H of location, in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different datatransmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O ports, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make data can latch when outputting, data can buffer when making introduction, but four function of pass away these self-same. Expand among the system of memory outside having slice, four ports these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use port correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouth, its output grade draws the resistance supremely. When using it as the mouth in common use,output grade is it leak circuit to turn on, is it urge NMOS draw the resistance on taking to be outer with it while inputting to go out to fail. When being used as introduction, should write"1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate, can draw the pin to the high level fast; when resistance value is very large, P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw electric current load to offer outwards, draw the resistance on needn't answer and thinking. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end relatively about 20,000 ohms because of load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1.P3 mouth one multi-functional port, mouth getting many than P1 it have "3 doors and 4 buffers". Two parts there, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and" door 3functions one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W=At 1 o'clock, output Q end signal; act as Q=At 1 o'clock, can output W line signal. At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance .It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location to visit to P3 mouth/at not lasting lining, there are inside hardware latch Qs=1. The operation principle of P3 mouth is similar to P1 mouth.Output grade, P3 of mouth, P1 of P1, connect with inside have load resistance of drawing, every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outer. Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into0000H initially, make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally, as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective, should sustain 24 shake cycle (namely 2 machine cycles) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal inside. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running, should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscilloscope tentatively,push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.MCS-51系列单片机的功能和结构MSC-51系列单片机具有一个单芯片电脑的结构和功能，它是英特尔公司的系列产品的名称。
自动化专业单片机相关毕业论文外文文献翻译及中英对照
毕业设计（论文）外文文献翻译文献、资料题目：MCS -51系列单片机的功能和结构文献、资料来源：文献、资料发表（出版）日期：院（部）：专业：班级：姓名：学号：指导教师：翻译日期： 2017.02.14Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers .An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into atiming way too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includesthe procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formationthe same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instructionsystem of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharingThe circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different。
单片机 外文翻译 外文文献 英文文献 中英对照 基于C51兼容微(宝典)
附录A 英文原文Design of PWM Controller in a MCS-51 Compatible MCUAuthor . Yue-Li Hu Wei Wang Microelectronic Research Development Center CampusP.O.B.221 149 Yanchang Rd Shanghai 200072 China Introduction PWM technology is a kind of voltage regulation method by controlling the switchfrequency of DC power with fixed voltage to modify the two-end voltage of load. Thistechnology can be used for a variety of applications including motor control temperaturecontrol and pressure control and so on. In the motor control system shown as Fig. 1 throughadjusting the duty cycle of power switch the speed of motor can be controlled. As shown inFig. 2 under the control of PWM signal the average of voltage that controls the speed ofmotor changes with Duty-cycle D t1/T in this Figure thus the motor speed can beincreased when motor power turn on decreased when power turn off.Fig.1: The Relationship between Voltage of Armature and Fig.2 Architecture of PWM Module Therefore the motor speed can be controlled with regularly adjusting the time of turn-onand turn-off. There are three methods could achieve the adjustment of duty cycle: 1 Adjustfrequency with fixed pulse-width. 2 Adjust both frequency and pulse-width. 3 Adjustpulse-width with fixed frequency. Generally there are four methods to generate the PWM signals as the following: 1Generated by the device composed of separate logic components. This method is the originalmethod which now has been discarded. 2 Generated by software. This method need CPU tocontinuously operate instructions to control I/O pins for generating PWM output signals sothat CPU can not do anything other. Therefore the method also has been discarded gradually.3 Generated by ASIC. The ASIC makes a decrease of CPU burden and steady workgenerally has several functions such as over-current protection dead-time adjustment and soon. Then the method has been widely used in many kinds of occasion now. 4 Generated byPWM function module of MCU. Through embedding PWM function module in MCU andinitializing the function PWM pins of MCU can also automatically generate PWM outsignals without CPU controlling only when need to change duty-cycle. It is the method thatwill be implemented in this paper. In this paper we propose a PWM module embedded in a 8051 microcontroller. ThePWM module can support PWM pulse signals by initializing the control register andduty-cycle register with three methods just mentioned above to adjust the duty cycle andseveral operation modes to add flexibility for user. The following section explains the architecture of the PWM module and the architecturesof basic functional blocks. Section3 describes two operation modes. Experimental andsimulation results verifying proper system operation are also shown in that section.Depending on mode of operation the PWM module creates one or more pulse-widthmodulated signals whose duty ratios can be independently adjusted. Implementation of PWM module in MCU Overview of the PWM module A block diagram of PWM module is shown in Fig.3. It is clearly from the diagram thatthe whole module is composed of two sections: PWM signal generator and dead-timegenerator with channel select logic. The PWM function can be started by the user throughimplementing some instructions for initializing the PWM module. In particular the followingpower and motion control applications are supported: DC Motor Uninterruptablel Power Supply UPSThe PWM module also has the following features: Two PWM signal outputs with complementary or independent operation Hardware dead-time generators for complementary mode Duty cycle updates are configurable to be immediated or synchronized to the PWM Fig.3 Architecture of PWM Module Details of the architecture PMW generator The architecture of the 2-output PWM generator shownin Fig.4 is based on a 16-bitresolution counter which creates a pulse-width modulated signal. The system is synthesizedby a system clock signal whose frequency can be divided by 4 times or 12 times throughsetting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON asshown in Fig.4. To PWM0 generator the clock to 16-bit counter will be pre-divided by 4times by default when T3M is set to zero. And the clock will be divided by 12 times whenT3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained indetail in Table 1. Fig .4 Bit Mapping of PWMCON Table 1: The Bit Definition in PWMCONChannel-select logic The follow Fig. 5 shows the channel-select logic which is useful in ComplementaryMode. From this diagram it is clear to know that signal CP and CPWM control the source ofPWMH and PWML. And the details about the two control signals will be discussed in thesection 3 and the architecture of dead-time generator will also be discussed in section 5 forthe continuity of Complementary Mode. Fig. 5 Diagram of Channel-select LogicOperation Mode and Simulation Results The design has two operation modes: Independent Mode and Complimentary Mode. Bysetting the corresponding bit CPWM in register PWMCON shown in Fig.6 user can select oneof the two operation modes. When CPWM is set to zero PWM module will work inIndependent Mode whereas PWM module will work in Complimentary Mode. In thefollowing of this section the two operation mode will be explained respectively in detail andthe simulation results of the PWM module from the Synoposys VCS EDA platform whichverify the design will also be shown.Independent PWM Output Mode An Independent PWM Output mode is useful for driving loads such as the one shown inFigure 6. A particular PWM output is in the Independent Output mode when thecorresponding CP bit in the PWMCON register is set to zero.In this case two-channel PWMoutputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0generator and the signal on pin PWM1/PWML is from PWM0 generator. The separate case isachieved by the channel-select logic shown in Fig. 6. The PWM I/O pins are set toindependent mode by default upon advice reset. The dead-time generator is disabled in theIndependent mode. The simulation result is shown in Figure 6 as the following Fig.6 Tr4 andtr3 are run bits to PWM0 and PWM1 respectively. Actually from this diagram Pin P15/P14 of MCU is used for PWMH/ PWML or normal I/O alternatively. Fig6 the Waveform of PWM Outputs in Independent ModeComplementary PWM Output Mode The Complementary Output mode is used to drive inverter loads similar to the oneshown in Figure 7. This inverter topology is typical for DC applications. In ComplementaryOutput Mode the pair of PWM outputs cannot be active simultaneously. The PWM channeland output pin pair are internally configured through channel-select logic as shown in Figure7.A dead-time may be optionally inserted during device switching where both outputs areinactive for a short period. Fig 7 : Typical Load for Complementary PWM Outputs The Complementary mode is selected for PWM I/O pin pair by setting the appropriateCPWM bit in PWMCON. In this case PSEL is in effect. PWMH and PWML will come fromPWM0 generator when PSEL is set to zero when the signals from PWM1 generator is uselesswhereas PWMH and PWML will come from PWM1 generator when PSEL is set to 1 whenthe signals from PWM0 generator is useless. In the process of producing the PWM outputs inComplementary Mode the dead-time will be inserted to be discussed in the following section.Dead-time Control Dead-time generation is automatically enabled when PWM I/O pin pair is operating inthe Complementary Output mode. Because the power output devices cannotswitchinstantaneously some amount of time must be provided between the turn-off event of onePWM output in a complementary pair and the turn-on event of the other transistor. The2-output PWM module has one programmable dead-time with 8-bitregister.Thecomplementary output pair for the PWM module has an 8-bit down counter that is used toproduce the dead-time insertion. As shown in Figure 8 the dead time unit has a rising andfalling edge detector connected to PWM signal from one of PWM generator. The dead timesis loaded into the timer on the detected PWM edge event. Depending on whether the edge isrising or falling one of the transitions on the complementary outputs is delayed until the timercounts down to zero. A timing diagram indicating the dead time insertion for the pair of PWMoutputs is shown in Figure 8a. Fig 8a Dead-time Unit Block Diagram Fig. 8b the Waveforms of PWM Outputs in Complementary ModeConclusions In this paper we have designed PWM module based on an 8-bit MCU compatible with8051 family. The design can generate 2-channel programmable periodic PWM signals withtwo operation mode Independent Mode and Complementary Mode in which dead-time willbe inserted. The simulation results on the EDA platform have proven its correctness andusefulness. 附录B 汉语翻译基于C51 兼容微处理器单片机的PWM 控制器设计Yue-Li Hu Wei Wa 单片机研究与开发中心Campus P.O.B.221 149Yanchang Rd Shanghai 200072 China 导言PWM 技术，是一种电压调节方法，通过控制具有固定电压的直流电源的开关频率来调整两端负荷电压。
单片机毕业设计(论文)外文资料翻译---51系列单片机的结构和功能
毕业设计(论文)外文资料翻译系：电光系专业：电子科学与技术姓名：学号： 080403136外文出处：Structure and function of(用外文写)the MCS-51 series 附件： 1.外文资料翻译译文；2.外文原文。
指导教师评语：签名：年月日注：请将该封面与附件装订成册。
附件1：外文资料翻译译文51系列单片机的结构和功能51系列单片机是英特尔公司生产的具有一定结构和功能的单片机产品。
这家公司在1976年引入8位MCS - 48系列单片机后，于1980年又推出了8位高档的MCS - 51系列单片机。
它包含很多种这类型的单片机，如8051，8031，8751，80C51BH，80C31BH等，它们的基本组成，基本性能和指令系统都是一样的。
一般情况习惯用8051来代表51系列单片机。
早期的单片机都是8位或4位的。
其中最成功的是INTEL的8031，因为简单可靠而性能不错获得了很大的好评。
此后在8031上发展出了MCS51系列单片机系统。
基于这一系统的单片机系统直到现在还在广泛使用。
随着工业控制领域要求的提高，开始出现了16位单片机，但因为性价比不理想并未得到很广泛的应用。
90年代后随着消费电子产品大发展，单片机技术得到了巨大提高。
随着INTEL i960系列特别是后来的ARM系列的广泛应用，32位单片机迅速取代16位单片机的高端地位，并且进入主流市场。
而传统的8位单片机的性能也得到了飞速提高，处理能力比起80年代提高了数百倍。
目前，高端的32位单片机主频已经超过300MHz，性能直追90年代中期的专用处理器，而普通的型号出厂价格跌落至1美元，最高端的型号也只有10美元。
当代单片机系统已经不再只在裸机环境下开发和使用，大量专用的嵌入式操作系统被广泛应用在全系列的单片机上。
而在作为掌上电脑和手机核心处理的高端单片机甚至可以直接使用专用的Windows和Linux操作系统。
单片机比专用处理器更适合应用于嵌入式系统，因此它得到了最多的应用。
单片机的外文文献及中文翻译
单片机的外文文献及中文翻译一、外文文献Title: The Application and Development of SingleChip Microcontrollers in Modern ElectronicsSinglechip microcontrollers have become an indispensable part of modern electronic systems They are small, yet powerful integrated circuits that combine a microprocessor core, memory, and input/output peripherals on a single chip These devices offer significant advantages in terms of cost, size, and power consumption, making them ideal for a wide range of applicationsThe history of singlechip microcontrollers can be traced back to the 1970s when the first microcontrollers were developed Since then, they have undergone significant advancements in technology and performance Today, singlechip microcontrollers are available in a wide variety of architectures and capabilities, ranging from simple 8-bit devices to complex 32-bit and 64-bit systemsOne of the key features of singlechip microcontrollers is their programmability They can be programmed using various languages such as C, Assembly, and Python This flexibility allows developers to customize the functionality of the microcontroller to meet the specific requirements of their applications For example, in embedded systems for automotive, industrial control, and consumer electronics, singlechip microcontrollers can be programmed to control sensors, actuators, and communication interfacesAnother important aspect of singlechip microcontrollers is their low power consumption This is crucial in batterypowered devices and portable electronics where energy efficiency is of paramount importance Modern singlechip microcontrollers incorporate advanced power management techniques to minimize power consumption while maintaining optimal performanceIn addition to their use in traditional electronics, singlechip microcontrollers are also playing a significant role in the emerging fields of the Internet of Things （IoT) and wearable technology In IoT applications, they can be used to collect and process data from various sensors and communicate it wirelessly to a central server Wearable devices such as smartwatches and fitness trackers rely on singlechip microcontrollers to monitor vital signs and perform other functionsHowever, the design and development of systems using singlechip microcontrollers also present certain challenges Issues such as realtime performance, memory management, and software reliability need to be carefully addressed to ensure the successful implementation of the applications Moreover, the rapid evolution of technology requires developers to constantly update their knowledge and skills to keep up with the latest advancements in singlechip microcontroller technologyIn conclusion, singlechip microcontrollers have revolutionized the field of electronics and continue to play a vital role in driving technological innovation Their versatility, low cost, and small form factor make them an attractive choice for a wide range of applications, and their importance is expected to grow further in the years to come二、中文翻译标题：单片机在现代电子领域的应用与发展单片机已成为现代电子系统中不可或缺的一部分。
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The Introduction of AT89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one 5 vector two-level interrupt architecture, a full duplex serial port, one-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also be configured to be the multiplexed address/data bus during accesses to external program and data memory. In this mode P0 has internal Pull-up resistor. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during Program verification. External Pull-up resistors are required during Program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal Pull-up resistors. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal Pull-up resistors and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal Pull-up resistors. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal Pull-up resistor and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current, because of the internal Pull-up resistor. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal Pull-up resistor when emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives thehigh-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal Pull-up resistor and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the Pull-up resistor. Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the addressduring accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.译文：AT89C51的介绍描述AT89C51是一个低电压，高性能CMOS 8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。