基于51单片机的英文论文
基于51单片机步进电机毕业设计外文资料原文与译文
外文原文Stepping motor application and controlStepping motor is an electrical pulse will be converted into angular displacement of the implementing agencies.Put it in simple language-speaking:When the stepper drive pulse signal to a receiver,it drives stepper motor rotation direction by setting a fixed point of view(and the step angel).You can control the number of pulses to control the amount of angular displacement,so as to achieve the purpose of accurate positioning;At the same time,you can by controlling the pulse frequency to control the motor rotation speed and acceleration,so as to achieve the purpose of speed.Stepping motor directly from the AC-DC power supply,and must use special equipment-stepper motor drive. Stepping motor drive system performance,in addition to their own performance with the motor on the outside.but also to a large extent depend on the drive is good or bad.A typical stepper motor drivesystem is operated by the stepper motor controller,stepper motor drives and stepper motor body is composed of therr parts. Stepping motor controller stepper pulse and direction signal,each made of a pulse,stepper motor-driven stepper motor drives a rotor rotating step angle,that is,step-by=step further.High or low speed stepper motor,or speed,or deceleration,start or stop pulses are entirely dependent on whether the level or frequency.Decide the direction of the signal controller stepper motor clockwise or counterclockwise rotation. Typically,the stepper motor drive circuit from the logic control,power driver circuit,protection circuit and power components. Stepping motor drive controller,once received from the direction of the signal and step pulse,the control circuit on a pre-determined way of the electrical power-phase stepper motor drive controller,once received from the direction of the signal and step pulse,the control circuit on a pre-determined way of the electrical power=phase stepper motor excitation windings of the conduction or cut-off signal.Control circuit output signal power amplifier,which is stepper motor driven power drive part.Power stepper motor drive circuit to control the input current winding to form a space for rotating magnetic filed excitation,the rotor-driven movement.Protection circuit in the event of short circuit,overload,overheating,such as failure to stop the rapid and motor.Motor is usually for the permanent rotor,when the current flows through the stator windings,the stator windings produce a magnetic field vector.The magnetic field will lead to a rotor angle of rotation,making a pair of rotor and stator magnetic field direction of the magnetic field direction.When the stator rotating magnetic field vector from a different angle.Also as the rotor magnetic field to a point of view,An electrical pulse for each input,the motor rotation angle step,Tts output and input of the angular displacement is proportional to the pulses,with pulse frequency proportional to speed.Power to change the order of winding,the electrical will be reversed.We can,therefore,control the pulse number,frequency and electrical power windings of each phase to control the order of rotation of stepper motor.Stepping motor types:Permanent magnet(PM).Magnetic generally two-phase stepper,torque and are smaller ab=nd generally stepping angle of 7.5 degrees or 15 degrees;put more wind for air-conditioning. Reactive (VR),the domestic general called BF,have a common three-phase reaction,step angle of 1.5 degrees;also have five-phase reaction.Noise,no torque has been set at a large number of out.Hybrid(HB),conmmon two-phase hybrid,five-phase hybrid,therr-phase hybrid,four-phasehybrid,two-phase can be common with the four-phase drive,five-phase ,three-phase must be used with their drives;Two-phase, four-phase hybrid step angle is 1.8 degrees more than a small size,great distance,and low noise;Five-phase hybrid stepping motor is generally 0.72,the motor step angle small,high resolution,but the complexity of drive circuits,wiring problems,such as the 5-phase system of 10 lines.Three-phase hybrid stepping motor step angle of 1.2 degrees,but according to the use of 1.8 degrees,the three-phase hybrid more pole will help electric folder symmetric angle,it can be more than two-phase,five-phase high accuracy,the error even smaller,run more smoothly. Stepper motor to maintain torque:stepper motor power means no rotation,the stator locked rotoe torque.It is a stepper motor,one of the most important parameters,usually in the low-speed stepper motor torque at the time of close to maintain the torque.As the stepper motor output torque increases with the speed of constant attention,the output power also increases with the speed of change,so as to maintain torque on the stepper motor to measure the parameters of one of the most important.For example,when people say that the stepper motor 2N.m,in the absence of special circumstances that means for maintaining the torque of the stepper motor 2N.m.Precision stepper motoes:stepper motor step angle accuracy of 3-5%,not cumulative. Stepper motor to allow the minimum amount of surface temperature: Stepper motor causes the motor remperature is too high the first magnetic demagnetization,resulting in loss of torque dowm even further,so the motor surface temperature should be the maximum allowed depending in the motor demagnetization of magnetic material pints; enerally speaking,the magnetic demagnetization points are above 130 degrees Clesius,and some even as high as 200degrees Celsius,so the stepper motor surface temperature of 80-90 degrees Celsius is normal. Start frequency of no-load:the stepper motor in case of no-load to the normal start of the pulse frequency,if the pulse frequency is higher than the value of motor does not start,possible to lose steps or blocking.In the case of the load,start frequency should be to accelerate the process,that is ,the lower frequency to start,and then rose to a certain acceleration of the desired frequency (motor speed from low rise to high-speed).Step angle:that is to send a pulse,the electrical angle corresponding to rotation.Torque positioning: positioning torque stepper motor does not refer to the case of electricity,locked rotor torque stator.Operating frequency:step-by-step stpper motor can run without losing thehighest frequency. Subdivision Drive: stepper motor drives the main aim is to weaken or eliminate low-frequency vibration of the stepper motor to improve the accuracy of the motor running.Reduce noise.If the step angle is 1.8 degrees(full step) the two-phase hybrid stepping motor,if the breakdown of the breakdown of the number of drives for the 8,then the operation of the electrical pulse for each resolution of 0.072 degrees,the precision of motor can reach or close to 0.225 degrees,also depends on the breakdown of the breakdown of the drive current control accuracy and other factors,the breakdown of the number of the more difficult the greater the precision of control.中文步进电机应用和控制步进电机是将电脉冲转换成角位移的执行机构。
51单片机英文文献及翻译
Data Memory
数据存储器
Te context with microcontrollers,
术语“数据存储器”用于微控制器。
The memory which stores data,i.e.RAM,is called data memory.
用来存储数据的存储器，即RAM，被称作数据存储器
The diffenent versions of 8048 series of microcontrollers microcontrollers contain 64,128.256 bytes of RAM.
8048系列的不同版本的微控制器包含64、128、256字节的RAM。
Data Memory The term data memory is used in the context with microcontrollers,The memory which stores data,i.e.RAM,is called data memory.The diffenent versions of 8048 series of microcontrollers microcontrollers contain 64,128.256 bytes of RAM.The 8048AH,8049AH and 8050AH contain 64,128 and 256 bytes of RAM respectively.64/128/256 bytes of RAM is used either as read/write memory or general-purpose registers.
There is need of cyclical reading (lower than 1 minute periods) of the actual values from the real-time clock and the sensors for pressure and temperature, and to store the read values into the microcontroller’s memory. The communication with the real-time clock and the sensors is possible with the use of I2C interface and the previously defined in the specifications protocols for reading and writing.
基于51单片机的英文论文
the Real-Time Clock Based on AT89S51Author: Class: ; Name:Abstract: Digital clock has become indispensable in people's daily life, it is widely used in public places such as the family and the office, and it gives people great convenience in study, work and entertainment. Due to the development of digital integrated circuit technology and the advanced quartz technology, the digital clock has advantages of accurate, stable performance and easy to carry. It is also used in automatic control, automatic signal and etc. Although the digital clocks are already sold on the market, but the single chip microcomputer timer function also can complete the design of the digital clock circuit. So it is necessary to the design of the digital clock. By single chip microcomputer internal timer timing precision, the four digital tube display year, month, day, time, minutes and seconds. With the keyboard, users can be preset time, display the time, set the content, set time operation mode, etc.Keywords: AT89S51; clock; digital tube; keyboard switch; function Introduction: AT89S51 is a very suitable for the beginners of the single chip microcomputer, it is fully compatible with the traditional instruction system of 8051,8031.Can realize the following functions:1. Use the keyboard switch, show respectively the seconds, minutes, hour, day, month, year;2. Use the keyboard preset year, month, day, time, minutes and seconds;3. Can the countdown, the countdown units for minutes;4. Every second , the four decimal point shine once;5. Timing alarm clock function, a buzzer call reminder.6. The clock error daily is not more than 1 second.Methods:1.The minimum single chip microcomputer systemAT89S51 has the following standard functions: 8 k bytes Flash, 256 bytes RAM, and 32-bit I/O lines, a watchdog timer, two data pointer, three 16 timer/counter, a level 6 vector 2 interrupt structure, full duplex serial port, piece of crystals and the clock circuit . In idle mode, the CPU stops working, allows RAM, timer/counter, serial port and interrupt continue to work. In fall protection mode, RAM content are stored, has been frozen, single chip microcomputer stops all work, until the next interruption or hardware reset.2.The displayDisplay uses the method of dynamic LED digital tube to display, P0 port output characters code to display, position codes are controlled by P2.4 ~ P2.7. The cost of the dynamic display is very low, but the dynamic display occupies more resources of the CPU interface. The design uses 12 lines. In addition by the dynamic display refreshing, which takes part of the work time of the CPU. So for some higher demand control system, we should consider the time taken by the display.3.The keyboardKeyboard uses 4 * 4 matrix keyboard, by P2.0 ~ P2.3 for row line, P1.4 ~ P1.7 for column line, phalanxes of 4 * 4 are made, and using the method of scanning software can determine the key value of each key. In the design, each key can be used to input data and commands.4.The power supplyControl power supply can be provided by DC 12V voltage, the power supply can be used by stepping motor driver, at the same time through the three linear stabilizer 7805 to provide other circuit power supply; If you don't need to use stepper motor, the control system of the DC5V power supply can be collected from ordinary USB interface of the computer, as long as the USB connects a computer USB port, the other connects two core power interface of controller.5.Programming interfaceMicroprocessor uses AT89S51. AT89S51 has ISP online programming function, and P1.5 ~ P1.7 are for the programming interface and software compilation and debugging includes two processes:1. By using keil software programming, input source program, and then compile until no grammar mistakes, using compilation command hex into system files(suffix:hex).2. After connecting the power cord and programming line, start USBASP programming software. Select the chip microprocessors model in the selection of AT89S51. Open and load in the flash. Load in the hex into system files. Use erase commands to erase chip in the original program, with programming command to write new programs in AT89S51. After finished, reset the program running, observing the consequence. If there is any error, it is needed to re-open the Medwin and modify the source program, to create the hex file, and then repeat the above operation, to meet the design requirements.Results:Key:| 1 | 2 | 3 | 分秒|| 4 | 5 | 6 | 时分|| 7 | 8 | 9 | 月日|| 确定| 0 | 倒计时| 年|#include <reg51.h>#include<stdio.h>#define uchar unsigned charsbit P1_3=P1^3;sbit P3_2=P3^2;unsigned char t=0;unsigned char t1=50;unsigned char t2=59;unsigned char t3=23;unsigned char t4=7;unsigned char t5=60;unsigned char t6=60;unsigned char k1=4;uchar i;uchar c;uchar a[10]={0x81,0xED,0x43,0x49,0x2D,0x19,0x11,0xCD,0x01,0x09};uchar p[5];void delay(int MS){int i,j;for( i=0;i<MS;i++)for(j=0;j<1141;j++);}uchar encoder(uchar num) {uchar i;switch(num){case 0x11:i=0x11;break;case 0x12:i=0x12;break;case 0x14:i=0x13;break;case 0x18:i=0x14;break;case 0x21:i=0x15;break;case 0x22:i=0x09;break;case 0x24:i=0x06;break;case 0x28:i=0x03;break;case 0x41:i=0x00;break;case 0x42:i=0x08;break;case 0x44:i=0x05;break;case 0x48:i=0x02;break;case 0x81:i=0x16;break;case 0x82:i=0x07;break;case 0x84:i=0x04;break;case 0x88:i=0x01;break;}return(i);}uchar key_value(){uchar tem,s,t,n;P1&=0x0f;P2|=0x0f;;tem=P2;tem|=0xf0;s=~tem;P2&=0xf0;P1|=0xf0;;tem=P1;tem|=0x0f;t=~tem;s=s+t;n=encoder(s);return(n);}uchar key(void){uchar i;P2|=0x0f;P1&=0x0f;;i=P2;i|=0xf0;i=~i;return(i);}void show1(uchar i,uchar j){P0=a[j];P2=P2&0x0f;P2|=1<<(i+3);}void show(uchar i,uchar j,uchar k,uchar l){uchar a[10]={0x81,0xED,0x43,0x49,0x2D,0x19,0x11,0xCD,0x01,0x09};uchar b,c,d,e;b=a[i];c=a[j];d=a[k];e=a[l];P2&=0x0f;P2=0x1f;P0=b;delay(1);P2&=0x0f;P2=0x2f;P0=c;delay(1);P2=0x4f;P0=d;delay(1);P2=0x8f;P0=e;delay(1);}void year(void){while(key()==0){show1(4,2);delay(1);show1(3,0);delay(1);show1(2,1);delay(1);show1(1,3);delay(1);}}void monthday(void) {TMOD=0X01;TH0=0x4c;TR0=1;IE=0X82;TMOD=0x01;while(key()==0){show1(4,0);delay(1);show1(3,1);delay(1);show1(2,0);delay(1);show1(1,t4%10);delay(1);}}void hourminute(void) {TMOD=0X01;TH0=0x4c;TL0=0x00;TR0=1;IE=0X82;TMOD=0x01;while(key()==0){show1(4,t3/10);delay(1);show1(3,t3%10);delay(1);show1(2,t2/10);delay(1);show1(1,t2%10);delay(1);}}void minutesecond() {TMOD=0X01;TH0=0x4c;TL0=0x00;TR0=1;IE=0X82;while(key()==0){show1(4,t2/10);delay(1);show1(3,t2%10);delay(1);show1(2,t1/10);delay(1);show1(1,t1%10);delay(1);}}void jishi(void){TMOD=0X01;TH0=0x4c;TL0=0x00;TR0=1;IE=0X82;TMOD=0x01;while(key()==0){show1(2,t5/10);delay(1);show1(1,t5%10);delay(1);}}void shuru(void) {--k1;if(k1==0)k1=4; while(key()==0){p[k1]=c;show1(4,c);delay(1);}}void sure(void){while(key()==0){show(p[1],p[2],p[3],p[4]);delay(1);}}void timer0(void) interrupt 1 {t++;if(t==20){t=0;t1++;t5--;if(t5==0){while(key()==0){show1(2,0);delay(1);show1(1,0);delay(1);P3_2=~P3_2;delay(1);P1_3=~P1_3;delay(1);}}t6--;if(t6==0){}if(t1==60){t1=0;t2++;if(t2==60){t2=0;t3++;if(t3==24){t3=1;t4++;if(t4==30)t4==1;}}}}TH0=0x4c;TL0=0x00;}void main(){while(1){i=key();while(i!=0){if(i==key()){uchar k;k=key_value();c=k;if(c==0x11)year();elseif(c==0x12)monthday();elseif(c==0x13)hourminute();elseif(c==0x14)minutesecond();elseif(c==0x15)jishi();elseif(c==0x16)sure();elseif(c==0x00||0x01||0x02||0x03||0x04||0x05||0x06||0x07||0x08||0x09) shuru();else;}elsebreak;}}}Conclusion: Through the single chip microcomputer can accurately realize the accurate per time, can realize the countdown, display determined year, month, day, hour, minutes, seconds, and some other functions.Reference:[1]郭晓林.基于单片机的电子时钟设计[J].中国科技博览，2010，（9).[2]何立民.单片机应用技术选编（11）［M］．北京航天航空大学出版社，2006．[3]刘守义.单片机应用技术［M］．西安电子科技大学出版社，2009.[4]时钟芯片DS1302中文资料，/info/commonIC/0083003.html。
关于单片机的英文文献
The General Situation of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU withabove average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.1-3Pin DescriptionVCC Supply voltage.GND Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs .Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 alsoreceives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special feature soft the AT89C51 as listed below:RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin all receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quarts crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to externalmemory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFR but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.2.1Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmedcode data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.2.2 Chip Erase:The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.2.3 Reading the Signature Bytes:The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows : (030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming2.4 Programming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the。
关于单片机的英文文献
The General Situation of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, abilityto service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.1-3Pin DescriptionVCC Supply voltage.GND Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs .Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special feature soft the AT89C51 as listed below:RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin all receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quarts crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the devicenormally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFR but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.2.1Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.2.2 Chip Erase:The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.2.3 Reading the Signature Bytes:The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows : (030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming2.4 Programming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function ofany interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for digital-to-analog converter. This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned to a form suitable for operating an actuator. The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPU’s window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be drivento either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions. Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.。
外文翻译--基于51单片机温度报警器的设计(适用于毕业论文外文翻译+中英文对照)
外文翻译--基于51单片机温度报警器的设计(适用于毕业论文外文翻译+中英文对照)XXX: Design of a Temperature Alarm Based on 51 MCUDepartment: n EngineeringMajor: Measurement and Control Technology and nClass:Student ID:Name:Supervisor:Date:A microcontroller。
also known as a single-chip computer system。
XXX its ns being integrated on a small chip。
it has most of the components needed for a complete computer system。
such as CPU。
memory。
internal and external bus systems。
and mostof them also have external storage。
At the same time。
it integrates XXX interfaces。
timers。
real-time clocks。
etc。
The most XXX integrate sound。
image。
ork。
and complex input-output systems on a single chip.XXX used in the industrial control field。
Microcontrollers XXX CPUs inside the chip。
The original design concept was to integrate a large number of peripheral devices and CPUs on a chip to make the computer system XXX's Z80 was the first processor designed according to this concept。
关于单片机的英文文献(可编辑修改word版)
The General Situation of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi- threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension,antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost- effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.1.2The AT89C51 provides the following standard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16- bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.1-3Pin DescriptionVCC Supply voltage.GND Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs .Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high- order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8- bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internalpull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special feature soft the AT89C51 as listed below:RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin all receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on- chip oscillator, as shown in Figure 1. Either a quarts crystal orceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power- down is a hardware reset. Reset redefines the SFR but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3.Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.2.1Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.2.2Chip Erase:The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.2.3Reading the Signature Bytes:The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 andP3.7 must be pulled to a logic low. The values returned areas follows :(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming2.4Programming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for digital-to- analog converter. This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned to a form suitable for operating an actuator. The signals used within microcomputer circuits are almost always too small to be con nected directly to the outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers.We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPU’s window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions. Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.。
关于单片机的英文文献
The General Situation of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, abilityto service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.The AT89C51 provides the following standard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.1-3Pin DescriptionVCC Supply voltage.GND Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs .Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special feature soft the AT89C51 as listed below:RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin all receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quarts crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the devicenormally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFR but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following . Input the desired memory location on the address . Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on . Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. is pulled low after ALE goes high during programming to indicate BUSY. is pulled high again when programming is done to indicate READY.Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase:The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes:The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that and must be pulled to a logic low. The values returned areas follows : (030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between theexternal and internal forms is carried out in a number of steps. An analog-to-digital converter is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for digital-to-analog converter. This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned to a form suitable for operating an actuator. The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPU’s window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions. Some typeof serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.。
（完整版）51单片机外文文献
（完整版）51单⽚机外⽂⽂献The Introduction of AT89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel 'hsigh-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one 5 vector two-level interrupt architecture, a full duplex serial port, one-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also be configured to be the multiplexedaddress/data bus during accessesto external program and data memory. In this mode P0 has internal Pull-up resistor . Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during Program verification . External Pull-up resistors are required during Program verification .Port 1Port 1 is an 8-bit bi-directional I/O port with internal Pull-up resistors. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal Pull-up resistors and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal Pull-up resistors. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal Pull-up resistor . The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal Pull-up resistor and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current, because of the internal Pull-up resistor . Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal Pull-up resistor when emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verificati on.Port 3Port 3 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 3 output buffers can sin k/source four TTL in puts. When 1s are writte n to Port 3 pins they are pulled high by the internal Pull-up resistor and can be used as in puts. As in puts, Port 3 pins that are exter nally being pulled low will source curre nt (IIL) because of the Pull-up resistor. Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset in put. A high on this pin for two mach ine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. Withthe bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51is executing code from external program memory, PSENis activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the in put and output, respectively, of an inverting amplifier which can be con figured for use as an on-chip oscillator, as show n in Figure 1.Either a quartz crystal or ceramic reson ator may be used. To drive the device from an exter nal clock source, XTAL2 should be left unconn ected while XTAL1 is drive n asshow n in Figure 2.There are no requireme nts on the duty cycle of the exter nal clock sig nal, since the in put to the internal clock ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Con figurati onC2T ⼘C1NG EXTERNALOSCILLATOR SIGNALftNDXTAL2XTAL1GNDFigure 1. Oscillator Connections Figure 2. External Clock DriveXTAL2X1AL1Idle ModeIn idle mode, the CPU puts itself to sleep while all the on chip peripherals rema in active. The mode is inv oked by software. The content of the on-chip RAM and all the special fun cti ons registers rema in un cha nged duri ng this mode. The idle mode can be term in ated by any en abled in terrupt or by a hardware reset. It should be no ted that whe n idle is termi nated by a hard ware reset, the device no rmally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this eve nt, but access to the port pins is not in hibited. To elimi nate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to exter nal memory.Power-dow n ModeIn the power-dow n mode, the oscillator is stopped, and the in struct ion that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its no rmal operat ing level and must be held active long eno ugh to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.Whe n lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a ran dom value, and holds that value un til reset is activated. It is n ecessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.译⽂:AT89C51的介绍描述AT89C51是⼀个低电压，⾼性能CMOS 8位单⽚机带有4K字节的可反复擦写的程序存储器（PENROM。
基于51单片机的智能照明控制系统的设计外文文献翻译、中英文翻译
附录C 外文翻译基于51单片机的智能照明控制系统的设计关键词：AT89C51；单片集成电路；照明控制系统摘要：随着智能建筑的发展和成熟，节能成为一种趋势，照明控制系统越来越普及。
同时，随着电子技术的飞速发展，以微型计算机为核心的嵌入式控制系统取代了传统的电子控制系统，基于单片机的控制系统在智能建筑中得到了广泛的应用。
本文针对公共场所的耗电浪费现象，以AT89C5 1为核心，提出了一种热释电红外传感器的测量和智能照明控制系统的光组合。
通过判断光强和室内是否有人自动切换灯，达到节能的目的。
引言近年来，随着经济的发展和技术的进步，人们对照明的要求越来越高。
传统的照明控制系统技术受到时代的强烈冲击，“智能照明”技术迅速出现和发展。
据统计，在建筑能耗中，仅照明占33%。
据测算，这种现象消耗电力占其单位耗电量的40%左右，因此照明节能显得很重要。
目前国内外常用的节能开关主要有语音控制、触摸、感光等。
这些类型的开关都有自己的缺点。
例如，语音式的不适合嘈杂的地方，触摸式的能自动关闭但不能自动打开，光敏式的在无人时不能自动关闭。
在本研究中，通过设计一种智能节能控制系统来替代现有产品是一项非常有意义的工作。
系统结构和工作原理本设计结合了AT89C51单片机、LED显示技术，红外传感、光传感技术、延时技术、关键采集和处理技术实现了照明的智能控制，结构如图1所示。
其原理是：第一、单片机通过继电器实现对光设备的开闭。
第二、单片机通过照明检测电路对照明附件周边亮度进行检测，如果亮度满足生活需要保持照明附件关闭；如亮度不足单片机检测是否采集人体热释电信号。
第三、如果检测人体信号，单片机立即控制照明附件打开；如果该芯片未检查人体信号，单片机控制照明附件继续保持关闭位置。
第四、当照明打开时，如果单片机在一个时间信号被延迟一段时间时没有检测到人体，那么如果检测到人体延迟的结束，则在信号中出现延迟。
第五、根据不同场所和人员的使用，可以通过设置P1.0-P1.4引脚的状态来设定不同的延时值。
关于单片机的英文文献
时磊忖呎…The General Situation of AT89C51Microc on trollers are used in a multitude of commercial applicatio ns such as modems, motor-c on trol systems, air con diti oner con trol systems, automotive engine and amongothers. The high processing speed and enhanced peripheral set of these microc on trollers make them suitable for such high-speed event-based applications. However, these critical applicati on doma ins also require that these microc on trollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers b oth at the component and at the system level.In tel Platform Engin eeri ng departme nt developed an object-orie ntedmulti-threaded test environment for the validation of its AT89C51 automotive microco ntrollers. The goals of this en vir onment was not only to provide a robust testing environment for the AT89C51 automotive microc on trollers, but to develop an en vir onment which canbe easily extended and reused for the validation of several other future microcontrollers. T he environment was developed in conjunctionwith Microsoft Foun dati on Classes (AT89C51). The paper describes the desig n and mecha nism of this test en vir onmen t, its in teract ions with varioushardware/software en vir onmen tal comp onen ts, and how to use AT89C51.1.1 In troduct ionThe 8-bitAT89C51 CHMOSnicrocontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microc on trollers are typically used for high-speed eve nt con trol systems. Commercial applications include modems,motor-control systems, printers,photocopiers, air con diti oner con trol systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in airbags, suspension systems, and antilock The AT89C51 is especially well suited to from its processing speed and enhanced on-chipsuch as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliableengin e-c on trol systems, brak ing systems (ABS).applications that benefit peripheral fun cti ons set,cost-effective controller with a low interrupt latency response, ability------------------- 时磊5说----- ----- -------时磊忖呎…to service the high nu mber of time and eve nt drive n in tegrated peripherals needed in real time applications, and a CPUWith above average processing power in a single package. The financial and legal risk of having devicesthat operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the samecoreand/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both thecomp onent level and system level un der worst case en vir onmen tal and voltage con diti ons. This complete and thorough validati on n ecessitates not only a well-defi ned process but also a proper en vir onment and tools to facilitate and execute the missi on successfully. In tel Chan dler Platform Engin eeri ng group provides post silic on system validati on (SV)of various micro-controllers and processors. The system validationprocess can be broke n into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the follow ing sta ndard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Modestops the CPUwhile allowing the RAM,timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAMsontents but freezes the oscillator disabling all other chip fun cti ons un til the n ext hardware reset.1-3Pin DescriptionVCC Supply voltage.GND Grou nd.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL in puts. Whe n 1s are writte n to port 0 pins, the pins can be used as high impeda nee in puts .Port 0 may also be con figured to be the multiplexed low order address/data bus duri ng accesses to exter nal program and data memory .In this modePO has internal pullups. Port 0 also receives the code bytes duri ng Flash program ming, and outputs the code bytes during program verification. External pullupsare required during program verification.Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sin k/source four TTL in puts. Whe n 1s are writte n to Port 1 pins they are pulled high by the internal pullups and can be used as in puts. As in puts, Port 1 pins that are exter nally being pulled low will source current (IIL) because of the internal pullups. Port1 also receives the low-order address bytes during Flash programming and verificati on.Port 2 : Port 2 is an 8-bit bi-directional I/O port with internalpullups. The Port 2 output buffers can sin k/source four TTL in puts. Whe n 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as in puts. As in puts, Port 2 pins that are exter nally being pulled low will source current (IIL) because of the internal pullups. Port2 emits the high-order address byte during fetches from external program memoryand during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte duri ng fetches from exter nal program memoryand duri ng accesses to exter nal data memory that use 16-bit addresses(MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX@RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sin k/source four TTL in puts. Whe n 1s are writte n to Port 3 pi ns they are pulled high by the internal pullups and can be used as in puts. As in puts, Port 3 pins that are exter nally being pulled low will source curre nt (IIL) because of the pullups.Port 3 also serves the functions of various special feature soft the AT89C51 as listed below:RST Reset in put. A high on this pin for two machi ne cycles while the oscillator时磊忖呎…is running resets the device.------------------- 时磊忖呎... ..... .... ..ALE/PROG Address Latch Enable output pulse for latching the low byte of the address duri ng accesses to exter nal memory. This pin is also the program pulse in put (PROG)duri ng Flash program ming. In no rmal operati on ALE is emitted at a constant rate of 1/6 the oscillator frequency, and maybe used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped duri ng each access to exter nal Data Memory. If desired, ALE operati on can be disabled by sett ing bit 0 of SFR locatio n 8EH. With the bit set, ALEis active only during a MOVXr MOV(^struction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN Program Store Enable is the read strobe to external program memory. When theAT89C51 is executi ng code from exter nal program memory, PSEN is activated twice each machine cycle, except that two PSEN activati ons are skipped duri ng each access to exter nal data memory.EA/VPP External Access En able. EA must be strapped to GND in order to enable the device to fetch code from external program memorylocations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EAshould be strapped to VCCfor internal program executions. This pin all receives the 12-voltprogramming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1 In put to the in vert ing oscillator amplifier and in put to the internal clock operati ng circuit.XTAL2:Output from the inverting oscillator amplifier. Oscillator CharacteristicsXTALI and XTAL2 are the in put and output, respectively, of an inverting amplifier which can be con figured for use as an on-chip oscillator, as shown in Figure 1. Either a quarts crystal or ceramic resonator maybe used. To drive the device from an external clock source, XTAL2should be left unconnected whileXTAL1is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the in put to the in ternal clock ing circuitry is through adivide-by-two flip-flop, but minimumand maximum/oltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals rema in active. The mode is invoked by software. The content of the on-chip RAM^nd all the special fun cti ons registers rema in un cha nged duri ng this mode. The idle modeca n be term in ated by any en abled in terrupt or by a hardware reset. It should be no ted that whe n idle is termi nated by a hard ware reset, the device时磊忖呎…no rmally resumes program executi on, from where it left off, up to twomachine cycles before the internal reset algorithm takes control. On-chip hardware in hibits access to internal RAMn this eve nt, but access to the port pins is not in hibited. To elim in ate the possibility of a n un expected write to a port pin when Idle is terminated by reset, the instruction follow ing the one that inv okes Idle should not be one that writes to a port pin or to exter nal memory.Power-dow n ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values un til the power-dow n mode is term in ated. The only exit from power-dow n is a hardware reset.Reset redefi nes the SFR but does not cha nge the on-chip RAM. The reset should not be activated before VCC is restored to its no rmal operat ing level and must be held active long eno ugh to allow the oscillator to restart and stabilize. TheAT89C51code memoryarray is programmedbyte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memorymust be erased using the Chip Erase Mode.2 Programmi ng AlgorithmBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming modetable and Figure 3 and Figure 4. To program the AT89C51, take the follow ing steps.1. In put the desired memorylocatio n on the address lin es.2. In put the appropriate data byte on the data lin es. 3. Activate the correct comb in ati on of con trol signals. 4. Raise EA/VPP to12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lockbits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, cha nging the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle.During a write cycle, an attempted read of the last byte written willresult in the complement of the written datum on PO.7. Oncethe write cycle has been completed, true data are valid on all outputs, and the next cycle may begi n. Data Polli ng may beg in any time after a write cycle has bee n in itiated.2.1Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to in dicate BUSY. P3.4 is pulled high aga in whe n program ming is done to in dicate READY.Program Verify:If lock bits LB1 a nd LB2 have not bee n programmed, the programmedcode data can be read back via the address and data lines for verification.The lock bits cannot be verified directly. Verification of the lock bitsis achieved by observing that their features are enabled.2.2 Chip Erase:The en tire Flash array is erased electrically by using the propercomb in ati on of con trol sig nals and by holdi ng ALE/PROdbw for 10 ms. The code array is written with all “ 1 ” s. The chip erase operation must be executed before the code memory can be re-programmed.2.3 Read ing the Sig nature Bytes:The sig nature bytes are read by the same procedure as a no rmal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows :(030H) = 1EH in dicates man ufactured by Atmel(031H) = 51H in dicates 89C51(032H) = FFH in dicates 12V programmi ng(032H) = 05H in dicates 5V programmi ng2.4 Programmi ng In terfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate comb in ati on of con trol sig nals.The write operation cycle is self timed and once initiated, willautomatically time itself to completi on. A microcomputer in terface converts in formatio n betwee n two forms. Outside the microcomputer the in formati on han dled by an electr onic system exists as a physical sig nal, but within the program, it is represented numerically. The function ofany in terface can be broke n dow n into a nu mber of operati ons which modify the data in some way, so that the process of conv ersi on betwee n the external and internal forms is carried out in a number of steps. An an alog-to-digital con verter is used to convert a con ti nu ously variable signal to a corresponding digital form which can take any one of a fixed nu mber of possible binary values. If the output of the tran sducer does not vary con ti nu ously, no ADC is n ecessary .In this case the sig nal con diti oning sect ion must convert the incoming sig nal to a form which canbe conn ected directly to the n ext part of the in terface, the in put/output secti on of the microcomputer itself. Output in terfaces take a similar form, the obvious differenee being that here the flow of information is in the opposite directi on; it is passed from the program to the outside world.In this case the program may call an output subroutine which supervises the operati on of the in terface and performs the scali ng nu mbers which maybe needed for digital-to-analog converter. This subroutine passesin formati on in tur n to an output device which produces a corresp onding electrical sig nal, which could be conv erted in to an alog form using a DAC. Fin ally the sig nal is con diti oned to a form suitable for operati ng an actuator. The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world ” and some kind of in terface must be used to tran slate them to a more appropriate form. The desig n of secti on of in terface circuits is one of the most importa nt tasks facing the engin eer wishi ng to apply microcomputers. We have see n that in microcomputers in formati on is represe nted as discrete patter ns of bits; this digital form is most useful whe n the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world problems, a microc on troller must have more tha n just a CPU, a program, and a data memory .In additi on, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers in formatio n and processes the data, it must also be able to effect change on someportion of the outside world. These hardware devices, called peripherals, are the CPU ' s window to the outside.The most basic form of peripheral available on microc on trollers is the gen eral purpose I70 port. Each of the I/O pins can be used as either an in put or an output. The fun cti on of each pin is determ ined by sett ing or cleari ng corresp onding bits in a corresp onding data directi on register during the initialization stage of a program. Each output pin maybe driven------------------- 时磊5说------ - ---- ------- to either a logic one or a logic zero by using CPU instructions to pinmay be viewed (or read.) by the CPUUsing program instructions. Sometype of serial unit is included on microcontrollers to allow the CPU to com muni cate bit-serially with exter nal devices. Using a bit serial format in stead of bit-parallel format requires fewer I/O pins to perform thecom muni cati on fun cti on, which makesit less expe nsive, but slower. Serial tran smissi ons are performed either synchrono usly or asynchrono usly.。
51单片机论文英语文翻译
英文原文DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Block DiagramVCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers cansink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers cansink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers cansink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receivessome control signals forFlash programming andverification.RSTReset input. A high onthis pin for two machinecycles while the oscillator isrunning resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin orto external memory.Power Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:If the device is powered up without a reset, the latch initializes to a random value, and holds that valueuntil reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash：The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled.program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: T he entire Flash Programmable and Erasable Read Only Memory array is erasedelectrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated,will automatically time itself to completion.Figure 3. Programming the Flash Figure 4. Verifying the FlashFlash Programming and Verification CharacteristicsNote: 1. Only used in 12-volt programming mode.Flash Programming and Verification Waveforms - High Voltage Mode (VPP = 12V)Flash Programming and Verification Waveforms - Low Voltage Mode (VPP = 5V)Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°CStorage Temperature ..................................... -65°C to +150°CVoltage on Any Pinwith Respect to Ground .....................................-1.0V to +7.0VMaximum Operating Voltage............................................. 6.6VDC Output Current...................................................... 15.0 mADC CharacteristicsMaximum IOL per port pin: 10 mAMaximum IOL per 8-bit port: Port 0: 26 mAPorts 1, 2, 3: 15 mAMaximum total IOL for all output pins: 71 mA2. Minimum VCC for Power Down is 2V.AC Characteristics(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF)External Program Memory Read CycleExternal Data Memory Read CycleExternal Data Memory Write CycleExternal Clock Drive WaveformsShift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1)Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.Float Waveforms(1)Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH/VOL level occurs.Ordering Information– Reserved bits.. Reset value depends on reset source.描述AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
单片机 外文翻译 外文文献 英文文献 中英对照 基于C51兼容微(宝典)
附录A 英文原文Design of PWM Controller in a MCS-51 Compatible MCUAuthor . Yue-Li Hu Wei Wang Microelectronic Research Development Center CampusP.O.B.221 149 Yanchang Rd Shanghai 200072 China Introduction PWM technology is a kind of voltage regulation method by controlling the switchfrequency of DC power with fixed voltage to modify the two-end voltage of load. Thistechnology can be used for a variety of applications including motor control temperaturecontrol and pressure control and so on. In the motor control system shown as Fig. 1 throughadjusting the duty cycle of power switch the speed of motor can be controlled. As shown inFig. 2 under the control of PWM signal the average of voltage that controls the speed ofmotor changes with Duty-cycle D t1/T in this Figure thus the motor speed can beincreased when motor power turn on decreased when power turn off.Fig.1: The Relationship between Voltage of Armature and Fig.2 Architecture of PWM Module Therefore the motor speed can be controlled with regularly adjusting the time of turn-onand turn-off. There are three methods could achieve the adjustment of duty cycle: 1 Adjustfrequency with fixed pulse-width. 2 Adjust both frequency and pulse-width. 3 Adjustpulse-width with fixed frequency. Generally there are four methods to generate the PWM signals as the following: 1Generated by the device composed of separate logic components. This method is the originalmethod which now has been discarded. 2 Generated by software. This method need CPU tocontinuously operate instructions to control I/O pins for generating PWM output signals sothat CPU can not do anything other. Therefore the method also has been discarded gradually.3 Generated by ASIC. The ASIC makes a decrease of CPU burden and steady workgenerally has several functions such as over-current protection dead-time adjustment and soon. Then the method has been widely used in many kinds of occasion now. 4 Generated byPWM function module of MCU. Through embedding PWM function module in MCU andinitializing the function PWM pins of MCU can also automatically generate PWM outsignals without CPU controlling only when need to change duty-cycle. It is the method thatwill be implemented in this paper. In this paper we propose a PWM module embedded in a 8051 microcontroller. ThePWM module can support PWM pulse signals by initializing the control register andduty-cycle register with three methods just mentioned above to adjust the duty cycle andseveral operation modes to add flexibility for user. The following section explains the architecture of the PWM module and the architecturesof basic functional blocks. Section3 describes two operation modes. Experimental andsimulation results verifying proper system operation are also shown in that section.Depending on mode of operation the PWM module creates one or more pulse-widthmodulated signals whose duty ratios can be independently adjusted. Implementation of PWM module in MCU Overview of the PWM module A block diagram of PWM module is shown in Fig.3. It is clearly from the diagram thatthe whole module is composed of two sections: PWM signal generator and dead-timegenerator with channel select logic. The PWM function can be started by the user throughimplementing some instructions for initializing the PWM module. In particular the followingpower and motion control applications are supported: DC Motor Uninterruptablel Power Supply UPSThe PWM module also has the following features: Two PWM signal outputs with complementary or independent operation Hardware dead-time generators for complementary mode Duty cycle updates are configurable to be immediated or synchronized to the PWM Fig.3 Architecture of PWM Module Details of the architecture PMW generator The architecture of the 2-output PWM generator shownin Fig.4 is based on a 16-bitresolution counter which creates a pulse-width modulated signal. The system is synthesizedby a system clock signal whose frequency can be divided by 4 times or 12 times throughsetting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON asshown in Fig.4. To PWM0 generator the clock to 16-bit counter will be pre-divided by 4times by default when T3M is set to zero. And the clock will be divided by 12 times whenT3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained indetail in Table 1. Fig .4 Bit Mapping of PWMCON Table 1: The Bit Definition in PWMCONChannel-select logic The follow Fig. 5 shows the channel-select logic which is useful in ComplementaryMode. From this diagram it is clear to know that signal CP and CPWM control the source ofPWMH and PWML. And the details about the two control signals will be discussed in thesection 3 and the architecture of dead-time generator will also be discussed in section 5 forthe continuity of Complementary Mode. Fig. 5 Diagram of Channel-select LogicOperation Mode and Simulation Results The design has two operation modes: Independent Mode and Complimentary Mode. Bysetting the corresponding bit CPWM in register PWMCON shown in Fig.6 user can select oneof the two operation modes. When CPWM is set to zero PWM module will work inIndependent Mode whereas PWM module will work in Complimentary Mode. In thefollowing of this section the two operation mode will be explained respectively in detail andthe simulation results of the PWM module from the Synoposys VCS EDA platform whichverify the design will also be shown.Independent PWM Output Mode An Independent PWM Output mode is useful for driving loads such as the one shown inFigure 6. A particular PWM output is in the Independent Output mode when thecorresponding CP bit in the PWMCON register is set to zero.In this case two-channel PWMoutputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0generator and the signal on pin PWM1/PWML is from PWM0 generator. The separate case isachieved by the channel-select logic shown in Fig. 6. The PWM I/O pins are set toindependent mode by default upon advice reset. The dead-time generator is disabled in theIndependent mode. The simulation result is shown in Figure 6 as the following Fig.6 Tr4 andtr3 are run bits to PWM0 and PWM1 respectively. Actually from this diagram Pin P15/P14 of MCU is used for PWMH/ PWML or normal I/O alternatively. Fig6 the Waveform of PWM Outputs in Independent ModeComplementary PWM Output Mode The Complementary Output mode is used to drive inverter loads similar to the oneshown in Figure 7. This inverter topology is typical for DC applications. In ComplementaryOutput Mode the pair of PWM outputs cannot be active simultaneously. The PWM channeland output pin pair are internally configured through channel-select logic as shown in Figure7.A dead-time may be optionally inserted during device switching where both outputs areinactive for a short period. Fig 7 : Typical Load for Complementary PWM Outputs The Complementary mode is selected for PWM I/O pin pair by setting the appropriateCPWM bit in PWMCON. In this case PSEL is in effect. PWMH and PWML will come fromPWM0 generator when PSEL is set to zero when the signals from PWM1 generator is uselesswhereas PWMH and PWML will come from PWM1 generator when PSEL is set to 1 whenthe signals from PWM0 generator is useless. In the process of producing the PWM outputs inComplementary Mode the dead-time will be inserted to be discussed in the following section.Dead-time Control Dead-time generation is automatically enabled when PWM I/O pin pair is operating inthe Complementary Output mode. Because the power output devices cannotswitchinstantaneously some amount of time must be provided between the turn-off event of onePWM output in a complementary pair and the turn-on event of the other transistor. The2-output PWM module has one programmable dead-time with 8-bitregister.Thecomplementary output pair for the PWM module has an 8-bit down counter that is used toproduce the dead-time insertion. As shown in Figure 8 the dead time unit has a rising andfalling edge detector connected to PWM signal from one of PWM generator. The dead timesis loaded into the timer on the detected PWM edge event. Depending on whether the edge isrising or falling one of the transitions on the complementary outputs is delayed until the timercounts down to zero. A timing diagram indicating the dead time insertion for the pair of PWMoutputs is shown in Figure 8a. Fig 8a Dead-time Unit Block Diagram Fig. 8b the Waveforms of PWM Outputs in Complementary ModeConclusions In this paper we have designed PWM module based on an 8-bit MCU compatible with8051 family. The design can generate 2-channel programmable periodic PWM signals withtwo operation mode Independent Mode and Complementary Mode in which dead-time willbe inserted. The simulation results on the EDA platform have proven its correctness andusefulness. 附录B 汉语翻译基于C51 兼容微处理器单片机的PWM 控制器设计Yue-Li Hu Wei Wa 单片机研究与开发中心Campus P.O.B.221 149Yanchang Rd Shanghai 200072 China 导言PWM 技术，是一种电压调节方法，通过控制具有固定电压的直流电源的开关频率来调整两端负荷电压。
(完整word版)关于单片机的英文文献
The General Situation of AT89C51Microcontrollers are used in a multitude of commercial applicationssuch as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for suchhigh-speed event-based applications. However, these critical application domains also require that these microcontrollers are highlyreliable. The high reliability and low market risks can be ensured by arobust testing process and a proper tools environment for the validationof these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not onlyto provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the designand mechanism of this test environment, its interactions with varioushardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, m otor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliablecost-effective controller with a low interrupt latency response, ability。
单片机英文文献 免费
单片机英文文献Principle of MCUSingle-chip is an integrated on a single chip a complete computer system. Even though most of his features in a small chip, but it has a need to complete the majority of computer components: CPU, memory, internal and external bus system, most will have the Core. At the same time, such as integrated communication interfaces, timers, real-time clock and other peripheral equipment. And now the most powerful single-chip microcomputer system can even voice, image, networking, input and output complex system integration on a single chip.Also known as single-chip MCU (Microcontroller), because it was first used in the field of industrial control. Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large number of peripherals and CPU in a single chip, the computer system so that smaller, more easily integrated into the complex and demanding on the volume control devices. INTEL the Z80 is one of the first design in accordance with the idea of the processor, From then on, the MCU and the development of a dedicated processor parted ways.Early single-chip 8-bit or all of the four. One of the most successful is INTEL's 8031, because the performance of a simple and reliable access to a lot of good praise. Since then in 8031 to develop a single-chip microcomputer system MCS51 series. Based on single-chip microcomputer system of the system is still widely used until now. As the field of industrial control requirements increase in the beginning of a 16-bit single-chip, but not ideal because the price has not been very widely used. After the 90's with the big consumer electronics product development, single-chip technology is a huge improvement. INTEL i960 Series with subsequent ARM in particular, a broad range of applications, quickly replaced by 32-bit single-chip 16-bit single-chip high-end status, and enter the mainstream market. Traditional 8-bit single-chip performance has been the rapid increase in processing power compared to the 80's to raise a few hundred times. At present, the high-end 32-bit single-chip frequency over 300MHz, the performance of the mid-90's close on the heels of a special processor, while the ordinary price of the model dropped to one U.S. dollars, the most high-end models, only 10 U.S. dollars. Contemporary single-chip microcomputer system is no longer only the bare-metal environment in the development and use of a large number of dedicated embedded operating system is widely used in the full range of single-chip microcomputer. In PDAs and cell phones as the core processing of high-end single-chip or even a dedicated direct access to Windows and Linux operating systems.More than a dedicated single-chip processor suitable for embedded systems, so it was up to the application. In fact the number of single-chip is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will have a single-chip integration. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse in the Department are equipped with 1-2 single chip. And personal computers also have a large number of single-chip microcomputer in the workplace. Vehicles equipped with more than 40 Department of the general single-chip, complex industrial control systems and even single-chip may have hundreds of work at the same time! SCM is not only far exceeds the number of PC and other integrated computing, even more than the number of human beings.Hardwave introductionThe 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a company's entire line of products since it can perform many functions and developers will only have to learn this one platform.The basic architecture consists of the following features:·an eight bit ALU·32 descrete I/O pins (4 groups of 8) which can be individually accessed·two 16 bit timer/counters·full duplex UART· 6 interrupt sources with 2 priority levels·128 bytes of on board RAM·separate 64K byte address spaces for DA TA and CODE memoryOne 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).单片机原理单片机是指一个集成在一块芯片上的完整计算机系统。
关于51英语作文
关于51英语作文The art of crafting an impactful and engaging English essay is a skill that has been honed and refined over centuries. As students embark on their academic journeys, the ability to effectively communicate ideas, analyze complex topics, and present well-structured arguments becomes increasingly crucial. At the heart of this endeavor lies the 51 English essay a unique and powerful tool that allows individuals to showcase their linguistic prowess and critical thinking abilities.The 51 English essay derives its name from the fact that it is typically a composition of approximately 51 paragraphs. This structured approach, while seemingly daunting, offers a framework that enables writers to delve deeply into their chosen subject matter and present their findings in a coherent and compelling manner. The number 51 is not arbitrary but rather a reflection of the intricate balance between concision and comprehensiveness that the essay format demands.One of the primary advantages of the 51 English essay is its ability tofoster a deep level of engagement with the topic at hand. By dedicating a significant number of paragraphs to the exploration of a single idea or argument, writers are afforded the opportunity to meticulously examine various perspectives, analyze relevant evidence, and construct a well-reasoned narrative. This depth of analysis not only showcases the writer's intellectual prowess but also serves to captivate the reader, drawing them into the unfolding story and inviting them to contemplate the complexities of the subject matter.Moreover, the 51 English essay encourages a systematic and organized approach to writing. Each paragraph serves a specific purpose, whether it be introducing a new concept, providing supporting evidence, or transitioning seamlessly between ideas. This structured format helps writers to maintain a clear and coherent flow throughout the essay, ensuring that the reader can follow the progression of thought with ease. By adhering to this established framework, writers can effectively communicate their ideas and convey their message with a high degree of clarity and precision.In the realm of academic writing, the 51 English essay holds a particularly esteemed position. Universities and educational institutions often view this format as a hallmark of intellectual rigor and critical thinking. Students who demonstrate proficiency in crafting 51 English essays are often recognized for their ability to engage with complex topics, synthesize information from multiplesources, and present their findings in a compelling and well-organized manner.Beyond the academic sphere, the 51 English essay also holds relevance in the professional world. Many organizations and industries value the ability to communicate effectively through written communication. The skills developed in composing a 51 English essay can be readily applied to a wide range of professional contexts, from crafting persuasive business proposals to drafting impactful policy documents. The depth of analysis, the clarity of expression, and the overall organizational structure of the 51 English essay make it a highly sought-after skill in the workplace.However, the mastery of the 51 English essay is not without its challenges. Crafting a well-structured and engaging essay of this length requires a deep understanding of the subject matter, a keen eye for detail, and a strong command of the English language. Writers must navigate the delicate balance between providing comprehensive coverage of the topic and maintaining a concise and coherent narrative. Additionally, the sheer volume of content can be daunting, and writers must exercise discipline and focus to ensure that each paragraph contributes meaningfully to the overall essay.Despite these challenges, the rewards of mastering the 51 English essay are numerous. The process of researching, organizing, andcomposing such a comprehensive piece of writing not only enhances one's writing skills but also fosters critical thinking, problem-solving, and the ability to effectively communicate complex ideas. Furthermore, the successful completion of a 51 English essay can serve as a source of immense personal satisfaction and a testament to one's intellectual capabilities.In conclusion, the 51 English essay is a powerful and versatile tool that holds great significance in both academic and professional realms. Its structured approach, depth of analysis, and emphasis on clear and concise communication make it a hallmark of intellectual rigor and critical thinking. As students and professionals alike continue to hone their skills in this format, they will undoubtedly reap the benefits of enhanced communication abilities, deeper engagement with subject matter, and the opportunity to leave a lasting impact on their readers. The 51 English essay stands as a testament to the enduring value of effective written expression and the pursuit of excellence in the art of language.。
51单片机c语言程序设计经典实例的英文
51单片机c语言程序设计经典实例的英文English:"Embedded systems programming with C for microcontrollers is a classic area of study that encompasses a wide range of applications. Some classic examples include implementing a digital thermometer using a temperature sensor interfaced with a microcontroller, developing a simple alarm system with motion sensors and actuators, creating a digital clock with real-time functionality using timers and interrupts, designing a traffic light controller with different states and timings, and building a home automation system to control lights, appliances, and security features. These examples showcase the versatility and practicality of using C language in single-chip microcontroller programming, allowing developers to create efficient and reliable solutions for various electronic systems."中文翻译："使用C语言进行单片机的嵌入式系统编程是一个经典的研究领域，涵盖了广泛的应用范围。
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the Real-Time Clock Based on AT89S51Author: Class: ; Name:Abstract: Digital clock has become indispensable in people's daily life, it is widely used in public places such as the family and the office, and it gives people great convenience in study, work and entertainment. Due to the development of digital integrated circuit technology and the advanced quartz technology, the digital clock has advantages of accurate, stable performance and easy to carry. It is also used in automatic control, automatic signal and etc. Although the digital clocks are already sold on the market, but the single chip microcomputer timer function also can complete the design of the digital clock circuit. So it is necessary to the design of the digital clock. By single chip microcomputer internal timer timing precision, the four digital tube display year, month, day, time, minutes and seconds. With the keyboard, users can be preset time, display the time, set the content, set time operation mode, etc.Keywords: AT89S51; clock; digital tube; keyboard switch; function Introduction: AT89S51 is a very suitable for the beginners of the single chip microcomputer, it is fully compatible with the traditional instruction system of 8051,8031.Can realize the following functions:1. Use the keyboard switch, show respectively the seconds, minutes, hour, day, month, year;2. Use the keyboard preset year, month, day, time, minutes and seconds;3. Can the countdown, the countdown units for minutes;4. Every second , the four decimal point shine once;5. Timing alarm clock function, a buzzer call reminder.6. The clock error daily is not more than 1 second.Methods:1.The minimum single chip microcomputer systemAT89S51 has the following standard functions: 8 k bytes Flash, 256 bytes RAM, and 32-bit I/O lines, a watchdog timer, two data pointer, three 16 timer/counter, a level 6 vector 2 interrupt structure, full duplex serial port, piece of crystals and the clock circuit . In idle mode, the CPU stops working, allows RAM, timer/counter, serial port and interrupt continue to work. In fall protection mode, RAM content are stored, has been frozen, single chip microcomputer stops all work, until the next interruption or hardware reset.2.The displayDisplay uses the method of dynamic LED digital tube to display, P0 port output characters code to display, position codes are controlled by P2.4 ~ P2.7. The cost of the dynamic display is very low, but the dynamic display occupies more resources of the CPU interface. The design uses 12 lines. In addition by the dynamic display refreshing, which takes part of the work time of the CPU. So for some higher demand control system, we should consider the time taken by the display.3.The keyboardKeyboard uses 4 * 4 matrix keyboard, by P2.0 ~ P2.3 for row line, P1.4 ~ P1.7 for column line, phalanxes of 4 * 4 are made, and using the method of scanning software can determine the key value of each key. In the design, each key can be used to input data and commands.4.The power supplyControl power supply can be provided by DC 12V voltage, the power supply can be used by stepping motor driver, at the same time through the three linear stabilizer 7805 to provide other circuit power supply; If you don't need to use stepper motor, the control system of the DC5V power supply can be collected from ordinary USB interface of the computer, as long as the USB connects a computer USB port, the other connects two core power interface of controller.5.Programming interfaceMicroprocessor uses AT89S51. AT89S51 has ISP online programming function, and P1.5 ~ P1.7 are for the programming interface and software compilation and debugging includes two processes:1. By using keil software programming, input source program, and then compile until no grammar mistakes, using compilation command hex into system files(suffix:hex).2. After connecting the power cord and programming line, start USBASP programming software. Select the chip microprocessors model in the selection of AT89S51. Open and load in the flash. Load in the hex into system files. Use erase commands to erase chip in the original program, with programming command to write new programs in AT89S51. After finished, reset the program running, observing the consequence. If there is any error, it is needed to re-open the Medwin and modify the source program, to create the hex file, and then repeat the above operation, to meet the design requirements.Results:Key:| 1 | 2 | 3 | 分秒|| 4 | 5 | 6 | 时分|| 7 | 8 | 9 | 月日|| 确定| 0 | 倒计时| 年|#include <reg51.h>#include<stdio.h>#define uchar unsigned charsbit P1_3=P1^3;sbit P3_2=P3^2;unsigned char t=0;unsigned char t1=50;unsigned char t2=59;unsigned char t3=23;unsigned char t4=7;unsigned char t5=60;unsigned char t6=60;unsigned char k1=4;uchar i;uchar c;uchar a[10]={0x81,0xED,0x43,0x49,0x2D,0x19,0x11,0xCD,0x01,0x09};uchar p[5];void delay(int MS){int i,j;for( i=0;i<MS;i++)for(j=0;j<1141;j++);}uchar encoder(uchar num) {uchar i;switch(num){case 0x11:i=0x11;break;case 0x12:i=0x12;break;case 0x14:i=0x13;break;case 0x18:i=0x14;break;case 0x21:i=0x15;break;case 0x22:i=0x09;break;case 0x24:i=0x06;break;case 0x28:i=0x03;break;case 0x41:i=0x00;break;case 0x42:i=0x08;break;case 0x44:i=0x05;break;case 0x48:i=0x02;break;case 0x81:i=0x16;break;case 0x82:i=0x07;break;case 0x84:i=0x04;break;case 0x88:i=0x01;break;}return(i);}uchar key_value(){uchar tem,s,t,n;P1&=0x0f;P2|=0x0f;;tem=P2;tem|=0xf0;s=~tem;P2&=0xf0;P1|=0xf0;;tem=P1;tem|=0x0f;t=~tem;s=s+t;n=encoder(s);return(n);}uchar key(void){uchar i;P2|=0x0f;P1&=0x0f;;i=P2;i|=0xf0;i=~i;return(i);}void show1(uchar i,uchar j){P0=a[j];P2=P2&0x0f;P2|=1<<(i+3);}void show(uchar i,uchar j,uchar k,uchar l){uchar a[10]={0x81,0xED,0x43,0x49,0x2D,0x19,0x11,0xCD,0x01,0x09};uchar b,c,d,e;b=a[i];c=a[j];d=a[k];e=a[l];P2&=0x0f;P2=0x1f;P0=b;delay(1);P2&=0x0f;P2=0x2f;P0=c;delay(1);P2=0x4f;P0=d;delay(1);P2=0x8f;P0=e;delay(1);}void year(void){while(key()==0){show1(4,2);delay(1);show1(3,0);delay(1);show1(2,1);delay(1);show1(1,3);delay(1);}}void monthday(void) {TMOD=0X01;TH0=0x4c;TR0=1;IE=0X82;TMOD=0x01;while(key()==0){show1(4,0);delay(1);show1(3,1);delay(1);show1(2,0);delay(1);show1(1,t4%10);delay(1);}}void hourminute(void) {TMOD=0X01;TH0=0x4c;TL0=0x00;TR0=1;IE=0X82;TMOD=0x01;while(key()==0){show1(4,t3/10);delay(1);show1(3,t3%10);delay(1);show1(2,t2/10);delay(1);show1(1,t2%10);delay(1);}}void minutesecond() {TMOD=0X01;TH0=0x4c;TL0=0x00;TR0=1;IE=0X82;while(key()==0){show1(4,t2/10);delay(1);show1(3,t2%10);delay(1);show1(2,t1/10);delay(1);show1(1,t1%10);delay(1);}}void jishi(void){TMOD=0X01;TH0=0x4c;TL0=0x00;TR0=1;IE=0X82;TMOD=0x01;while(key()==0){show1(2,t5/10);delay(1);show1(1,t5%10);delay(1);}}void shuru(void) {--k1;if(k1==0)k1=4; while(key()==0){p[k1]=c;show1(4,c);delay(1);}}void sure(void){while(key()==0){show(p[1],p[2],p[3],p[4]);delay(1);}}void timer0(void) interrupt 1 {t++;if(t==20){t=0;t1++;t5--;if(t5==0){while(key()==0){show1(2,0);delay(1);show1(1,0);delay(1);P3_2=~P3_2;delay(1);P1_3=~P1_3;delay(1);}}t6--;if(t6==0){}if(t1==60){t1=0;t2++;if(t2==60){t2=0;t3++;if(t3==24){t3=1;t4++;if(t4==30)t4==1;}}}}TH0=0x4c;TL0=0x00;}void main(){while(1){i=key();while(i!=0){if(i==key()){uchar k;k=key_value();c=k;if(c==0x11)year();elseif(c==0x12)monthday();elseif(c==0x13)hourminute();elseif(c==0x14)minutesecond();elseif(c==0x15)jishi();elseif(c==0x16)sure();elseif(c==0x00||0x01||0x02||0x03||0x04||0x05||0x06||0x07||0x08||0x09) shuru();else;}elsebreak;}}}Conclusion: Through the single chip microcomputer can accurately realize the accurate per time, can realize the countdown, display determined year, month, day, hour, minutes, seconds, and some other functions.Reference:[1]郭晓林.基于单片机的电子时钟设计[J].中国科技博览，2010，（9).[2]何立民.单片机应用技术选编（11）［M］．北京航天航空大学出版社，2006．[3]刘守义.单片机应用技术［M］．西安电子科技大学出版社，2009.[4]时钟芯片DS1302中文资料，/info/commonIC/0083003.html。