设计高压侧栅极驱动电路与损耗

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IGBT的栅极驱动电路

SCALE系列驱动电路中应用较多的一种，是可驱动和保护大功率IGBT的专用集成驱动电路。该电路可广泛的应用于大功率电机控制器、弧焊电源、DC/DC变换器等领域。 2SD315A内部包含有两路IGBT驱动电路，可用于驱动两路IGBT，且具有安全性、智能性与易用性等特点。
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2. 2SD315A的内部结构
电，E点电位逐步下降，二极管D1导通使D点电位也逐步
下降，从而使EXB841引脚3的电位也逐步下降，慢慢关断IGBT。
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3.2.3 HR065 IGBT厚膜集成驱动电路
（1）内部结构和工作原理
输入脉冲信号经高速光耦合器隔离后，通过传输级即可送到输出级，产生正、负偏压加到 IGBT 栅极。
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T4、T5、D1及R4～R8、C1～C3 构成了过电流检测、故障信号输出电路及导通保持电路。
当IGBT正常导通时，引脚8和引脚1之间的电压（为IGBT
饱和压降与外接检测二极管正向压降之和）较低，故 DW1 中无电流通过，T5基极没有正向偏置而处于截止状态，故障输出端5、6之间无电压输出。
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①开通过程。
光电耦合器 OC1 导通，A点电位降到0 V，使T1和T2截止。T2截止使D点电位上升到20 V，T4导通，T5截止。 T4通过栅极电阻 RG 向 IGBT 的栅极提供一个驱动电流使其导通。
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①开通过程。
T1截止，使＋20 V电源通过R3向电容C2充电，B点电位上升，由于IGBT约1s后导通，uCE下降至3 V，从而将EXB841引脚6的电位钳制在8 V左右，因此，B点和C点电位只能到8 V左右。DW1 的稳压值为13 V 。
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EXB841集成驱动电路的原理图

高压栅极驱动 ic 自举电路的设计与应用指南(

一、概述高压栅极驱动IC自举电路是一种常用于驱动MOSFET等功率器件的电路，其设计与应用对于提高系统的性能和稳定性具有重要意义。

本文将从基本原理、设计要点和实际应用等方面，对高压栅极驱动IC自举电路进行全面系统的介绍和分析，旨在为工程师和研究人员提供一份全面且实用的指南。

二、基本原理1. 高压栅极驱动IC自举电路的概念高压栅极驱动IC（Integrated Circuit）自举电路是一种能够产生驱动信号所需的高压电源的电路，通常用于驱动功率开关器件（如MOSFET、IGBT等）。

2. 自举电路的工作原理自举电路通过外部电容器储存电荷，在需要驱动时将这部分电荷释放，从而形成高压供电。

该电路能够有效地提供驱动信号所需的高电压，同时具有简单、高效等特点。

三、设计要点1. 电容器的选择在设计高压栅极驱动IC自举电路时，电容器的特性对电路的性能具有重要影响。

电容器的选择应考虑其容量、工作电压和频率特性等。

2. 电源管理电路自举电路需要有稳定可靠的电源管理电路，来保证其供电过程的稳定性和可靠性。

在设计时应选用合适的稳压器、电源管理IC等器件。

3. 驱动信号的匹配高压栅极驱动IC自举电路应能够有效地匹配待驱动器件的输入电压和电流要求，以确保系统的性能和稳定性。

四、实际应用1. 在功率电子系统中的应用高压栅极驱动IC自举电路广泛应用于各种功率电子系统中，如电源逆变器、电机驱动器、变流器等。

2. 在新能源领域的应用随着新能源技术的快速发展，高压栅极驱动IC自举电路在太阳能、风能等领域得到了广泛的应用，为新能源系统的高效工作提供了重要支持。

五、总结高压栅极驱动IC自举电路作为一种常见的功率器件驱动方案，在现代电子系统中具有重要的应用价值。

本文通过对其基本原理、设计要点和实际应用进行了全面介绍，旨在帮助读者更好地了解和应用这一技术，并在实际工程中取得更好的效果。

文章的篇幅可能不足3000字，需要根据实际情况继续扩展内容。

IGBT栅极驱动的参数要求和驱动条件

驱动电路的基本性能1.概述IGBT器件的发射极和栅极之间是绝缘的二氧化硅结构，直流电不能通过，因而低频的静态驱动功率接近于零。

但是栅极和发射极之间构成了一个栅极电容CGs，因而在高频率的交替导通和关断时需要一定的动态驱动功率。

小功率IGBT的CGs一般在10~l00pF 之内，对于大功率的绝缘栅功率器件，由于栅极电容CGs较大，在1~l00pF，甚至更大，因而需要较大的动态驱动功率。

IGBT栅极电压可由不同的驱动电路产生，栅极驱动电路设计的优劣直接关系到由IGBT构成的系统长期运行可靠性。

正向栅极电压的值应该足够令IGBT产生完全饱和，并使通态损耗减至最小，同时也应限制短路电流和它所带来的功率应力。

IGBT正栅压VGE越大，导通电阻越低，损耗越小。

但是，如果VGE过大，一旦IGBT过流，会造成内部寄生晶闸管的静态擎柱效应，造成IGBT失效。

相反如果VGE过小，可能会使IGBT的工作点落人线性放大区，最终导致器件的过热损坏。

在任何情况下，开通时的栅极驱动电压，应该在12~20V之间。

当栅极电压为零时，IGBT处于断态。

由于IGBT的关断过程可能会承受很大的dv/dt，伴随关断浪涌电流，干扰栅极关断电压，可能造成器件的误开通。

为了保证IGBT在集电极-发射极电压上出现dv/dt噪声时仍保持关断，必须在栅极上施加一个反向关断偏压，采用反向偏压还可减少关断损耗。

反向偏压应该在-5~-15V之间。

理想的心鄒驱动再路应具有以下基本性能：1)要求驱动电路为IGBT提供一定幅值的正反向栅极电压VGE。

理论上VGE≥VGE(th），IGBT即可导通；当VGE太大时，可能引起栅极电压振荡，损坏栅极。

正向VGE越高，IGBT器件的VGES 越低，越有利于降低器件的通态损耗。

但也会使IGBT承受短路电流的时间变短，并使续流二极管反向恢复过电压增大。

因此正偏压要适当，一般不允许VGE超过+-20V。

关断IGBT时，必须为IGBT 器件提供-5~-15V的反向VGE，以便尽快抽取IGBT器件内部的存储电荷，缩短关断时间，提高IGBT的耐压和抗干扰能力。

IGBT的驱动特性及功率损耗计算

IGBT的驱动特性及功率损耗计算作者：海飞乐技术时间：2017-05-17 15:361.IGBT的驱动特性1.1驱动特性的主要影响因素IGBT的驱动条件与IGBT的特性密切相关。

设计栅极驱动电路时，应特别注意开通特性、负载短路能力和dv/dt引起的误触发等问题。

栅极电压Uge增加(应注意Uge过高而损坏IGBT)，则通态电压下降(Eon也下降)，如图1所示(此处以200 A lGBT为例)。

由图中可看出，若Ugc固定不变时，导通电压将随集电极电流增大而增高。

如图1a，电流容量将随结温升高而减少(NPT工艺正温度特性的体现)如图1b所示。

图1 栅极电压Uge与Uce和Tvj的关系栅极电压Uge直接影响IGBT的可靠运行，栅极电压增高时有利于减小IGBT的开通损耗和导通损耗，但同时将使lGBT能承受的短路时间变短(10 µs以下)，使续流二极管反向恢复过电压增大，所以务必控制好栅极电压的变化范围，一般Vge可选择在-10~+15 V之间，关断电压-10V，开通电压+15V。

开关时Uge与lg的关系曲线见图2a和图2b所示。

图2 开关时Uge与Ig的关系曲线栅极电阻Rg增加，将使IGBT的开通与关断时间增加，使开通与关断能耗均增加，但同时，可以使续流二极管的反恢复过电压减小，同时减少EMI的影响。

而门极电阻减少，则又使di/dt增大，可能引发IGBT误导通，但是，当Rg减少时，可以使得IGBT关断时由du/dt所带来误触发的可能性减小，同时也可以提高IGBT承受短路能量的能力，所以Rg 大小各有好坏，客户可根据自己设计特点选择。

图3为Rg大小对开关特性的影响，损耗关系请参照图4所示。

图3Rg大小对开关特性的影响(di/dt大小不同)图4 门极电阻Rg与Eon/Eoff由上述可得IGBT的特性随门极驱动条件的变化而变化，就象双极型晶体管的开关特性和安全工作区随基板驱动而变化一样。

但是lGBT所有特性难以同时最佳化，根据不同应用，在参数设定时进行评估，找到最佳折冲点。

高压栅极驱动器自举电路设计

自举式电路具有简单和低成本的优点，但是，它也有一些局限。
占空比和导通时间受限于自举电容 CBOOT，刷新电荷所需时间的限制。
这个电路最大的难点在于：当开关器件关断时，其源极的负电压会使负载电流突然流过续流二极管，如图 3 所示。
该负电压会给栅极驱动电路的输出端造成麻烦，因为它直接影响驱动电路或 PWM 控制集成电路的源极 VS 引脚，可能会明显地将某些内部电路下拉到地以下，如图 4 所示。另外一个问题是，该负电压的转换可能会使自举电容处于过压状态。
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使用说明书
2.4 VS 引脚产生负电压的原因
如图 5 所示，低端续流二极管的前向偏置是已知的将 VS 下低到 COM （地）以下的原因之一。
主要问题出现在整流换向期间，仅仅在续流二极管开始箝压之前。
在这种情况下，电感 LS1 和 LS2 会将 VS 压低到 COM 以下，甚至超过如上所述的位置或正常稳态。
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图 6. 关断期间的波形
© 2008 飞兆半导体 Rev. 1.0.0 • 6/8/09
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AN-6076
2.5 VS 引脚电压下冲的影响
如果电压下冲幅度超过规定的绝对最大额定值，栅极驱动集成电路受到损害，或者栅极驱动集成电路暂时锁存现态。
图 7 显示高端输出信号没有随输入信号而改变但发生闭锁现象，此时，半桥电路中的外部主高端和低端开关处于短路状态。
使用说明书
2.7 寄生电感效应
负电压的振幅是：
VS − COM = −(VRBOOT + VFDBOOT ) − (LS1 + LS2 )di dt
(1)
为了减小流过寄生电感的电流随时间变化曲线的斜度，要使等式 1 中的导数项最小。

600v单片集成ipm高压侧栅极驱动电路设计

600v单片集成ipm高压侧栅极驱动电路设计
设计一个600V单片集成IPM（智能功率模块）高压侧栅极驱动电路需要考虑到多个因素，包括电压等级、驱动能力、隔离要求、电磁兼容性等。

以下是一个基本的设计步骤和考虑因素：
1. 电压等级和安全裕量：考虑到600V的电压等级，设计时应留有足够的
安全裕量。

通常，实际应用中的电压可能高于或低于标称值，因此设计时应考虑这些极端情况。

2. 驱动能力：栅极驱动电路需要能够提供足够的电流来驱动IPM的功率开关。

这需要根据具体的IPM规格来确定。

3. 隔离要求：在高压应用中，隔离是关键。

需要考虑使用光耦、磁耦或者
其他隔离技术来确保电路的安全运行。

4. 电磁兼容性（EMC）：设计时需要考虑到EMC问题，如减小噪声、防
止电磁干扰等。

这可能涉及到滤波、屏蔽等措施。

5. 集成单片设计：考虑到单片集成的要求，应选择合适的芯片工艺和封装
形式。

同时，电路设计应尽量简洁高效，以减小芯片面积和成本。

6. 可靠性：在设计时应考虑采用一些可靠性措施，如降额设计、热设计等，以增强电路的稳定性。

7. 保护功能：考虑加入过流保护、过压保护、欠压保护等功能，以防止电
路在异常情况下受损。

8. 测试与验证：在设计完成后，需要进行充分的测试和验证，以确保电路的功能和性能满足要求。

具体设计时，还需要根据具体的IPM规格书和实际应用需求来进行调整。

如果需要更详细的设计指导或者具体电路图，建议寻求专业电子工程师的帮助。

应用栅极电荷设计MOSFET IGBT驱动电路

应用栅极电荷设计MOSFET、IGBT驱动电路1、MOSFET、IGBT的栅极输入特性那些对MOSFET、IGBT的栅极输入特性不太熟悉的工程师经常通过data sheet 上提供的栅极与源极间(Ciss)、栅极与漏极间电容（Crss）来设计驱动电路的参数。

然而仅通过这两个数据设计驱动电路是远远不够的。

虽然Ciss是一个很重要的参数，但是在实际应用当中Crss要比所给的数值大的多而且很难掌握因为它随电压并不成线性变化，虽然Ciss也受电压的影响但程度要小。

Crss 的影响类似于在真空放大管发现的现象即：Miller 效应。

在真空管里面两个极板之间（输出于输入之间）由于极间电容的影响存在一个反馈回路,这个回路将会抬高器件的输入条件进而导致动态时的极间电容要比静态时电容大的多。

这个现象最初是由Miller先生发现的。

在高频时Crss的作用不可忽视并且此时与DS极电压成一个函数关系。

克服Miller 效应没什么直接了当的方法及时针对真空管也是这样，而对MOSFET来讲就更难。

虽然在静态时Crss 要比Ciss小的多，但动态时Crss的值可能会是Ciss的20倍，因此在开通时Crss要比Ciss需要更多的充电电荷。

为了给工程师们提供一种实用有效的栅极驱动的设计方法，IR公司给他们的IGBT 、MOSFET产品加了一个“栅极电荷”的参数。

工程师们可以用这个参数计算栅极驱动所需要的电流。

栅极电荷是这样定义的：控制管子导通程度所需要的电荷。

2、测试电路图1典型的用来测试栅极电荷的电路如图1所示。

在此电路中有一个固定电流通过0.1uF的电容C1和一个整流二极管D1给所测试器件（DUT）栅极充电，在这个测试装置中消耗在栅极上的电荷与加在DS极间的电压和充电的恒定电流相关。

图2是我们在示波器上所看到Vgs的测试波形（横坐标是电量，纵坐标是栅极电压）。

由于充电电流是恒定的，所以每一阶段的时间长短就表明了所需电荷的多少。

负载波动下IGBT损坏分析及驱动电路优化设计

负载波动下IGBT损坏分析及驱动电路优化设计摘要：本文分析了四种常见变频器的运行参数，并从维修的层面分析了这些变频器的可靠性。

得出了一个结论就是：只有更可靠的变频器驱动电路才可以有效地将输出级与控制级隔离，并且有效地吸收来自门的不同报警信号。

随着电机负载的波动，IGBT栅极中的浪涌电压产生了一个波动的电压信号，导致IGBT在应该关闭的时候跳闸，导致上下桥IGBT的拉伤和IGBT的损坏。

对此，提出了优化的 IGBT 驱动电路的结构，并在使用中证明，该驱动电路不仅结构系统简单、还具有运行可靠等特点。

关键词：IGBT; 驱动电路; 可靠性; 振荡电压引言：IGBT电源模块的损坏是一种比较常见的故障诊断，一般是由很多种因素造成的。

比如：输出负载短路；外部电源电压过高；负载过大；大电流持续工作；负载波动引起浪涌电流过大；冷却风扇的性能不好；造成部件温度过高；进而引起性能变差、参数改变甚至部件烧坏等。

由冷却风扇不良引起的IGBT损坏可以通过加强变频器的维护来防止；由负载短路和电流过长引起的变频器损坏是不正确的，因为变频器有一个特殊的电路来施加保护，如果这个电路工作正常，除非电路设计不合理，否则变频器不会因这些原因而损坏。

经过分析，笔者认为，当负载振荡时，会引起IGBT栅极的电压波动，如果振荡幅度大，将使上下桥IGBT产生应变导致IGBT损坏。

虽然克服这类振荡通常采用在IGBT关断时向栅极加一个反向电压来减小振荡影响，但是若负载振荡达到较大程度, IGBT仍有可能受到损伤。

通过对IGBT栅极振荡机制进行深入剖析，这里提出了一个可靠的控制电路方案，具有良好的实际应用前景。

一、IGBT的概述及特性IGBT（绝缘栅双极晶体管）是一种由MOSFET（绝缘栅场效应管）和BJT（双极结晶体管）组成的复合半导体器件。

虽然IGBT有电流消耗的缺点，但它同时具有低MOSFET驱动电流和高BJT电流的优点，被广泛用于高电压、大电流和高速开关环境中。

高压栅极驱动ic自举电路的设计与应用指南

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文档下载后可定制修改，请根据实际需要进行调整和使用，谢谢!本店铺为大家提供各种类型的实用资料，如教育随笔、日记赏析、句子摘抄、古诗大全、经典美文、话题作文、工作总结、词语解析、文案摘录、其他资料等等，想了解不同资料格式和写法，敬请关注!Download tips: This document is carefully compiled by this editor. I hope that after you download it, it can help you solve practical problems. The document can be customized and modified after downloading, please adjust and use it according to actual needs, thank you! In addition, this shop provides you with various types of practical materials, such as educational essays, diary appreciation, sentence excerpts, ancient poems, classic articles, topic composition, work summary, word parsing, copy excerpts, other materials and so on, want to know different data formats and writing methods, please pay attention!高压栅极驱动IC自举电路的设计与应用指南在电子设备中，高压栅极驱动IC自举电路是一项关键技术。

MOS驱动电路设计

高速MOS驱动电路设计和应用指南简介MOSFET是Metal Oxide Semiconductor Field Effect Transistor的首字母缩写，它在电子工业高频、高效率开关应用中是一种重要的元件。

或许人们会感到不可思议，但是FET是在1930年，大约比双极晶体管早20年被发明出来。

第一个信号电平FET晶体管制成于二十世纪60年代末期，而功率MOSFET是在二十世纪80年代开始被运用的。

如今,成千上万的MOSFET晶体管集成在现代电子元件,从微型的到“离散”功率晶体管。

本课题的研究重点是在各种开关模型功率转换应用中栅极驱动对功率MOSFET 的要求。

场效应晶体管技术双极晶体管和场效应晶体管有着相同的工作原理。

从根本上说,，两种类型晶体管均是电荷控制元件，即它们的输出电流和控制极半导体内的电荷量成比例。

当这些器件被用作开关时，两者必须和低阻抗源极的拉电流和灌电流分开，用以为控制极电荷提供快速的注入和释放。

从这点看，MOS-FET在不断的开关，当速度可以和双极晶体管相比拟时，它被驱动的将十分的‘激烈’。

理论上讲，双极晶体管和MOSFET的开关速度是基本相同的，这取决与载流子穿过半导体所需的时间。

在功率器件的典型值为20 ~ 200皮秒，但这个时间和器件的尺寸大小有关。

与双极结型晶体管相比，MOSFET在数字技术应用和功率应用上的普及和发展得益于它的两个优点。

优点之一就是在高频率开关应用中MOSFET使用比较方便。

MOSFET更加容易被驱动，这是因为它的控制极和电流传导区是隔离开的，因此不需要一个持续的电流来控制。

一旦MOSFET导通后，它的驱动电流几乎为0。

另外，在MOSFET中，控制电荷的积累和存留时间也大大的减小了。

这基本解决了设计中导通电压降（和多余的控制电荷成反比）和关断时间之间的矛盾。

因此，MOSFET技术以其更加简单的、高效的驱动电路使它比晶体管设备具有更大的经济效益。

此外，有必要突出强调下，尤其是在电源应用上，MOSFET本身具有阻抗特性。

AN-6076高压栅极驱动 IC 自举电路的设计与应用指南

VCC
DBOOT
VDC INPUT
IN VB CBOOT Q1 B RGATE LS1 GND VS C LS2
GND
HVIC
VDD
RBOOT DBOOT
HO
A
CDRV
iLOAD C iFree COUT
VB
RG1
VOUT
- VS
DHO
CBOOT Ls1
Q1 High Side OFF
VDC
t -VS
Freewheeling
VB
UVLO PULSE GENERATOR Shoot-through current compensated gate driver
IN
NOISE CANCELLER
R S
R Q
HO
VS
图 1. 高端驱动集成电路的电平转换器
2.2 自举式驱动电路工作原理
自举式电路在高电压栅极驱动电路中是很有用的，其工作原理如下。当 VS 降低到 IC 电源电压 VDD 或下拉至地时（低端开关导通，高端开关关断），电源 VDD 通过自举电阻， RBOOT，和自举二极管， DBOOT，对自举电容 CBOOT，进行充电，如图 2 所示。当 VS 被高端开关上拉到一个较高电压时，由 VBS 对该自举电容充电，此时， VBS 电源浮动，自举二极管处于反向偏置，轨电压（低端开关关断，高端开关导通）和 IC 电源电压 VDD，被隔离开。
DC SUPPLY
2.4 VS 引脚产生负电压的原因
如图 5 所示，低端续流二极管的前向偏置是已知的将 VS 下低到 COM( 地 ) 以下的原因之一。主要问题出现在整流器换向期间，仅仅在续流二极管开始箝压之前。在这种情况下，电感 LS1 和 LS2 会将 VS 压低到 COM 以下，甚至如上所述的位置或正常稳态。该负电压的放大倍数正比于寄生电感和开关器件的关断速度， di/dt ；它由栅极驱动电阻， RGATE 和开关器件的输入电容， Ciss 决定。 Cgs 与 Cgd 的和，称为密勒电容。

高速MOSFET栅极驱动电路的设计与应用指南

高速MOSFEMOSFET T栅极驱动电路的设计与应用指南摘要本文将展示一个用来设计高速开关应用所需的高性能栅极驱动电路的系统性方案。

它综合了各方面的信息，可一次性解决一些最常见的设计问题。

因此，各个层面的电力电子工程师都值得一读。

文中分析了一些最流行的电路方案及其性能，包括寄生元件、瞬间和极端工作条件的影响。

首先，文章对MOSFET技术和开关操作进行了大致讨论，从简单问题逐渐转向复杂问题，并详细讲述了低端和高端栅极驱动电路以及交流耦合和变压器隔离式方案的设计程序。

另外，文章还专门用一个章节的内容来讨论同步整流器应用中MOSFET的栅极驱动要求。

最后，本文还提供了多个分步骤的设计案例。

简介MOSFET，全称为金属氧化物半导体场效应晶体管，是电子产品领域各种高频高效开关应用的关键元器件。

FET技术发明于1930年，比双极晶体管还要早大约20年，这一点令人感到意外。

最早的信号级FET晶体管出现在20世纪50年代末，而功率MOSFET则是在70年代中期问世的。

如今，数百万的MOSFET 晶体管被集成到了各种电子元器件中，从微控制器到“离散式”功率晶体管。

本话题的重点在于各种开关模式电源转换应用中功率MOSFET的栅极驱动要求。

Design And Application GuideFor High Speed MOSFET Gate Drive CircuitsBy Laszlo BaloghABSTRACTThe main purpose of this paper is to demonstrate a systematic approach to design high performance gate drive circuits for high speed switching applications. It is an informative collection of topics offering a “one-stop-shopping” to solve the most common design challenges. Thus it should be of interest to power electronics engineers at all levels of experience.The most popular circuit solutions and their performance are analyzed, including the effect of parasitic components, transient and extreme operating conditions. The discussion builds from simple to more complex problems starting with an overview of MOSFET technology and switching operation. Design procedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolated solutions are described in great details. A special chapter deals with the gate drive requirements of the MOSFETs in synchronous rectifier applications.Several, step-by-step numerical design examples complement the paper.INTRODUCTIONMOSFET – is an acronym for Metal Oxide Semiconductor Field Effect Transistor and it is the key component in high frequency, high efficiency switching applications across the electronics industry. It might be surprising, but FET technology was invented in 1930, some 20 years before the bipolar transistor. The first signal level FET transistors were built in the late 1950’s while power MOSFETs have been available from the mid 70’s. Today, millions of MOSFET transistors are integrated in modern electronic components, from microprocessors, through “discrete” power transistors.The focus of this topic is the gate drive requirements of the power MOSFET in various switch mode power conversion applications. MOSFET TECHNOLOGYThe bipolar and the MOSFET transistors exploit the same operating principle. Fundamentally, both type of transistors are charge controlled devices which means that their output current is proportional to the charge established in the semiconductor by the control electrode. When these devices are used as switches, both must be driven from a low impedance source capable of sourcing and sinking sufficient current to provide for fast insertion and extraction of the controlling charge. From this point of view, the MOSFETs have to be driven just as “hard” during turn-on and turn-off as a bipolar transistor to achieve comparable switching speeds. Theoretically, the switching speeds of the bipolar and MOSFET devices are close to identical, determined by the time required for the charge carriers to travel across the semiconductor region. Typical values in power devices are approximately 20 to 200 picoseconds depending on the size of the device. The popularity and proliferation of MOSFET technology for digital and power applications is driven by two of their major advantages over the bipolar junction transistors. One of these benefits is the ease of use of the MOSFET devices in high frequency switching applications. The MOSFET transistors are simpler to drive because their control electrode is isolated from the current conducting silicon, therefore a continuous ON current is not required. Once the MOSFET transistors are turned-on, their drive current is practically zero. Also, the controlling charge and accordingly the storage time in the MOSFET transistors is greatly reduced. This basically1eliminates the design trade-off between on state voltage drop – which is inversely proportional to excess control charge – and turn-off time. As a result, MOSFET technology promises to use much simpler and more efficient drive circuits with significant economic benefits compared to bipolar devices.Furthermore, it is important to highlight especially for power applications, that MOSFETs have a resistive nature. The voltage drop across the drain source terminals of a MOSFET is a linear function of the current flowing in the semiconductor. This linear relationship is characterized by the R DS(on) of the MOSFET and known as the on-resistance. On-resistance is constant for a given gate-to-source voltage and temperature of the device. As opposed to the -2.2mV/°C temperature coefficient of a p-n junction, the MOSFETs exhibit a positive temperature coefficient of approximately 0.7%/°C to 1%/°C. This positive temperature coefficient of the MOSFET makes it an ideal candidate for parallel operation in higher power applications where using a single device would not be practical or possible. Due to the positive TC of the channel resistance, parallel connected MOSFETs tend to share the current evenly among themselves. This current sharing works automatically in MOSFETs since the positive TC acts as a slow negative feedback system. The device carrying a higher current will heat up more – don’t forget that the drain to source voltages are equal – and the higher temperature will increase its R DS(on) value. The increasing resistance will cause the current to decrease, therefore the temperature to drop. Eventually, an equilibrium is reached where the parallel connected devices carry similar current levels. Initial tolerance in R DS(on) values and different junction to ambient thermal resistances can cause significant – up to 30% – error in current distribution.Device typesAlmost all manufacturers have got their unique twist on how to manufacture the best power MOSFETs, but all of these devices on the market can be categorized into three basic device types. These are illustrated in Figure 1.Figure 1. Power MOSFET device types Double-diffused MOS transistors were introduced in the 1970’s for power applications and evolved continuously during the years. Using polycrystalline silicon gate structures and self-aligning processes, higher density integration and rapid reduction in capacitances became possible. The next significant advancement was offered by the V-groove or trench technology to further increase cell density in power MOSFET devices. The better performance and denser integration don’t come free however, as trench MOS devices are more difficult to manufacture.The third device type to be mentioned here is the lateral power MOSFETs. This device type is constrained in voltage and current rating due to its inefficient utilization of the chip geometry. Nevertheless, they can provide significant benefits in low voltage applications, like in microprocessor power supplies or as synchronous rectifiers in isolated converters.2The lateral power MOSFETs have significantly lower capacitances, therefore they can switch much faster and they require much less gate drive power.MOSFET ModelsThere are numerous models available to illustrate how the MOSFET works, nevertheless finding the right representation might be difficult. Mostof the MOSFET manufacturers provide Spice and/or Saber models for their devices, but these models say very little about the application traps designers have to face in practice. They provide even fewer clues how to solve the most common design challenges.A really useful MOSFET model which would describe all important properties of the device from an application point of view would be very complicated. On the other hand, very simple and meaningful models can be derived of the MOSFET transistor if we limit the applicabilityof the model to certain problem areas.The first model in Figure 2 is based on the actual structure of the MOSFET device and can be used mainly for DC analysis. The MOSFET symbol in Figure 2a represents the channel resistance and the JFET corresponds to the resistance of the epitaxial layer. The length, thus the resistance of the epi layer is a function of the voltage rating of the device as high voltage MOSFETs require thicker epitaxial layer.Figure 2b can be used very effectively to model the dv/dt induced breakdown characteristic of a MOSFET. It shows both main breakdown mechanisms, namely the dv/dt induced turn-on of the parasitic bipolar transistor - present in all power MOSFETs - and the dv/dt induced turn-onof the channel as a function of the gate terminating impedance. Modern power MOSFETs are practically immune to dv/dt triggering of the parasitic npn transistor due to manufacturing improvements to reduce the resistance between the base and emitter regions.It must be mentioned also that the parasitic bipolar transistor plays another important role. Its base – collector junction is the famous body diode of the MOSFET.Figure 2. Power MOSFET models34Figure 2c is the switching model of the MOSFET. The most important parasitic components influencing switching performance are shown in this model. Their respective roles will be discussed in the next chapter which is dedicated to the switching procedure of the device.MOSFET Critical ParametersWhen switch mode operation of the MOSFET is considered, the goal is to switch between the lowest and highest resistance states of the device in the shortest possible time. Since the practical switching times of the MOSFETs (~10ns to 60ns) is at least two to three orders of magnitude longer than the theoretical switching time (~50ps to 200ps), it seems important to understand the discrepancy. Referring back to the MOSFET models in Figure 2, note that all models include three capacitors connected between the three terminals of the device. Ultimately, the switching performance of the MOSFET transistor is determined by how quickly the voltages can be changed across these capacitors.Therefore, in high speed switching applications, the most important parameters are the parasitic capacitances of the device. Two of these capacitors, the C GS and C GD capacitors correspond to the actual geometry of the device while the C DS capacitor is the capacitance of the base collector diode of the parasitic bipolar transistor (body diode).The C GS capacitor is formed by the overlap of the source and channel region by the gate electrode. Its value is defined by the actual geometry of the regions and stays constant (linear) under different operating conditions.The C GD capacitor is the result of two effects. Part of it is the overlap of the JFET region and the gate electrode in addition to the capacitance of the depletion region which is non-linear. The equivalent C GD capacitance is a function of the drain source voltage of the device approximated by the following formula:DS1GD,0GD V K 1C C ⋅+≈The C DS capacitor is also non-linear since it is the junction capacitance of the body diode. Its voltage dependence can be described as:DS 2DS,0DS V K C C ⋅≈Unfortunately, non of the above mentioned capacitance values are defined directly in the transistor data sheets. Their values are given indirectly by the C ISS , C RSS , and C OSS capacitor values and must be calculated as: RSSOSS DS RSS ISS GS RSSGD C C C C C C C C −=−== Further complication is caused by the C GD capacitor in switching applications because it is placed in the feedback path between the input and output of the device. Accordingly, its effective value in switching applications can be much larger depending on the drain source voltage of the MOSFET. This phenomenon is called the “Miller” effect and it can be expressed as:()GD L fs eqv GD,C R g 1C ⋅⋅+=Since the C GD and C DS capacitors are voltage dependent, the data sheet numbers are valid only at the test conditions listed. The relevant average capacitances for a certain application have to be calculated based on the required charge to establish the actual voltage change across the capacitors. For most power MOSFETs the following approximations can be useful: offDS,spec DS,spec OSS,ave OSS,off DS,spec DS,spec RSS,ave GD,V V C 2C V V C 2C ⋅⋅=⋅⋅=The next important parameter to mention is the gate mesh resistance, R G,I . This parasitic resistance describes the resistance associated by the gate signal distribution within the device. Its importance is very significant in high speed switching applications because it is in between the driver and the input capacitor of the device, directly impeding the switching times and the5dv/dt immunity of the MOSFET. This effect is recognized in the industry, where real high speed devices like RF MOSFET transistors use metal gate electrodes instead of the higher resistance polysilicon gate mesh for gate signal distribution. The R G,I resistance is not specified in the data sheets, but in certain applications it can be a very important characteristic of the device. In the back of this paper, Appendix A4 shows a typical measurement setup to determine the internal gate resistor value with an impedance bridge.Obviously, the gate threshold voltage is also a critical characteristic. It is important to note that the data sheet V TH value is defined at 25°C and at a very low current, typically at 250μA. Therefore, it is not equal to the Miller plateau region of the commonly known gate switching waveform. Another rarely mentioned fact about V TH is its approximately –7mV/°C temperature coefficient. It has particular significance in gate drive circuits designed for logic level MOSFET where V TH is already low under the usual test conditions. Since MOSFETs usually operate at elevated temperatures, proper gate drive design must account for the lower V TH when turn-off time, and dv/dt immunity is calculated as shown in Appendix A and F.The transconductance of the MOSFET is its small signal gain in the linear region of its operation. It is important to point out that every time the MOSFET is turned-on or turned-off, it must go through its linear operating mode where the current is determined by the gate-to-source voltage. The transconductance, g fs , is the small signal relationship between drain current and gate-to-source voltage:GSD fs dV dI g =Accordingly, the maximum current of the MOSFET in the linear region is given by: ()fs th GS D g V V I ⋅−=Rearranging this equation for V GS yields the approximate value of the Miller plateau as a function of the drain current.fs D th Miller GS,g IV V +=Other important parameters like the source inductance (L S ) and drain inductance (L D ) exhibit significant restrictions in switching performance. Typical L S and L D values are listed in the data sheets, and they are mainly dependant on the package type of the transistor. Their effects can be investigated together with the external parasitic components usually associated with layout and with accompanying external circuit elements like leakage inductance, a current sense resistor, etc.For completeness, the external series gate resistor and the MOSFET driver’s output impedance must be mentioned as determining factors in high performance gate drive designs as they have a profound effect on switching speeds and consequently on switching losses.SWITCHING APPLICATIONSNow, that all the players are identified, let’s investigate the actual switching behavior of the MOSFET transistors. To gain a better understanding of the fundamental procedure, the parasitic inductances of the circuit will be neglected. Later their respective effects on the basic operation will be analyzed individually. Furthermore, the following descriptions relate to clamped inductive switching because most MOSFET transistors and high speed gate drive circuits used in switch mode power supplies work in that operating mode.Figure 3. Simplified clamped inductive switchingmodelThe simplest model of clamped inductive switching is shown in Figure 3, where the DC current source represents the inductor. Its current can be considered constant during the short switching interval. The diode provides a path for the current during the off time of the MOSFET and clamps the drain terminal of the device to the output voltage symbolized by the battery.Turn-On procedureThe turn-on event of the MOSFET transistor can be divided into four intervals as depicted in Figure 4.Figure 4. MOSFET turn-on time intervalsIn the first step the input capacitance of the device is charged from 0V to V TH. During this interval most of the gate current is charging the C GS capacitor. A small current is flowing through the C GD capacitor too. As the voltage increases at the gate terminal and the C GD capacitor’s voltage has to be slightly reduced. This period is called the turn-on delay, because both the drain current and the drain voltage of the device remain unchanged.Once the gate is charged to the threshold level, the MOSFET is ready to carry current. In the second interval the gate is rising from V TH to the Miller plateau level, V GS,Miller. This is the linear operation of the device when current is proportional to the gate voltage. On the gate side, current is flowing into the C GS and C GD capacitors just like in the first time interval and the V GS voltage is increasing. On the output side of the device, the drain current is increasing, while the drain-to-source voltage stays at the previous level (V DS,OFF). This can be understood looking at the schematic in Figure 3. Until all the current is transferred into the MOSFET and the diode is turned-off completely to be able to block reverse voltage across its pn junction, the drain voltage must stay at the output voltage level. Entering into the third period of the turn-on procedure the gate is already charged to the sufficient voltage (V GS,Miller) to carry the entire load current and the rectifier diode is turned off. That now allows the drain voltage to fall. While the drain voltage falls across the device, the gate-to-source voltage stays steady. This is the Miller plateau region in the gate voltage waveform. All the gate current available from the driver is diverted to discharge the C GD capacitor to facilitate the rapid voltage change across the drain-to-source terminals. The drain current of the device stays constant since it is now limited by the external circuitry, i.e. the DC current source.The last step of the turn-on is to fully enhance the conducting channel of the MOSFET by applying a higher gate drive voltage. The final amplitude of V GS determines the ultimate on-resistance of the device during its on-time. Therefore, in this fourth interval, V GS is increased from V GS,Miller to its final value, V DRV. This is accomplished by charging the C GS and C GD capacitors, thus gate current is now split between the two components. While these capacitors are being charged, the drain current is still constant, and the drain-to-source voltage is slightly decreasing as the on-resistance of the device is being reduced.6Turn-Off procedureThe description of the turn-off procedure for the MOSFET transistor is basically back tracking the turn-on steps from the previous section. Start with V GS being equal to V DRV and the current in the device is the full load current represented by I DC in Figure 3. The drain-to-source voltage is being defined by I DC and the R DS(on) of the MOSFET. The four turn-off steps are shown in Figure 5. for completeness.Figure 5. MOSFET turn-off time intervals The first time interval is the turn-off delay which is required to discharge the C ISS capacitance from its initial value to the Miller plateau level. During this time the gate current is supplied by the C ISS capacitor itself and it is flowing through the C GS and C GD capacitors of the MOSFET. The drain voltage of the device is slightly increasing as the overdrive voltage is diminishing. The current in the drain is unchanged.In the second period, the drain-to-source voltage of the MOSFET rises from I D⋅R DS(on) to the final V DS(off) level, where it is clamped to the output voltage by the rectifier diode according to the simplified schematic of Figure 3. During this time period – which corresponds to the Miller plateau in the gate voltage waveform - the gate current is strictly the charging current of the C GDcapacitor because the gate-to-source voltage is constant. This current is provided by the bypass capacitor of the power stage and it is subtracted from the drain current. The total drain current still equals the load current, i.e. the inductor current represented by the DC current source in Figure 3.The beginning of the third time interval is signified by the turn-on of the diode, thus providing an alternative route to the load current.The gate voltage resumes falling from V GS,Miller to V TH. The majority of the gate current is coming out of the C GS capacitor, because the C GDcapacitor is virtually fully charged from the previous time interval. The MOSFET is in linear operation and the declining gate-to-source voltage causes the drain current to decrease and reach near zero by the end of this interval.Meanwhile the drain voltage is steady at V DS(off)due to the forward biased rectifier diode.The last step of the turn-off procedure is to fully discharge the input capacitors of the device. V GSis further reduced until it reaches 0V. The bigger portion of the gate current, similarly to the third turn-off time interval, supplied by the C GScapacitor. The drain current and the drain voltage in the device are unchanged.Summarizing the results, it can be concluded that the MOSFET transistor can be switched between its highest and lowest impedance states (either turn-on or turn-off) in four time intervals. The lengths of all four time intervals are a function of the parasitic capacitance values, the required voltage change across them and the available gate drive current. This emphasizes the importance of the proper component selection and optimum gate drive design for high speed, high frequency switching applications.7Characteristic numbers for turn-on, turn-off delays, rise and fall times of the MOSFET switching waveforms are listed in the transistor data sheets. Unfortunately, these numbers correspond to the specific test conditions and to resistive load, making the comparison of different manufacturers’ products difficult. Also, switching performance in practical applications with clamped inductive load is significantly different from the numbers given in the data sheets.Power lossesThe switching action in the MOSFET transistorin power applications will result in some unavoidable losses, which can be divided into two categories.The simpler of the two loss mechanisms is the gate drive loss of the device. As described before, turning-on or off the MOSFET involves chargingor discharging the C ISS capacitor. When the voltage across a capacitor is changing, a certain amount of charge has to be transferred. The amount of charge required to change the gate voltage between 0V and the actual gate drive voltage V DRV, is characterized by the typical gate charge vs. gate-to-source voltage curve in the MOSFET datasheet. An example is shown in Figure 6.Figure 6. Typical gate charge vs. gate-to-sourcevoltage This graph gives a relatively accurate worst case estimate of the gate charge as a function of the gate drive voltage. The parameter used to generate the individual curves is the drain-to-source off state voltage of the device. V DS(off) influences the Miller charge – the area below the flat portion of the curves – thus also, the total gate charge required in a switching cycle. Once the total gate charge is obtained from Figure 6, the gate charge losses can be calculated as:DRVGDRVGATEfQVP⋅⋅=where V DRV is the amplitude of the gate drive waveform and f DRV is the gate drive frequency – which is in most cases equal to the switching frequency. It is interesting to notice that the Q G⋅f DRV term in the previous equation gives the average bias current required to drive the gate. The power lost to drive the gate of the MOSFET transistor is dissipated in the gate drive circuitry. Referring back to Figures 4 and 5, the dissipating components can be identified as the combination of the series ohmic impedances in the gate drive path. In every switching cycle the required gate charge has to pass through the driver output impedances, the external gate resistor, and the internal gate mesh resistance. As it turns out, the power dissipation is independent of how quickly the charge is delivered through the resistors. Using the resistor designators from Figures 4 and 5, the driver power dissipation can be expressed as:OFFDRV,ONDRV,DRVIG,GATELODRVGDRVLOOFFDRV,IG,GATEHIDRVGDRVHIONDRV,PPPRRRfQVR21PRRRfQVR21P+=++⋅⋅⋅⋅=++⋅⋅⋅⋅=In the above equations, the gate drive circuit is represented by a resistive output impedance and this assumption is valid for MOS based gate drivers. When bipolar transistors are utilized in the gate drive circuit, the output impedance becomes non-linear and the equations do not yield the correct answers. It is safe to assume that with low value gate resistors (<5Ω) most gate drive losses are dissipated in the driver. If R GATE is sufficiently large to limit I G below the output89current capability of the bipolar driver, the majority of the gate drive power loss is then dissipated in R GATE .In addition to the gate drive power loss, the transistors accrue switching losses in the traditional sense due to high current and high voltage being present in the device simultaneously for a short period. In order to ensure the least amount of switching losses, the duration of this time interval must be minimized. Looking at the turn-on and turn-off procedures of the MOSFET, this condition is limited to intervals 2 and 3 of the switching transitions in both turn-on and turn-off operation. These time intervals correspond to the linear operation of the device when the gate voltage is between V TH and V GS,Miller , causing changes in the current of the device and to the Miller plateau region when the drain voltage goes through its switching transition.This is a very important realization to properly design high speed gate drive circuits. It highlights the fact that the most important characteristic of the gate driver is its source-sink current capability around the Miller plateau voltage level. Peak current capability, which is measured at full V DRV across the driver’s output impedance, has very little relevance to the actual switching performance of the MOSFET. What really determines the switching times of the device is the gate drive current capability when the gate-to-source voltage, i.e. the output of the driver is at ~5V (~2.5V for logic level MOSFETs).A crude estimate of the MOSFET switching losses can be calculated using simplified linear approximations of the gate drive current, drain current and drain voltage waveforms during periods 2 and 3 of the switching transitions. First the gate drive currents must be determined for the second and third time intervals respectively:()G.I GATE HI MillerGS,DRV G3G.IGATE HI TH Miller GS,DRVG2R R R V V I R R R V V 0.5V I ++−=+++⋅−=Assuming that I G2 charges the input capacitor of the device from V TH to V GS,Miller and I G3 is the discharge current of the C RSS capacitor while the drain voltage changes from V DS(off) to 0V, the approximate switching times are given as:G3offDS,RSS G2THMillerGS,ISS I V C t3I V V C t2⋅=−⋅=During t2 the drain voltage is V DS(off) and the current is ramping from 0A to the load current, I L while in t3 time interval the drain voltage is falling from V DS(off) to near 0V. Again, using linear approximations of the waveforms, the power loss components for the respective time intervals can be estimated:Loff DS,Loff DS,I 2V T t3P32I V T t2P2⋅⋅=⋅⋅=where T is the switching period. The total switching loss is the sum of the two loss components, which yields the following simplifed expression:Even though the switching transitions are well understood, calculating the exact switching losses is almost impossible. The reason is the effect of the parasitic inductive components which will significantly alter the current and voltage waveforms, as well as the switching times during the switching procedures. Taking into account the effect of the different source and drain inductances of a real circuit would result in second order differential equations to describe the actual waveforms of the circuit. Since the variables, including gate threshold voltage, MOSFET capacitor values, driver output impedances, etc. have a very wide tolerance, the above described linear approximation seems to be a reasonable enough compromise to estimate switching losses in the MOSFET.Effects of parasitic componentsThe most profound effect on switching performance is exhibited by the source inductance. There are two sources for parasitic source inductance in a typical circuit, the sourceTt3t22I V P L DS(off)SW +⋅⋅=。

高速MOS驱动电路设计和应用指南

高速MOS驱动电路设计和应用指南摘要本篇论文的主要目的是来论证一种为高速开关应用而设计高性能栅极驱动电路的系统研究方法。

它是对“一站买齐”主题信息的收集，用来解决设计中最常见的挑战。

因此，各级的电力电子工程师对它都应该感兴趣。

对最流行电路解决方案和他们的性能进行了分析，这包括寄生部分的影响、瞬态的和极限的工作情况。

整篇文章开始于对MOSFET技术和开关工作的概述，随后进行简单的讨论然后再到复杂问题的分析。

仔细描述了设计过程中关于接地和高边栅极驱动电路、AC耦合和变压器隔离的解决方案。

其中一个章节专门来解决同步整流器应用中栅极驱动对MOSFET的要求。

另外，文章中还有一些一步一步的参数分析设计实例。

简介MOSFET是Metal Oxide Semiconductor Field Effect Transistor的首字母缩写，它在电子工业高频、高效率开关应用中是一种重要的元件。

或许人们会感到不可思议，但是FET是在1930年，大约比双极晶体管早20年被发明出来。

第一个信号电平FET晶体管制成于二十世纪60年代末期，而功率MOSFET是在二十世纪80年代开始被运用的。

如今,成千上万的MOSFET晶体管集成在现代电子元件,从微型的到“离散”功率晶体管。

本课题的研究重点是在各种开关模型功率转换应用中栅极驱动对功率MOSFET 的要求。

场效应晶体管技术双极晶体管和场效应晶体管有着相同的工作原理。

从根本上说,，两种类型晶体管均是电荷控制元件，即它们的输出电流和控制极半导体内的电荷量成比例。

当这些器件被用作开关时，两者必须和低阻抗源极的拉电流和灌电流分开，用以为控制极电荷提供快速的注入和释放。

从这点看，MOS-FET在不断的开关，当速度可以和双极晶体管相比拟时，它被驱动的将十分的‘激烈’。

理论上讲，双极晶体管和MOSFET的开关速度是基本相同的，这取决与载流子穿过半导体所需的时间。

在功率器件的典型值为20 ~ 200皮秒，但这个时间和器件的尺寸大小有关。

栅极驱动电路mos管烧坏原因

栅极驱动电路mos管烧坏原因1.引言1.1 概述栅极驱动电路是一种广泛应用于电子设备中的重要电路组成部分，它主要负责控制MOS管的开关动作。

然而，在实际使用过程中，经常会遇到栅极驱动电路损坏的情况，导致MOS管烧坏。

这给电子设备的正常运行带来了一定的困扰。

本文旨在深入探讨栅极驱动电路导致MOS管烧坏的原因。

通过对这些原因的深入分析，我们可以更好地了解MOS管烧坏的机制，从而采取相应的预防措施。

在本文的正文部分，我们将首先介绍栅极驱动电路的作用，详细解释其在电子设备中的重要性。

随后，我们将逐一探讨导致MOS管烧坏的常见原因，包括过电压、过电流、过温度等因素的影响。

我们将以具体的实例和案例进行说明，以便读者更好地理解这些原因对MOS管烧坏的影响。

在结论部分，我们将对全文进行总结，并从栅极驱动电路和MOS管烧坏原因的角度提供一些建议和启示。

我们将强调预防措施和解决方案的重要性，并提供相应的建议，以帮助读者在实际应用中避免MOS管烧坏的情况发生。

通过本文的撰写和研究，我们希望读者能够更好地理解栅极驱动电路和MOS管烧坏原因之间的关系，从而能够有效地应对和解决相关问题。

最终，我们希望能够为电子设备的稳定运行提供一定的指导和参考。

1.2文章结构文章结构部分主要介绍本文的章节设置和内容安排。

本文共分为引言、正文和结论三个部分。

下面将对每个部分的内容进行详细说明。

1. 引言部分1.1 概述在这一部分，将简要介绍栅极驱动电路mos管烧坏原因的相关背景和重要性。

可以提到MOS管作为电子器件中常用的一种器件，其使用广泛，但在使用过程中往往会出现烧坏现象，影响设备的正常工作。

因此，了解MOS管烧坏的原因以及栅极驱动电路对其影响的重要性就显得尤为重要。

1.2 文章结构在这一部分，将详细介绍本文的章节设置和内容安排，为读者提供全文的框架和脉络。

本文共分为引言、正文和结论三个部分。

在正文部分，我们将首先介绍栅极驱动电路的作用，然后列举MOS管烧坏的常见原因。

IGBT驱动电路设计

IGBT驱动电路设计————————————————————————————————作者：————————————————————————————————日期：一种IGBT驱动电路的设计IGBT的概念是20世纪80年代初期提出的。

IGBT具有复杂的集成结构，它的工作频率可以远高于双极晶体管。

IGBT已经成为功率半导体器件的主流。

在10～100 kHz的中高压大电流的范围内得到广泛应用。

IGBT进一步简化了功率器件的驱动电路和减小驱动功率。

1 IGBT的工作特性。

IGBT的开通和关断是由栅极电压来控制的。

当栅极施以正电压时，MOSFET内形成沟道，并为PNP晶体管提供基极电流，从而使IGBT导通。

此时从N+区注入到N-区的空穴（少子）对N-区进行电导调制，减小Ⅳ区的电阻R dr ，使阻断电压高的IGBT也具有低的通态压降。

当栅极上施以负电压时。

MOSFET内的沟道消失，PNP晶体管的基极电流被切断，IGBT即被关断。

在IGBT导通之后。

若将栅极电压突然降至零，则沟道消失，通过沟道的电子电流为零，使集电极电流有所下降，但由于N-区中注入了大量的电子和空穴对，因而集电极电流不会马上为零，而出现一个拖尾时间。

2 驱动电路的设计2.1 IGBT器件型号选择1）IGBT承受的正反向峰值电压考虑到2-2.5倍的安全系数，可选IGBT的电压为1 200 V。

2）IGBT导通时承受的峰值电流。

额定电流按380 V供电电压、额定功率30 kVA容量算。

选用的IGBT型号为SEMIKRON公司的SKM400GA128D。

2.2 IGBT驱动电路的设计要求对于大功率IGBT，选择驱动电路基于以下的参数要求：器件关断偏置、门极电荷、耐固性和电源情况等。

门极电路的正偏压VGE负偏压-VGE和门极电阻RG的大小，对IGBT的通态压降、开关时间、开关损耗、承受短路能力以及dv／dt电流等参数有不同程度的影响。

门极驱动条件与器件特性的关系见表1。

工程师经验之高压栅极驱动器自举电路设计

工程师经验之高压栅极驱动器自举电路设计本文讲述了一种运用于功率型2. 高速栅极驱动电路1自举栅极驱动技术2自举式驱动电路工作原理S 降低到IC 电源电压VDD 或下拉至地时（低端开关导通，高端开关关断），电源VDD 通过自举电阻，RBOOT，和自举BOOT，对自举电容CBOOT，进行充电，如图2 所示。

当VS 被高端开关上拉到一个较高电压时，由VBS 对该自举电容充电，此时，VBS 电源浮动，自举二极管处于反向偏置，轨电压（低端开关关断，高端开关导通）和IC 电源电压VDD，被隔离开。

3自举式电路的缺点BOOT，刷新电荷所需时间的限制。

S引脚，可能会明显地将某些内部电路下拉到地以下，如图4 所示。

另外一个问题是，该负电压的转换可能会使自举电容处于过压状态。

BOOT，通过自举二极管DBOOT，被电源VDD瞬间充电。

DD 电源以地作为基准，自举电容产生的最大电压等于VDD 加上源极上的负电压振幅。

4VS引脚产生负电压的原因S下低到COM （地）以下的原因之一。

GATE 和开关器件的输入电容，Ciss 决定。

5VS 引脚电压下冲的影响S 电压下冲没有超过规定的绝对最大额定值，栅极驱动IC 不会受到损害。

然而，当VS 处于如图8 所示的下冲状态时，高端输出不会对输入转换作出响应。

在这种情况下，高端栅极驱动电路的电平转换器不会受到工作电压余量不足的影响。

需要注意的是，大多数事实证明高端通常不需要在一个开关动作之后立即改变状态。

6考虑闭锁效应S电压严重不足和由此产生闭锁效应之间的关系。

DD由一个零欧姆电源驱动，通过一个理想二极管连接到VB，如图9 所示。

当大电流流过续流二极管时，由于di/dt 很大，VS电压将低于地电压。

这时，闭锁危险发生了，因为栅极驱动器内部的寄生二极管DBS，最终沿VS 到VB 方向导通，造成下冲电压与VDD叠加，使得自举电容被过度充电，如图10 所示。

DD=15V，VS下冲超过10V，迫使浮动电源电压在25V 以上，二极管DBS有被击穿的危险，进而产生闭锁。

MOS管驱动变压器隔离电路分析和应用

MOS管驱动变压器隔离电路分析和应用今天在研究全桥电路，资料和书上谈到的，大多数基于理想的驱动器（立即充电完成）。

这里一篇幅把MOS管驱动的来龙去脉搞搞清楚。

预计要分几个篇幅：1.MOS管驱动基础和时间功耗计算2.MOS管驱动直连驱动电路分析和应用3.MOS管驱动变压器隔离电路分析和应用4.MOS管网上搜集到的电路学习和分析今天主要分析MOS管驱动变压器隔离电路分析和应用和MOS管驱动基础和时间功耗计算。

参考材料：《Design And Application Guide For High Speed MOSFET Gate Drive Circuits》是一份很好的材料《MOSFET 驱动器与MOSFET 的匹配设计》也可以借鉴。

首先谈一下变压器隔离的MOS管驱动器：如果驱动高压MOS管，我们需要采用变压器驱动的方式和集成的高边开关。

这两个解决方案都有自己的优点和缺点，适合不同的应用。

集成高边驱动器方案很方便，优点是电路板面积较小，缺点是有很大的导通和关断延迟。

变压器耦合解决方案的优点是延迟非常低，可以在很高的压差下工作。

常它需要更多，缺点是需要很多的元件并且对变压器的运行有比较深入的认识。

变压器常见问题和与MOS管驱动相关的问题：变压器有两个绕组，初级绕组和次级绕组实现了隔离，初级和次级的匝数比变化实现了电压缩放，对于我们的设计一般不太需要调整电压，隔离却是我们最注重的。

理想情况下，变压器是不储存能量的（反激“变压器”其实是耦合电感）。

不过实际上变压器还是储存了少量能量在线圈和磁芯的气隙形成的磁场区域，这种能量表现为漏感和磁化电感。

对于功率变压器来说，减少漏感可以减少能量损耗，以提高效率。

MOS管驱动器变压器的平均功率很小，但是在开通和关闭的时候传递了很高的电流，为了减少延迟保持漏感较低仍然是必须的。

法拉第定律规定，变压器绕组的平均功率必须为零。

即使是很小的直流分量可能会剩磁，最终导致磁芯饱和。