EDA数字秒表课程设计

合集下载
  1. 1、下载文档前请自行甄别文档内容的完整性,平台不提供额外的编辑、内容补充、找答案等附加服务。
  2. 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
  3. 3、如文档侵犯您的权益,请联系客服反馈,我们会尽快为您处理(人工客服工作时间:9:00-18:30)。

EDA课程设计实验报告

数字秒表

班级:电1104

姓名:***

学号:********

设计数字秒表

一、实验要求:

1.要求设置启/停开关。当按下启/停开关,将启动秒表开始计时,当再按一下启

/停开关时,将终止计时操作。

2.数字秒表的计时范围是0秒~59分59.99……

3.要求计时精度为0.01s。

4.复位开关可以在任何情况下使用,即便在计时过程中,只要按一下复位开关,

计时器就清零,并做好下次计时的准备。

二、实验分模块源程序及仿真结果:

(一)时积分频模块的VHDL源程序(CB10.VHD)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CB10 IS

PORT(CLK:IN STD_LOGIC;

CO:OUT STD_LOGIC);

END CB10;

ARCHITECTURE ART OF CB10 IS

SIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS(CLK)

BEGIN

IF RISING_EDGE(CLK) THEN

IF COUNT="1001"THEN

COUNT<="0000";

CO<='1';

ELSE

COUNT<=COUNT+1;

CO<='0';

END IF;

END IF;

END PROCESS;

END ART;

CB10仿真波形

(二)控制模块的VHDL源程序(CTRL.VHD)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CTRL IS

PORT(CLR,CLK,SP:IN STD_LOGIC;

EN:OUT STD_LOGIC);

END;

ARCHITECTURE BEHA VE OF CTRL IS

TYPE STATES IS ARRAY(1 DOWNTO 0) OF STD_LOGIC; CONSTANT S0: STATES:="00";

CONSTANT S1: STATES:="01";

CONSTANT S2: STATES:="11";

CONSTANT S3: STATES:="10";

SIGNAL CURRENT_STATE,NEXT_STATE:STATES; BEGIN

COM:PROCESS(SP,CURRENT_STATE,NEXT_STATE) BEGIN

CASE CURRENT_STATE IS

WHEN S0=>EN<='0';

IF SP='1' THEN

NEXT_STATE<=S1;

ELSE

NEXT_STATE<=S0;

END IF;

WHEN S1=>EN<='1';

IF SP='1' THEN

NEXT_STATE<=S1;

ELSE

NEXT_STATE<=S2;

END IF;

WHEN S2=>EN<='1';

IF SP='1' THEN

NEXT_STATE<=S3;

ELSE

NEXT_STATE<=S2;

END IF;

WHEN S3=>EN<='0';

IF SP='1' THEN

NEXT_STATE<=S3;

ELSE

NEXT_STATE<=S0;

END IF;

END CASE;

END PROCESS;

SYNCH:PROCESS(CLR,CLK,SP)

BEGIN

IF CLR='1' THEN

CURRENT_STATE<=S0;

ELSIF CLK'EVENT AND CLK='1' THEN

CURRENT_STATE<=NEXT_STATE;

END IF;

END PROCESS;

END;

CTRL仿真波形

(三)计时模块的VHDL源程序

(1)十进制计数器的VHDL 源程序(CDU10.VDH)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CDU10 IS

PORT(CLK:IN STD_LOGIC;

CLR:IN STD_LOGIC;

EN:IN STD_LOGIC;

CN:OUT STD_LOGIC;

COUNT10:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END CDU10;

ARCHITECTURE ART OF CDU10 IS

SIGNAL SCOUNT10:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

COUNT10<=SCOUNT10;

PROCESS(CLK,CLR,EN)

BEGIN

IF(CLR='1') THEN

SCOUNT10<="0000";CN<='0';

ELSIF RISING_EDGE(CLK) THEN

IF(EN='1') THEN

IF SCOUNT10="1001" THEN

CN<='1';

SCOUNT10<="0000";

ELSE

CN<='0';

SCOUNT10<=SCOUNT10+1;

END IF;

END IF;

END IF;

END PROCESS;

相关文档
最新文档