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Modelsim简单教程.

Modelsim入门技术文档单位：深圳大学EDA中心实验室指导老师：徐渊作者：陈战夫rshamozhihu@时间：2010-1-7说明：本文档作为EDA中心研究生modelsim入门用。

分三个章节阐述。

1.modelsim中库的编译1.自己新建一个文件夹，如D:\modelsimpro\counter，将counter.v与counter_tb.v文件拷贝到该文件夹下。

2.点击modelsim的图标，打开modelsim的界面窗口。

3.选择File > Change Directory，选择步骤1中的目录，点击OK。

4.选择File > New > Library。

5.在library name与library physical name两栏中均填work.点击OK。

（在transcript窗口中可看到vlib workvmap work work）。

6.选择Compile > Compile，出现如下窗口。

同时选中counter.v与counter_tb.v两个文件。

7.点击compile.再点击done.8.在library标签点击work库前面的“+”号，可看到counter.v与counter_tb.v均在其目录下。

9.双击counter_tb.v可将该设计装载到本次工程库中。

10.选择View > Debug Windows >wave.将弹出波形窗口。

11.在workspace窗口下点击sim标签。

12.右击counter_tb.v，在出现的菜单中选择Add > Add to Wave。

13.在transcript窗口中VSIM>后敲入run 1000.则系统将仿真1000ns.我们可根据波形查看仿真结果。

14.在workspace窗口中点击files标签，鼠标左键双击counter.v，打开counter.v文件。

15.在第10行数字10旁鼠标左键点击一下，可出现一小红点，即断点。

Modelsim 自动化仿真平台搭建

Modelsim do文件的自动化仿真创建虚拟信号
虚拟信号可以把实际信号转化为更人性化的信号，比如将信号的数值转化为字符显示，例如状态机的跳转可以用虚拟信号标注这样更清晰。
virtual type { {1 IDLE} {2 READ} {4 WRITE} {8 STOP} } state_struc 以上简历一个虚拟的结构体，结构体的名字叫state_struc
Modelsim do文件的自动化仿真 Tcl语言的语法
vlib:创建库。格式vlib <library name>,默认库的名字为work 示例： vlib work vmap:映射逻辑库名，将逻辑库名映射库路径。语法格式vmap work <library name> 示例：vlib work work vdir:显示指定库的内容。语法格式vdir –lib <library name> 示例:vdir –lib work vlog:编译Verilog 源代码，库名缺省编译到work本地库，文件按顺序编译。语法格式 vlog
modelsim将加载两次，这种结果不是我们想要的。 .SDO文件并不是标准的延时文件，如果想转到标准的延迟文件可以用以下命令，sdf文件比
sdo文件小加载速度快。sdf文件采用了gzip压缩。 sdfcom netlist/my_design.sdo netlist/my_design.sdf
Modelsim 自动化仿真平台源自Modelsim GUI仿真流程
1. 打开Modelsim 软件，建一个工程文件夹，简历Modelsim 仿真工程。 2. 在用户窗口界面加入需要仿真的所有代码和库文件。 3. 编译有文件 4. 选择testbench顶层文件启动仿真。 5. 选择所要观察的目标信号，并将其加入到波形观察窗口，如需更改bus显示

ModelSimSE中建立Xilinx仿真库

ModelSim SE中建立Xilinx仿真库版本说明：ModelSim SE 6.5，Xilinx 10.1（Xilinx 10.1要安装ModelSim SE 6.3c以上的版本）目录1 ModelSim不同的版本比较 (1)2 ModelSim SE中Xilinx仿真库的建立步骤： (2)2.1 为modelsim生成3个库 (2)2.2 DOS下输入命令法 (6)3 关联Xilinx和ModelSim (6)1 ModelSim不同的版本比较ModelSim分几种不同的版本：SE、PE、LE和OEM，其中SE是最高级的版本而集成在Actel、Atmel、Altera、Xilinx以及Lattice等FPGA厂商设计工具中的均是其OEM版本。

SE版和OEM版在功能和性能方面有较大差别，比如对于大家都关心的仿真速度问题，以Xilinx公司提供的OEM版本ModelSim XE为例，对于代码少于40000行的设计，ModelSim SE 比ModelSim XE要快10倍；对于代码超过40000行的设计，ModelSim SE要比ModelSim XE快近40倍。

以下列表介绍了OEM版本（以Xilinx公司提供的ModelSim XE版本为例）与ModelSim SE版本之间的差异。

ModelSim SE支持PC、UNIX和LINUX混合平台；提供全面完善以及高性能的验证功能；全面支持业界广泛的标准；Mentor Graphics公司提供业界最好的技术支持与服务。

ModelSim版本功能与性能差异技术差异 ModelSim SE ModelSim XE II单一语言支持支持支持im_ver，Unisim_ver，Xilinxcorelib_ver这三个库的，可以采用2.1的方法。

2.2介绍了一种更加简单的方法。

提醒：无论是安装文件的路径还是库的保存路径，都不能含有空格，如不能安装在“p p”的路径下。

Modelsim中建立库文件

5在弹出的对话框中选中新建的库文件的名称在查找范围对话框中选择自己需要编译的库文件然后点击compile如下图所示
在modelsim中建立库的方法步骤如下：
1，打开modelsim，选择FileChange Directory，将当前的地址切换到想要建立库文件的地址，如下图所示：
2，选择FileNewLibrary，如下图所示：
3，在弹出的对话框中填入想命名的库文件名称，选择Ok。如下图所示：
4，选择CompileCompile…，如下图所示：
5，在弹出的对话框中，选中新建的库文件的名称，在“查找范围”对话框中，选择自己需要编译的库文件，然后点击“Compile”，如下图所示：
6，Байду номын сангаас编译结束后，选择“Done”。
7，在modelsim相应的安装目录下，选择modelsim.ini文件，用UE打开，将
lattice_ecp_work =
C:\ispTOOLS8_1\cae_library\simulation\verilog\modelsim_lib\lattice_ecp_work写入该文件中，保存，关系Modelsim，然后重新打开modelsim，即可发现新建库已经在modelsim的Library中。如下图所示：

Modelsim 中建立仿真库的简单方法(我一直用方法3)

方法一（参照方法二，设置真的很复杂....）：奶奶的，搞了一晚上的modelsim仿真库，找了很多方法，找到一种一劳永逸的，介绍如下：看下图，我新建一个工程时，注意到最下面的Copy Setting From，里面的内容是D:/Program Files/modeltech_6.5b/examples/modelsim.ini，我发现这个是modelsim系统的一个默认配置，所以一劳永逸的方法就是更改这个文件：modelsim.ini。

1.参照我的上述路径取消Modelsim.ini配置文件的只读属性。

2.找一个永久保存的路径，比如我的是在在D:\2_Project\FPGA\sim_lib。

打开modelsim，然后file->change Direcory，指向D:\2_Project\FPGA\sim_lib。

3.执行File->New->Library，在弹出的对话框中，Create项选择"a new library and a logical mapping to it"；Library Name项填写新建库的名称，我的是altera_mf_sim；Library Physical Name中也自动修改为altera_mf_sim。

点击OK后，在D:\2_Project\FPGA\sim_lib下将会看到新建的altera_mf_sim文件夹。

4.执行Compile->Compile，弹出如下对话框。

在Library下拉列表中选择库，表示编译工作是对该库进行的，我选择新建的altera_mf_sim库；然后在下面窗口中选择仿真模型文件，这里以altera_mf.v为例，它是quartus自带的仿真模型文件，在quartus安装路径\eda\sim_lib 文件夹中可以找到。

选择库和文件后（可以是多个文件），点击"Compile"按钮，等待编译完成，然后点击"Done"按钮退出。

modelsim使用教程

modelsim使用教程ModelSim是一款常用的硬件描述语言（HDL）仿真工具，本教程将向您介绍如何使用ModelSim进行仿真。

步骤1：安装ModelSim首先，您需要下载和安装ModelSim软件。

在您的电脑上找到安装程序并按照提示进行安装。

步骤2：创建工程打开ModelSim软件，点击"File"菜单中的"New"，然后选择"Project"。

在弹出的对话框中，选择工程的存储位置，并为工程命名。

点击"OK"完成工程创建。

步骤3：添加设计文件在ModelSim的工程窗口中，右键点击"Design"文件夹，选择"Add Existing File"。

然后选择包含您的设计文件的目录，并将其添加到工程中。

步骤4：配置仿真设置在工程窗口中，右键点击"Design"文件夹，选择"Properties"。

在弹出的对话框中，选择"Simulation"选项卡。

在"Top level entity"字段中，选择您的设计的顶层模块。

点击"Apply"和"OK"保存设置。

步骤5：运行仿真在ModelSim的工具栏中，找到"Simulate"按钮，点击并选择"Start Simulation"。

这将打开仿真窗口。

在仿真窗口中，您可以使用不同的命令来控制和观察设计的行为。

步骤6：查看仿真结果您可以在仿真窗口中查看信号波形、调试设计并分析仿真结果。

在仿真窗口的菜单栏中，您可以找到一些常用的查看和分析工具，如波形浏览器、信号分析器等。

步骤7：结束仿真当您完成仿真时，可以选择在仿真窗口的菜单栏中找到"Simulate"按钮，并选择"End Simulation"以结束仿真。

modelsim的详细使用方法

一、简介ModelSim是一款由美国Mentor Graphics公司推出的集成电路仿真软件，广泛应用于数字电路和系统设计领域。

它提供了强大的仿真和验证功能，能够帮助工程师快速高效地进行电路设计与验证工作。

本文将详细介绍ModelSim的使用方法，以帮助读者更好地掌握这一工具的操作技巧。

二、安装与配置1. 下载ModelSim安装包，并解压到指定目录2. 打开终端，进入ModelSim安装目录，执行安装命令3. 安装完成后，配置环境变量，以便在任何目录下都能够调用ModelSim程序4. 打开ModelSim，进行软件注册和授权，确保软件可以正常运行三、工程创建与管理1. 新建工程：在ModelSim主界面点击“File” -> “New” -> “Project”，输入工程名称和存储路径，选择工程类型和目标设备，点击“OK”完成工程创建2. 添加文件：在工程目录下右键点击“Add Existing”，选择要添加的源文件，点击“OK”完成文件添加3. 管理工程：在ModelSim中可以方便地对工程进行管理，包括文件的增删改查以及工程参数的设置等四、代码编写与编辑1. 在ModelSim中支持Verilog、VHDL等多种硬件描述语言的编写和编辑2. 在ModelSim主界面点击“File” -> “New” -> “File”，选择要新建的文件类型和存储位置，输入文件名称，点击“OK”完成文件创建3. 在编辑器中进行代码编写，支持代码高亮、自动缩进、语法检查等功能4. 保存代码并进行语法检查，确保代码符合规范，没有错误五、仿真与调试1. 编译工程：在ModelSim中进行代码编译，生成仿真所需的可执行文件2. 设置仿真参数：在“Simulation”菜单下选择“S tart Simulation”，设置仿真时钟周期、输入信号等参数3. 运行仿真：点击“Run”按钮，ModelSim将开始对设计进行仿真，同时显示波形图和仿真结果4. 调试设计：在仿真过程中，可以通过波形图和仿真控制面板对设计进行调试，查找并解决可能存在的逻辑错误六、波形查看与分析1. 查看波形：在仿真过程中，ModelSim会生成相应的波形文件，用户可以通过“Wave”菜单查看波形并进行波形分析2. 波形操作：支持波形的放大、缩小、平移、选中等操作，方便用户对波形进行分析和观察3. 波形保存：用户可以将波形结果保存为图片或文本文件，以便日后查阅和分析七、性能优化与验证1. 时序优化：在设计仿真过程中，可以通过观察波形和性能分析结果，对设计进行优化，提高设计的时序性能2. 逻辑验证：通过对仿真的结果进行逻辑验证，确保设计符合预期的逻辑功能3. 时序验证：对设计的时序性能进行验证，确保信号传输和时钟同步的正确性八、项目输出与文档整理1. 输出结果：在仿真和验证完成后，可以将仿真结果、波形图和性能分析结果输出为文本文件或图片，方便后续的文档整理和报告撰写2. 结果分析：对仿真结果和验证结果进行详细的分析，确定设计的性能和功能是否符合设计要求3. 文档整理：根据仿真和验证结果，进行文档整理和报告撰写，为后续的设计和优化工作提供参考九、总结与展望ModelSim作为一款专业的集成电路仿真软件，具有着强大的功能和丰富的特性，可以帮助工程师进行电路设计与验证工作。

Modelsim的基本使用流程(没法再省的步骤)

Modelsim的基本使用流程—————By Metcalf 一、预备准备一个源文件和一个相应的测试文件，并在QuartusII或ISE环境下编译成功。

没有的自行百度搜。

二、整体流程工程的建立、编译文件和仿真。

三、具体流程1.工程的建立1）File→New→New Project…2）在D盘新建文件夹，命名为Metcalf(笔者暂时的英文名),将工程命名为Counter_Design,默认库名work,其他选项不需要改动，如图1所示，再点击“OK”。

图1 建立工程3）在弹出的对话框选择“Add Existing File”，又弹出一个对话框，在该对话框点击“Browse..”,添加准备好的两个文件，如图2所示，点击“打开”，选中“Copy to project directory”，如图3所示，点击“OK”，得到的效果如图4所示。

图2 选取文件图3 添加文件到工程里图4 添加文件后的效果2.编译文件Compile→Compile All，产生的效果如图5，注意红色方框内的前后变化。

Library库里work的变化如图6所示。

文件夹的变化如图7。

图5 编译后的效果图6 work的变化图7 文件夹里的变化3.仿真1）Simulate→Start Simulation，弹出图8，选中work里的Counter_Design_TB,去掉Enable optimization的选项，点击“OK”。

图8 选择并设置测试文件2）选中图9中红色方框里的内容，鼠标右击，Add→To Wave→All items in region，出现图10。

图9图103）Simulate→Run→Run-All，额，怎么没有波形，别急，左手按住Ctrl，右手滚动鼠标滑轮，波形图出现了！如图11所示。

图11。

modelsim使用流程

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文档下载后可定制随意修改，请根据实际需要进行相应的调整和使用，谢谢!并且，本店铺为大家提供各种各样类型的实用资料，如教育随笔、日记赏析、句子摘抄、古诗大全、经典美文、话题作文、工作总结、词语解析、文案摘录、其他资料等等，如想了解不同资料格式和写法，敬请关注!Download tips: This document is carefully compiled by theeditor. I hope that after you download them,they can help yousolve practical problems. The document can be customized andmodified after downloading,please adjust and use it according toactual needs, thank you!In addition, our shop provides you with various types ofpractical materials,such as educational essays, diaryappreciation,sentence excerpts,ancient poems,classic articles,topic composition,work summary,word parsing,copy excerpts,other materials and so on,want to know different data formats andwriting methods,please pay attention!1. 建立工程打开 Modelsim 软件。

选择“File”菜单，然后选择“New”->“Project”。

ModelSim入门教程

门级仿真和时序列仿真 (后仿真)
使用综合软件综合后生成的门级网表进行仿真,不加入时延文件的仿真就是门级仿真 .可以检验综合后的功能是否满足功能要求 ,其速度比功能仿真要慢,比时序仿真要快. 在门级仿真的基础上加入时延文件 (.sdf) 的仿真就是时序仿真 ,比较真实地反映了逻辑的时延与功能.综合考虑电路的路径延迟与门延迟的影响，验证电路能否在一定时序条件下满足设计构想的过程，是否存在时序违规
点击run -all
17
(2)我们可以在modelsim内直接编写Testbench Modelsim提供了很多Testbench模板，我们直接拿过来用可以减少工作量。点View->Source->Show Language Templates然后会出现一个加载工程，接着你会发现在刚才的文档编辑窗口左边出现了一个Language Templates窗口
文件对仿真没有影响48moresettings中设置如左图底下的testbenchmodenamevlgvectst对应ver你的主程序名用vhdvectst对应vhdl然后编译以后的同上49先在quarus中生成网表文件和时延文件然后调用modelsim进行仿真quar中设置仿真工具morngs也不用设置50设置完后成功编译quartusii会自动在当前project目录下生成一个simulation目录在该目录下有一个modelsim的文件夹此文件夹下有仿真所需要的网表文件及延时反标文件
9
功能仿真
功能仿真需要的文件
1．设计HDL源代码：可以使VHDL语言或Verilog语言。 2．测试激励代码：根据设计要求输入/输出的激励程序 3．仿真模型/库：根据设计内调用的器件供应商提供的模块而定，如：FIFO、 ADD_SUB等

Modelsim、Synplify.Pro、ISE设计全流程

Modelsim、Synplify.Pro、ISE设计全流程Modelsim、Synplify.Pro、ISE设计全流程第⼀章Modelsim编译Xilinx库本章介绍如何编译HDL必须的Xilinx库和结构仿真。

创建将被编译库的⽬录在编译库之前，最好先建⽴⼀个⽬录（事实上必须建⽴⼀个⽬录），步骤如下。

（假设Modelsim 的安装⽬录是“$Modeltech_6.0”，ISE的安装⽬录是“$Xilinx”）在“$Modeltech_6.0/”⽬录下建⽴⼀个名为XilinxLib的⽂件夹；启动Modelsim后，从“File”菜单项中点击“Change Directory”并指定到刚刚建⽴的那个⽂件夹“XilinxLib”；接下来要做的事情是将Xilinx库编译到“XilinxLib”⽂件夹中。

有三个库需要被编译。

它们分别是“simprims”，“unisims”和“XilinxCoreLib”；（所有这些库⽂件都在“$Xilinx/verilog/src”⽬录下）点击Modelsim中的“Workspace”窗⼝，建⽴⼀个名为Xilinx_CoreLib的新库；（这个操作创建⼀个名为“Xilinx_CoreLib”的⽂件夹，你可以在“Workspace”窗⼝中看到它）?现在开始编译！在“Compile”菜单中点击“Compile”，选择“$Xinlinx/verilog/scr/XilinxCoreLib”⽬录中所有的⽂件，在弹出的对话框中选中刚刚建⽴的“Xilinx_CoreLib”⽂件夹，再点击“Compile”按钮就可以了编译了；⽤同样的⽅式编译其他两个本地库（“simprims”和“unisims”）；⼆、调⽤Xilinx CORE-Generator当需要在设计中⽣成参数化和免费的IP内核（⿊箱⼦）时，⽆论是通过原理图⽅式还是HDL ⽅式，CORE-Generator都是⼀个⾮常有⽤的程序。

ModelSim的简要使用方法

第一章介绍ModelSim的简要使用方法第一课 Create a Project1．第一次打开ModelSim会出现Welcome to ModelSim对话框，选取Create a Project,或者选取File\New\Project,然后会打开Create Project对话框。

2．在Create Project对话框中，填写test作为Project Name；选取路径Project Location作为Project文件的存储目录；保留Default Library Name设置为work。

3．选取OK,会看到工作区出现Project and Library Tab。

4．下一步是添加包含设计单元的文件，在工作区的Project page中，点击鼠标右键，选取Add File to Project。

5．在这次练习中我们加两个文件，点击Add File to Project对话框中的Browse 按钮，打开ModelSim安装路径中的example目录，选取counter.v和tcounter.v，再选取Reference from current location，然后点击OK。

6．在工作区的Project page中，单击右键，选取Compile All。

7．两个文件编译了，鼠标点击Library Tab栏，将会看到两个编译了的设计单元列了出来。

看不到就要把Library的工作域设为work。

8．最后一不是导入一个设计单元，双击Library Tab中的counter，将会出现Sim Tab,其中显示了counter设计单元的结构。

也可以Design\Load design 来导入设计。

到这一步通常就开始运行仿真和分析，以及调试设计，不过这些工作在以后的课程中来完成。

结束仿真选取Design \ End Simulation，结束Project选取File \ Close \ Project。

ModelSim SE中Xilinx仿真库的建立

1. modelsim 库文件编译菜鸟手记在ISE的集成环境中直接仿真波形，需要编译相关的库文件，我先使用网站上timothy的宏文件，结果不能使用，并且使ISE集成环境的部分功能不能使用，卸载ISE和modelsim ,重新安装不行，继续卸载，删除注册表中的相关部分数据，安装，不行，格式化系统，重做系统，安装软件，手工编译库，verilog 库编译没有问题，vhdl 库手工编译不行，到xilinx 技术支持查找，有Running COMPXLIB from the command line (5.1i or later)To obtain the usage information, type "compxlib" at a command prompt. Run "compxlib -help" for details. Examples for using CompXLib with officially supported simulators are provided below. In all examples that do not use the "-p"Switch , it is assumed that the environment is set up for the desired simulator.ModelSim PE (PC example)This example compiles all of the libraries into the specified directory:compxlib -s mti_pe -f all -l all -o c:\modeltech_5.6b\xilinx_libsIf multiple versions of ModelSim are installed, point to the desired executable directory:compxlib -s mti_pe -f all -l all -o c:\modeltech_5.6b\xilinx_libs -p c:\Modeltech_5.6b\win32于是在cmd 方式下d:\xilinx\bin\nt\comxlib -s mti_se -f all -l all -o d:\modeltech_5.6\xilinx_libs运行结束后，一切正常，可以直接从ISE集成环境中调用modelsim 进行仿真模拟。

modelsim使用流程

modelsim使用流程下载温馨提示:该文档是我店铺精心编制而成，希望大家下载以后，能够帮助大家解决实际的问题。

1. 项目设置。

启动 ModelSim 软件并新建一个项目。

ModelSim

一个关于ModelSim的文章:首先，我把我用到的软件说明一下。

如果你发现根据我的操作，你还是解决不了ModelSim后仿真的问题，那就可能是软件版本的问题。

1， ModelSim Se 6.1b2， Synplify Pro 7.5.13， ISE 5.2i （这个是老了点）4， WindowsXP（这个应该没有多大的关系）还有就是我使用的是verilog，我想VHDL的方法与verilog是差不多的，最多也就是在建库方面有点差别而已。

下面的这些方法，是我这3天搞出来的。

当然也参考了一些文章。

如果谁有更方便的方法，欢迎指出来。

一、为modelsim生成3个库。

首先，介绍一下这三个库。

Simprim s_ver:用于布局布线后的仿真。

Unisim s_ver :如果要做综合后的仿真，还要编译这个库。

Xilinxcorelib_ver:如果设计中调用了CoreGen产生的核，则还需要编译这个库。

我们要为modelsim生成的是标准库。

所谓的标准库就是modelsim运行后，会自动加载的库。

不过这方面我还不是很肯定。

因为我在后仿真时，还是要为仿真指定库的路径，不然modelsim找不到。

第一步：在modelsim环境下，新建工程，工程的路径与你想把库存储的路径一致。

第二步：新建库，库名起作simprim s_ver。

我们首先就是要建的就是这个库。

第三步：在modelsim的命令栏上，打下如下命令：vlog -work simprim s_ver d:/Xilinx/verilog/src/simprims/*.v其中的d:/Xilinx是我的Xilinx的安装路径，你把这个改成你的就行了。

以下凡是要根据自己系统环境改变的内容，我都会用绿色标出，并加一个下划线。

编译完之后，你会发现你的工程文件夹下出现了一个simprim s文件夹，里面又有很多个文件夹。

这些就是我们要的库了。

第四步：按照上面的方法，编译另外两个库。

modelsim使用方法

Using ModelSim to Simulate LogicCircuits for Altera FPGA Devices1IntroductionThis tutorial is a basic introduction to ModelSim,a Mentor Graphics’simulation tool for logic circuits.We show how to perform functional and timing simulations of logic circuits implemented by using Quartus II CAD software.The reader is expected to have the basic knowledge of Verilog hardware description language,and the Altera Quartus II CAD software.Contents:•Introduction to simulation•What is ModelSim?•Functional simulation using ModelSim•Timing simulation using ModelSim1 Altera Corporation-University ProgramSeptember20102BackgroundDesigners of digital systems are inevitably faced with the task of testing their designs.Each design can be composed of many modules,each of which has to be tested in isolation and then integrated into a design when it operates correctly.To verify that a design operates correctly we use simulation,which is a process of testing the design by applying inputs to a circuit and observing its behavior.The output of a simulation is a set of waveforms that show how a circuit behaves based on a given sequence of inputs.The generalﬂow of a simulation is shown in Figure1.Figure1.The simulationﬂow.There are two main types of simulation:functional and timing simulation.The functional simulation tests the logical operation of a circuit without accounting for delays in the circuit.Signals are propagated through the circuit using logic and wiring delays of zero.This simulation is fast and useful for checking the fundamental correctness of the designed circuit.The second step of the simulation process is the timing simulation.It is a more complex type of simulation,where logic components and wires take some time to respond to input stimuli.In addition to testing the logical operation of the circuit,it shows the timing of signals in the circuit.This type of simulation is more realistic than the functional simulation;however,it takes longer to perform.2Altera Corporation-University ProgramSeptember2010In this tutorial,we show how to simulate circuits using ModelSim.You need Quartus II CAD software and ModelSim software,or ModelSim-Altera software that comes with Quartus II,to work through the tutorial.3Example DesignOur example design is a serial adder.It takes8-bit inputs A and B and adds them in a serial fashion when the g o input is set to1.The result of the operation is stored in a9-bit sum register.A block diagram of the circuit is shown in Figure2.It consists of three shift registers,a full adder,aﬂip-ﬂop to store carry-out signal from the full adder and aﬁnite state machine(FSM).The shift registers A andB are loaded with the values of A and B.After the st ar t signal is set high,these registers are shifted right one bit at a time.At the same time the least-signiﬁcant bits of A and B are added and the result is stored into the shift register sum.Once all bits of A and B have been added,the circuit stops and displays the sum until a new addition is requested.Figure2.Block diagram of a serial-adder circuit.The Verilog code for the top-level module of this design is shown in Figure3.It consists of the instances of the shift registers,an adder and aﬁnite state machine(FSM)to control this design.3 Altera Corporation-University ProgramSeptember20101.module serial(A,B,start,resetn,clock,sum);2.input[7:0]A,B;3.input resetn,start,clock;4.output[8:0]LEDR;5.6.//Registers7.wire[7:0]A_reg,B_reg;8.wire[8:0]sum;9.reg cin;10.11.//Wires12.wire reset,enable,load;13.wire bit_sum,bit_carry;14.15.//Confrol FSM16.FSM my_control(start,clock,resetn,reset,enable,load);17.18.//Datapath19.shift_reg reg_A(clock,1’b0,A,1’b0,enable,load,A_reg);20.shift_reg reg_B(clock,1’b0,B,1’b0,enable,load,B_reg);21.22.//a full adder23.assign bit_carry,bit_sum=A_reg[0]+B_reg[0]+cin;24.25.always@(posedge clock)26.begin27.if(enable)28.if(reset)29.cin<=1’b0;30.else31.cin<=bit_carry;32.end33.34.shift_reg reg_sum(clock,reset,9’d0,bit_sum,enable,1’b0,sum);35.defparam reg_sum.n=9;36.endmoduleFigure3.Verilog code for the top-level module of the serial adder.The Verilog code for the FSM is shown in Figure4.The FSM is a3-state Mealyﬁnite state machine,where theﬁrst and the third state waits for the st ar t input to be set to1or0,respectively.The computation of the sum of A and B4Altera Corporation-University ProgramSeptember2010happens during the second state,called WORK_STATE.The FSM completes computation when the counter reachesa value of8,indicating that inputs A and B have been added.The state diagram for the FSM is shown in Figure5.1.module FSM(start,clock,resetn,reset,enable,load);2.parameter WAIT_STATE=2’b00,WORK_STATE=2’b01,END_STATE=2’b11;3.input start,clock,resetn;4.output reset,enable,load;5.6.reg[1:0]current_state,next_state;7.reg[3:0]counter;8.9.//next state logic10.always@(*)11.begin12.case(current_state)13.WAIT_STATE:14.if(start)next_state<=WORK_STATE;15.else next_state<=W AIT_STATE;16.WORK_STATE:17.if(counter==4’d8)next_state<=END_STATE;18.else next_state<=WORK_STATE;19.END_STATE:20.if(∼start)next_state<=W AIT_STATE;21.else next_state<=END_STATE;22.default:next_state<=2’bxx;23.endcase24.end25.26.//state registers and a counter27.always@(posedge clock or negedge resetn)28.begin29.if(∼resetn)30.begin31.current_state<=W AIT_STATE;32.counter=’d0;33.end34.else35.beginFigure4.Verilog code for the FSM to control the serial adder(Part a).5 Altera Corporation-University ProgramSeptember201036.current_state<=next_state;37.if(current_state==W AIT_STATE)38.counter<=’d0;39.else if(current_state==WORK_STATE)40.counter<=counter+1’b1;41.end42.end43.//Outputs44.assign reset=(current_state==WAIT_STATE)&start;45.assign load=(current_state==W AIT_STATE)&start;46.assign enable=load|(current_state==WORK_STATE);47.endmoduleFigure4.Verilog code for the FSM to control the serial adder(Part b).Figure5.State diagram.The Verilog code for the shift register is given in Figure6.It consists of synchronous control signals to allow data to be loaded into the shift register,or reset to0.When enable input is set to1and the data is not being loaded or reset, the contents of the shift register are moved one bit to the right(towards the least-signiﬁcant bit).6Altera Corporation-University ProgramSeptember20101.module shift_reg(clock,reset,data,bit_in,enable,load,q);2.parameter n=8;3.4.input clock,reset,bit_in,enable,load;5.input[n-1:0]data;6.output reg[n-1:0]q;7.8.always@(posedge clock)9.begin10.if(enable)11.if(reset)12.q<=’d0;13.else14.begin15.if(load)16.q<=data;17.else18.begin19.q[n-2:0]<=q[n-1:1];20.q[n-1]<=bit_in;21.end22.end23.end24.endmoduleFigure6.Verilog code for the shift register.The design is located in the example/functional and example/timing subdirectories provided with this tutorial.A Quartus II project for this design has been created as well.In the following sections,we use the serial adder example to demonstrate how to perform simulation using Mod-elSim.We begin by describing a procedure to perform a functional simulation,and then discuss how to perform a timing simulation.4Functional Simulation with ModelSimWe begin this tutorial by showing how to perform a functional simulation of the example design.We start by opening the ModelSim program.7 Altera Corporation-University ProgramSeptember2010Figure7.ModelSim window.The ModelSim program window,shown in Figure7,consists of four sections:the main menu at the top,a set of workspace tabs on the left,a work area on the right,and a command prompt at the bottom.The menu is used to access functions available in ModelSim.The workspace contains a list of modules and libraries of modules available to you,as well as details of the project you are working on.The work area on the right is the space where windows containing waveforms and/or textﬁles will be displayed.Finally,the command prompt at the bottom shows feedback from the simulation tool and allows users to enter commands.To perform simulation with ModelSim follow a basicﬂow shown in Figure1.We begin by creating a project where all designﬁles to be simulated are included.We compile the design and then run the simulation.Based on the results of the simulation,the design can be altered until it meets the desired speciﬁcations.4.1Creating a ProjectTo create a project in ModelSim,select New>Project...from the File menu.A create project window shown in Figure8will appear.8Altera Corporation-University ProgramSeptember2010Figure8.Creating a new project.The create project window consists of severalﬁelds:project name,project location,default library name,and copy settingsﬁeld.Project name is a user selected name and the location is the directory where the sourceﬁles are located.For our example,we choose the project name to be serial,to match the top-level module name of our example design,and the location of the project is the example/functional subdirectory.The default library nameﬁeld speciﬁes a name by which ModelSim catalogues designs.For example,a set ofﬁles that describe the logical behaviour of components in an Altera Cyclone II device are stored in the cycloneii library. This allows the simulator to include a set ofﬁles in simulation as libraries rather than individualﬁles,which is particularly useful for timing simulations where device-speciﬁc data is required.For the purpose of this tutorial, specify tutorial as the library name for your project.The lastﬁeld in the create project window is the copy settingsﬁeld.This allows default settings to be copied from the initializationﬁle and applied to your project.Now,click OK to proceed to addﬁles to the project using the window shown in Figure9.Altera Corporation-University Program September20109Figure9.Add aﬁle to project window.The window in Figure9gives several options to addﬁles to the project,including creating newﬁles and directories, or adding existingﬁles.Since theﬁle for this tutorial exists,click Add Existing File and select serial.vﬁle.Once theﬁle is added to the project,it will appear in the Project tab on the left-hand side of the screen,as shown in Figure10.Figure10.Workspace window after the project is created.Now that all designﬁles have been included in the project,click Close to close the window in Figure9.10Altera Corporation-University ProgramSeptember20104.2Compiling a ProjectOnce the project has been created,it is necessary to compile pilation in ModelSim checks if the project ﬁles are correct and creates intermediate data that will be used during simulation.To perform compilation,select Compile All from the Compile menu.When the compilation is successful,a green check mark will appear to the right of the serial.vﬁle in the Project tab.4.3SimulationTo begin a simulation of the design,the software needs to be put in simulation mode.To do this,select Start Simulation...from the Simulate menu.The window in Figure11will appear.Figure11.Start simulation mode in ModelSim.The window to start simulation consists of many tabs.These include a Design tab that lists designs available for simulation,VHDL and Verilog tabs to specify language speciﬁc options,a Library tab to include any additional libraries,and timing and other options in the remaining two tabs.For the purposes of the functional simulation,we only need to look at the Design tab.In the Design tab you will see a list of libraries and modules you can simulate.In this tutorial,we want to simulate a module called serial,described in serial.vﬁle.To select this module,scroll down and locate the tutorial library and click on the plus(+)sign.You will see three modules available for simulation:FSM,serial,and shift_reg.Select the serial module,as shown in Figure11and click OK to begin simulation.When you click OK,ModelSim will begin loading the selected libraries and preparing to simulate the circuit.For the example in this tutorial,the preparation should complete quickly.Once ModelSim is ready to simulate your design, you will notice that several new tabs on the left-hand side of the screen and a new Objects window have appeared, as shown in Figure12.Figure12.New displays in the simulation mode.A key new tab on the left-hand side is the sim tab.It contains a hierarchical display of design units in your circuit in a form of a table.The columns of the table include the instance name,design unit and design unit type names. The rows of the table take a form of an expandable tree.The tree is rooted in the top-level entity called serial.Each module instance has a plus(+)sign next to its name to indicate it can be expanded to allow users to examine the contents of that module instance.Expanding the top-level entity in this view gives a list of modules and/or constructs within it.For example,in Figure12the top-level entity serial is shown to contain an instance of the FSM module,called my_control,three instances of a shift_reg module,four assign statements and an always block.Double-clicking on any of the constructs will cause ModelSim to open a sourceﬁle and locate the given construct within it.Double-clicking on a module instance will open a sourceﬁle and point to the description of the module in the sourceﬁle.In addition to showing modules and/or constructs,the sim tab can be used to locate signals for simulation.Notice that when the serial module is highlighted,a list of signals(inputs,outputs and local wires)is shown in the Objects window.The signals are displayed as a table with four columns:name,value,kind and mode.The name of a signal may be preceded by a plus(+)sign to indicate that it is a bus.The top-level entity comprises signals A,B,resetn, start,and clock as inputs,a sum output and a number of internal signals.12Altera Corporation-University ProgramWe can also locate signals inside of module instances in the design.To do this,highlight a module whose signals you wish to see in the Objects window.For example,to see the signals in the my_control instance of the FSM module, highlight the my_control instance in the sim tab.This will give a list of signals inside of the instance as shown in Figure13.Figure13.Expanded my_control instance.Using the sim tab and the Objects window we can select signals for simulation.To add a signal to simulation, right-click on the signal name in the Objects window and select Add>T o Wave>Selected items from the pop-up ing this method,add signals A,B,clock,resetn,start,sum,and current_state to the simulation.When you do so,a waveform window will appear in the work area.Once you have added these signals to the simulation, press the Undock button in the top-right corner of the waveform window to make it a separate window,as shown in Figure14.Figure14.A simulation window.Before we begin simulating the circuit,there is one more useful feature worth noting.It is the ability to combine signals and create aliases.It is useful when signals of interest are not named as well as they should be,or the given names are inconvenient for the purposes of simulation.In this example,we rename the start signal to go by highlighting the start signal and selecting Combine Signals...from the Tools menu.The window in Figure15will appear.14Altera Corporation-University Programbine signals window.In the textﬁeld labeled Result name type go and press the OK button.This will cause a new signal to appear in the simulation window.It will be named go,but it will have an orange diamond next to its name to indicate that it is an alias.Once the go alias is created,the original start input is no longer needed in the simulation window,so removeit by highlighting it and pressing the delete key.Your simulation window should now look as in Figure16.Figure16.Simulation window with aliased signals.Now that we set up a set of signals to observe we can begin simulating the circuit.There are two ways to run a simulation in ModelSim:manually or by using scripts.A manual simulation allows users to apply inputs and advance the simulation time to see the results of the simulation in a step-by-step fashion.A scripted simulation allows the user to create a script where the sequence of input stimuli are deﬁned in aﬁle.ModelSim can read theﬁle and apply input stimuli to appropriate signals and then run the simulation from beginning to end,displaying results only when the simulation is completed.In this tutorial,we perform the simulation manually.In this simulation,we use a clock with a100ps period.At every negative edge of the clock we assign new values to circuit inputs to see how the circuit behaves.To set the clock period,right-click on the clock signal and select Clock...from the pop-up menu.In the window that appears,set the clock period to100ps and theﬁrst edge to be the falling edge,as shown in Figure17.Then click OK.16Altera Corporation-University ProgramFigure17.Set the clock period.We begin the simulation be resetting the circuit.To reset the circuit,set the resetn signal low by right-clicking on it and selecting the Force...option from the pop-up menu.In the window that appears,set Value to0and click OK. In a similar manner,set the value of the go signal to0.Now that the initial values for some of the signals are set,wecan perform theﬁrst step of the simulation.To do this,locate the toolbar buttons shown in Figure18.The toolbar buttons shown in Figure18are used to step through the simulation.The left-most button is the restartbutton,which causes the simulation window to be cleared and the simulation to be restarted.The textﬁeld,shownwith a100ps string inside it,deﬁnes the amount of time that the simulation should run for when the Run button(tothe right of the textﬁeld)is pressed.The remaining three buttons,Continue,Run-All and Break,can be used toresume,start and interrupt a simulation,respectively.We will not need them in this tutorial.To run a simulation for100ps,set the value in the textﬁeld to100ps and press the Run button.After the simulationrun for100ps completes,you will see the state of the circuit as shown in Figure19.Figure19.Simulation results after100ps.In theﬁgure,each signal has a logic state.Theﬁrst two signals,A and B,are assigned a value between0and1in a blue color.This value indicates high impedance,and means that these signals are not driven to any logic state.The go and resetn signals is at a logic0value thereby resetting the circuit.The clock signal toggles state every50ps, starting with a falling edge at time0,a rising edge at time50ps and another falling edge at100ps.Now that the circuit is reset,we can begin testing to see if it operates correctly for desired inputs.To test the serial adder we will add numbers143and57,which should result in a sum of200.We can set A and B to143and57, respectively,using decimal notation.To specify a value for A in decimal,right-click on it,and choose Force... from the pop-up menu.Then,in the Valueﬁeld put10#143.The10#preﬁx indicates that the value that follows is speciﬁed in decimal.Similarly,set the value of input_B to57.To see the decimal,rather than binary,values of buses in the waveform window we need to change the Radix of A and B to unsigned.To change the radix of these signals,highlight them in the simulation window and select Radix >Unsigned from the Format menu,as shown in Figure20.Change the radix of the sum signal to unsigned as well.18Altera Corporation-University ProgramFigure20.Changing the radix of A,B and sum signals.Now that inputs A and B are speciﬁed,set resetn to1to stop the circuit from resetting.Then set go to1to begin serial addition,and press the Run button to run the simulation for another100ps.The output should be as illustrated in Figure21.Notice that the values of inputs A and B are shown in decimal as is the sum.The circuit also recognizeda go signal and moved to state01to begin computing the sum of the two inputs.Figure21.Simulation results after200ps.To complete the operation,the circuit will require9clock cycles.To fast forward the simulation to see the result,specify900ps in the textﬁeld next to the run button,and press the run button.This brings the simulation to time1100ps,at which point a result of summation is shown on the sum signal,as illustrated in Figure22.Figure22.Simulation results after1100ps.We can see that the result is correct and theﬁnite state machine controlling the serial adder entered state11,in which it awaits the go signal to become0.Once we set the go signal to0and advance the simulation by100ps,the circuit will enter state00and await a new set of inputs for addition.The simulation result after1200ps is shown inFigure23.Figure23.Simulation results after1200ps.At this point,we can begin the simulation for a new set of inputs as needed,repeating the steps described above.Wecan also restart the simulation by pressing the restart button to begin again from time0.By using the functional simulation we have shown that the serial.vﬁle contains an accurate Verilog HDL description20Altera Corporation-University Programof a serial adder.However,this simulation did not verify if the circuit implemented on an FPGA is correct.This is because we did not use a synthesized,placed and routed circuit as input to the simulator.The correctness of the implementation,including timing constraints can be veriﬁed using timing simulation.5Timing Simulation with ModelSimTiming simulation is an enhanced simulation,where the logical functionality of a design is tested in the presence of delays.Any change in logic state of a wire will take as much time as it would on a real device.This forces the inputs to the simulation be realistic not only in terms of input values and the sequence of inputs,but also the time when the inputs are applied to the circuit.For example,in the previous section we simulated the sample design and used a clock period of100ps.This clock period is shorter than the minimum clock period for this design,and hence the timing simulation would fail to produce the correct result.To obtain the correct result,we have to account for delays when running the simulation and use a clock frequency for which the circuit operates correctly.For Altera FPGA-based designs the delay information is available after the design is synthesized,placed and routed, and is generated by Quartus II CAD software.The project for this part of the tutorial has been created for you in the example/timing subdirectory.5.1Setting up a Quartus II Project for Timing Simulation with ModelSimTo perform timing simulation we need to set up Quartus II software to generate the necessary delay information for ModelSim by setting up EDA Tools for simulation in the Quartus II project.To set up EDA Tools for simulation, open the Quartus II project in example/timing subdirectory,and select Settings...from the Assignments menu.A window shown in Figure24will appear.The window in theﬁgure consists of a list on the left-hand side to select the settings category and a window area on the right-hand side that displays the settings for a given category.Select Simulation from the EDA Tool Settings category to see the screen shown on the right-hand side of Figure24.The right-hand side of theﬁgure contains the tool name at the top,EDA Netlist Writer settings in the middle,and NativeLink settings at the bottom.The tool name is a drop-down list containing the names of simulation tools for which Quartus II can produce a netlist with timing information automatically.This list contains many well-known simulation tools,including ModelSim.From the drop-down list select ModelSim-Altera.Once a simulation tool is selected,EDA Netlist Writer settings become available.These settings conﬁgure Quartus II to produce input for the simulation tool.Quartus II will use these parameters to describe an implemented design using a given HDL language,and annotate it with delay information obtained after compilation.The settings we can deﬁne are the HDL language,simulation time scale that deﬁnes time step size for the simulator to use,the location where the writer saves design and delay information,and others.For the purpose of this tutorial,only theﬁrst three settings are used.Set these settings to match those shown in Figure24and click OK.With the EDA Tools Settings speciﬁed,we can proceed to compile the project in Quartus II.The compilation process synthesizes,places,and routes the design,and performs timing analysis.Then it stores the compilation result in theFigure24.Quartus II EDA simulation tool settings.simulation directory for ModelSim to use.Take a moment to examine theﬁles generated for simulation using a text editor.The two mainﬁles are serial.vo,and serial_v.sdo.The serial.voﬁle is a Verilogﬁle for the design.Theﬁle looks close to the original Verilogﬁle,except that the design now contains a wide array of modules with a cycloneii_preﬁx.These modules describe resources on an Altera Cyclone II FPGA,on which the design was implemented using lookup tables,ﬂip-ﬂops,wires and I/O ports. The list delays for each module instance in the design is described in the serial_v.sdoﬁle.22Altera Corporation-University Program5.2Running a Timing SimulationTo simulate the design using timing simulation we must create a ModelSim project.The steps are the same as in the previous section;however,the project is located in the example/timing/simulation/modelsim subdirectory,and the sourceﬁle is serial.vo.We do not need to include the serial_v.sdoﬁle in the project,because a reference to it is included in the serial.voﬁle.Once you added the sourceﬁle to the project,compile it by selecting Compile All from the Compile menu.The next step in the simulation procedure is to place the ModelSim software in simulation mode.In the previous section,we did this by selecting Start Simulation...from the Simulate menu,and specifying the project name. To run a timing simulation there is an additional step required to include the Altera Cyclone II device library in the simulation.This library contains information about the logical operation of modules with cycloneii_preﬁx.To include the Cyclone II library in the project,select Start Simulation...from the Simulate menu and select the Library tab as shown in Figure25.Figure25.Including Altera Cyclone II library in ModelSim project.The Altera Cyclone II library is located in the altera/verilog/cycloneii directory in the ModelSim-Altera software. To add this library to your project,include the altera/verilog/cycloneii directory using the Add...button.Then,clickon the Design tab,select your project for simulation,and click OK.When the ModelSim software enters simulation mode,you will see a signiﬁcant difference in the contents of the workspace tabs on the left-hand side of the window as compared to when you ran the functional simulation.In particular,notice the sim tab and the Objects window shown in Figure26.The list of modules in the sim tab is larger,and the objects window contains more signals.This is due to the fact that the design is constructed using components on an FPGA and is more detailed in comparison to an abstract description we used in the previous section of the tutorial.Figure26.Workspace tabs and Objects window for timing simulation.We simulate the circuit by creating a waveform that includes signals A,B,go,and resetn aliases as before.In addition,we include the clock,reg_sum|q,reg_A|q,and reg_B|q signals from the Objects window.Signals reg_A|q and reg_B|q are registers that store A and B at the positive edge of the clock.The reg_sum|q signal is a register that stores the resulting sum.Begin the simulation by resetting the circuit.To do this,set go and resetn signals to0.Also,set the clock input to have a period of20ns,whoseﬁrst edge is a falling edge.To run the simulation,set the simulation step to20ns and press the Run button.The simulation result is shown in Figure27.24Altera Corporation-University Program。

modelsim建库流程_vip

modelsim建库流程_vipModelsim建库流程——在已有的IEEE库中加⼊新的库⽂件1.将所需要的库对应的vhd⽂件拷贝⾄C:\Actel\Libero_v9.0\Model\vhdl_src\ieee⽂件夹下；2.确保modelsim不是处于仿真状态下：3.编译库中的⽂件，⾸先需要选中库，确认如下4.可以在vhdl模块中调⽤ieee.math_utility_pkg⽂件了。

采⽤上述⽅法，可以加⼊math_utility_pkg和fixed_pkg等vhdl-93中没有包括的库⽂件，增加vhdl语⾔⽀持的综合功能。

5.点击modelsim项⽬⽂件中的presynth.mpf⽂件，可以打开这个modelsim项⽬，然后可以对所有⽂件进⾏编译、仿真等操作。

6.对于定点数运算，需要以下两个库：math_utility_pkg.vhdl - Types used in the fixed point packagefixed_pkg_c.vhdl - Fixed-point package (VHDL-93 compatibility version)⽽这两个库中⼜会调⽤floatfixlib库：这个库包含Actel/Libero_v9.1/Model/vhdl_src/floatfixlib ⽬录下的三个⽂件：fixed_pkg_c.vhd, float_pkg_c.vhd, math_utility_pkg.vhd，也就是说，要⽤这三个⽂件⽣成floatfixlib库。

----------------------------------------------------------------------Modelsim仿真流程－经验总结7.Modelsim简介略。

2.modelsim仿真流程：modelsim基本的仿真流程包括建⽴库、建⽴⼯程并编译、仿真、调试、但在libero环境中运⾏modelsim时，软件⾃动映射库和⽣成⼯程⽂件。

ModelSim,synplify,ISE后仿真流程

ModelSim,synplify,ISE后仿真流程首先，我把我用到的软件说明一下。

如果你发现根据我的操作，你还是解决不了ModelSim 后仿真的问题，那就可能是软件版本的问题。

下面的这些方法，是我这3天搞出来的。

当然也参考了一些文章。

如果谁有更方便的方法，欢迎指出来。

我的邮箱是vf1983cs@。

有空大家多交流。

一、为modelsim生成3个库。

首先，介绍一下这三个库。

Simprim_ver:用于布局布线后的仿真。

Unisim_ver :如果要做综合后的仿真，还要编译这个库。

Xilinxcorelib_ver:如果设计中调用了CoreGen产生的核，则还需要编译这个库。

我们要为modelsim生成的是标准库。

所谓的标准库就是modelsim运行后，会自动加载的库。

不过这方面我还不是很肯定。

因为我在后仿真时，还是要为仿真指定库的路径，不然modelsim找不到。

第一步：在modelsim环境下，新建工程，工程的路径与你想把库存储的路径一致。

第二步：新建库，库名起作simprim_ver。

我们首先就是要建的就是这个库。

第三步：在modelsim的命令栏上，打下如下命令：vlog -work simprim_ver d:/Xilinx/verilog/src/simprims/*.v其中的d:/Xilinx是我的Xilinx的安装路径，你把这个改成你的就行了。

以下凡是要根据自己系统环境改变的内容，我都会用绿色标出，并加一个下划线。

编译完之后，你会发现你的工程文件夹下出现了一个simprim文件夹，里面又有很多个文件夹。

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Modelsim建库流程——在已有的IEEE库中加入新的库文件1.将所需要的库对应的vhd文件拷贝至C:\Actel\Libero_v9.0\Model\vhdl_src\ieee文件夹下；2.确保modelsim不是处于仿真状态下：3.编译库中的文件，首先需要选中库，确认如下4.可以在vhdl模块中调用ieee.math_utility_pkg文件了。

采用上述方法，可以加入math_utility_pkg和fixed_pkg等vhdl-93中没有包括的库文件，增加vhdl语言支持的综合功能。

5.点击modelsim项目文件中的presynth.mpf文件，可以打开这个modelsim项目，然后可以对所有文件进行编译、仿真等操作。

6.对于定点数运算，需要以下两个库：math_utility_pkg.vhdl - Types used in the fixed point packagefixed_pkg_c.vhdl - Fixed-point package (VHDL-93 compatibility version)而这两个库中又会调用floatfixlib库：这个库包含Actel/Libero_v9.1/Model/vhdl_src/floatfixlib 目录下的三个文件：fixed_pkg_c.vhd, float_pkg_c.vhd, math_utility_pkg.vhd，也就是说，要用这三个文件生成floatfixlib库。

----------------------------------------------------------------------Modelsim仿真流程－经验总结7.Modelsim简介略。

2.modelsim仿真流程：modelsim基本的仿真流程包括建立库、建立工程并编译、仿真、调试、但在libero环境中运行modelsim时，软件自动映射库和生成工程文件。

其中功能仿真、综合仿真以及后仿真分别映射presynth、postsynth和postlayout库。

基本流程是：建立工作库→编译源代码→启动仿真→分析、调试。

8.建立库并映射在modelsim中，任何使用VHDL、Verilog HDL、SystemC等语言实现的设计，都被编译到一个库中。

♥方法一：File>New>Library选择新建并映射到该库；♥方法二：在modelsim>提示符下运行命令vlib work2-建立库,vmap work work2-建立映射库；9.建立工程Modelsim仿真需要建立自己的工程，同时modelsim还提供了文件夹管理工程的功能。

♥step1:File>New>project，并指定库文件名；♥step2:新建文件或导入文件；10.编译文件建立好工程后，使用compile功能对源文件进行编译。

Libero环境启动modelsim 时，系统执行run.do脚本文件自动编译源文件。

♥鼠标右击文件，选择compile All对所有的工程文件执行编译操作；♥启动仿真，使用simulation>start simulation>选择design选项卡功能使modelsim进入仿真状态，之后可以运行仿真。

在libero环境下，运行modelsim 直接从运行仿真这一步骤开始。

♥运行仿真可以设置仿真时间或选择仿真全部♥tcl命令： do run.do –当设计修改后，使用此命令重新导入设计；Do wave.do-打开波形列表文件，或者向当前波形添加列表；Restart-复位当前仿真，从0时刻重新仿真；Run 1ms-运行仿真1ms时间；Run all-运行全部的仿真；在libero环境下，可以自己编写脚本文件代替run.do文件，在项目比较大的情况下可以大大简化仿真的操作。

※do wave.do添加自己所需要的波形列表；※restart复位当前仿真到0时刻；※文件名要区别于run.do文件；※libero中设置：Project->settings->simulation导入自己编写的.do文件;2.4分析数据――wave，wave波形窗口直观方便的观察仿真结果，是最常用窗口之一。

可以使用菜单view>wave或者命令view wave打开♥添加信号：※在信号等窗口中右键使用”Add to wave”功能；※在主窗口中使用add wave命令添加信号；※在主窗口中使用do<filename>.do命令添加信号列表；※使用“拖－放”操作，直接从信号、结构等窗口向wave窗口中拖放；♥快捷操作：※波形放大缩小等操作，放大－键盘“＋”，缩小－键盘“－”，全屏－键盘“F”，光标放大－键盘“C”；※区域放大，选中的区域全屏显示；※使添加光标，可以利用光标时间差计算周期等参数；※显示/隐藏信号路径，方便阅读；♥设置断点：※右击变量，选择‘Insert Breakpoint’；当选中的变量波形值发生变化时，仿真自动暂停。

♥保存/打开列表：※波形列表为.do可执行脚本文件；打开列表可以使用do<filename>.do命令执行；※waveform formats选项保存变量、显示方式及变量相对位置等属性；♥保存/打开波形：※波形文件为.wlf格式文件，使用File>datasets>saveas 来保存波形；※波形文件可用于波形对比的对象，使用File>datasets>open来打开；♥波形对比：※在AE版本中，只能实现简单的手动对比波形；※用File>datasets方式打开波形文件，向wave窗口中添加需要对比的信号；♥分析数据――list:表格化显示数据，方便通过搜索特殊值或者特定条件的数据，简化分析数据的过程。

List窗口可通过菜单View>list，或者命令view list 打开。

♥分析数据――source：source窗口具有完全的编辑能力，同时提供分析数据的一些操作。

Source窗口可通过双击workspace的总的文件或信号打开。

※查看变量值：鼠标停留在变量上面，可显示当前值；※设置断点: source源代码窗口设置条件断点；♥分析数据――Memories: memory窗口列出工程中存储单元的数据，方便调试存储器的操作。

※step1:展开调用RAM单元的模块，并展开至RAM_ROC>STATCONFIG;※step2:objects窗口选择MEM_512_9选择View Memory Contonts；♥分析数据――watch: watch窗口中可实现监测变量的变化情况，watch窗口可通过菜单view>watch,或者命令view watch打开。

Watch窗口中的对象可以以拖拉的方式从object窗口、wave窗口、source窗口中拖拉进来；♥分析数据――signals:signals窗口显示被选中进程模块的变量、变量值。

Signals窗口可通过菜单view>signals，或者命令view signals打开。

※排序：支持按字母的升序或降序排列。

※拖放操作：可以将信号拖动到wave、list、watch窗口；※过滤器：选择要察看的信号（输入、输出部信号等等）。

※对信号右键操作，可查看源代码；3、Modelsim高级功能 SE版本支持，AE版本不支持的功能。

3．1 Code Coverage Modelsim SE版可以统计代码覆盖率。

代码覆盖率是指代码的覆盖程度，是一种度量方式。

※语句覆盖(statement Coverage)※分支覆盖(Branch Coverage)※条件覆盖(Condition Coverage)※状态机覆盖(FSM Coverage)※路径覆盖(Path Coverage)Modelsim SE版本可以测试代码覆盖率，代码覆盖率是测试验证的一个重要指标♥关于测试验证中的一般观点：※覆盖率只代表测试过哪些代码，不代表是否测试好这些代码；※不要过于相信覆盖率数据；※一个稳定的全面的测试仿真要求某些覆盖率尽量100％；※路径覆盖率>判定覆盖>语句覆盖。

♥统计覆盖率操作流程：※step1:设置编译选项，勾选要统计的代码覆盖率类别；※step2:使能代码覆盖率统计功能，启动仿真；※运行仿真，并分析数据；3．2Waveform Compare 波形对比能快速定位设计在修改前后的区别，在进行波形对比之前要保存原设计的波形文件，此文件为作为对比文件。

※step1:打开波形对比向导设置；tools->waveform compare->comparison wizard;※step2:导入波形文件，作为对比对象；※step3:选择对比信号的范围；※step4:根据信号范围选择需要对比的信号；※step5:分析数据；3．3 追踪数据流：数据流窗口能够对VHDL信号或者Verilog的线网型变量进行图示化跟踪，在界面中驱动信号或驱动线网变量的进程显示在左边，反之被驱动信号显示在右边。

可通过双击wave窗口中需要追踪的信号打开dataflow窗口。

※观察设计的连接性：可以检查设计的物理连接性，可以逐个单元的观察所关注的信号、互联网络或寄存器的输入/输出情况。

※跟踪事件：跟踪一个非预期的输出事件，使用嵌入波形观察器，可以由一个信号的跳变回溯追踪，查到事件的源头。

※追踪未知态：未知态在设计中是传递的，用dataflow中Trace>chaseX功能很容易追踪不定态的来源。

※显示层次结构：可以使用层次化实例显示设计的连通性。

数据流窗口追踪不定态的功能是工程师比较青睐的，在dataflow窗口中使用Trace>ChaseX功能，不断往驱动级追踪不定态传递的源头。

小结：仿真验证在整个项目的过程中有着重要的意义，科学合理的仿真方法和仿真技巧可以达到事半功倍的效果；反之，如果只是一味的理论分析而不会整合利用多种工具的优点特点，可能项目会寸步难行。

做到：※合理仿真系统的每一个模块，缩短系统的设计周期；※完整支持从功能前到布局布线后的仿真功能。