MIPI高速性能和电气特性测试
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DigRF v3
DSI Display CSI Camera Unipro Other
BB-IC debug ports Shared pins
- In development - DPhy is in definition, almost final - Physical layer solution volume Shipment Oct 08 - MPhy definition to start end of the year - DPhy Solution also requires Logic Analyzer. Minor adaptations to configuration are possible because standard is not defined yet!
The Stimulus Test Setup
• Full coverage of stimulus signal generation with flexible signal conditioning • Full Stress / Jitter tolerance testing • Modular configuration for 1, 2 or multiple lanes • Test Automation Software with MIPI Editor and pre-canned test pattern • Multi-application support by ParBERT platform (e.g. HDMI) • Depending on device design, full BER Analysis possible Multi Application Tester 7 Gbit/s
E4438C Signal Generator / clock source 81150A Noise / Jitter source
Economic High speed Tester 3.35 Gbit/s
81150A Noise / Jitter source
81250A ParBERT
81250A ParBERT
High Speed Digital Test
Enabling MIPI Physical Layer Test
July, 2008
Enabling MIPI D-PHY Physical Layer Test
Characterization at your fingertips
Next Level of Performance and Convenience through Test Automation
MIPI D-PHY operates in two modes with dynamic transitions
Low Power Signaling
High Speed Signal
Low Power Signaling
Low Power Signal High Speed Signal - Max 20 Mbit - > 1 Gbit -Single ended -Differential - CMOS -LVDS
MIPI D-Phy CSI
TX RX RF-IC
RX
TX
MIPI D-Phy
WiMAX
Camera
Enabling MIPI Physical Layer Test
Page 6
July, 2008
Enabling MIPI D-PHY Physical Layer Test
Control the transition
Protocol Viewer Dig RF tester
Digital Domain
Digital Physical Layer Debug / Validation
Pulse Function Arbitrary Noise Generator
BERT
Wide Band Oscilloscope
High Speed Digital Test
Enabling MIPI Physical Layer Test
July, 2008
Enabling Physical Layer Test – Bit Error Testing
Stress your device to its limits
RX Tests: Sensitivity and jitter tolerance on clock and data
High Speed From nominal to stress test
Agilent 81250A ParBERT Agilent 81150A Noise Source
Generate the signal you need
Control and synchronize transitions between different modes and channels
Multiple RF functions
– GPS – Bluetooth – WCDMA – GSM – WLAN – FM
Request for more bandwidth High speed serialization Digitization of IQ
Multiple Peripherals
Enabling MIPI Physical Layer Test
Page 4
July, 2008
The MIPI Evolution
Test & Debug Port Physical layers DigRF v3
MIPI DPhy
Protocol layers
Status
- Shipping today
Stress
RX Device Under Test Generator Solution
Expected Data Compare Bit Error Ratio
Data Analyzer Error Detector
- For several lanes at least 2 data and clock - Devices show immunity at combined jitter testing; data and clock needs to be tested independently - For all kinds of jitter and stress test - Jitter injection from 81150A via delay line to the ParBERT 81250A
The ParBERT 81250A
- Generates the signal you need - Controls the sequences - Forces the bus through low to high speed transition and vice versa - Glitch free change of timing parameters
Enabling MIPI Physical Layer Test
MIPI MPhy
DigRF v4
Page 5
July, 2008
How to Get Confidence on the Physical Layer Characterizing the Parameters
TX Tests:
Data bus timing Transition times DC levels and AC swing Low Power / High Speed mode switching Jitter
From Analog to Digital
The Digital Interface
• Is easier and cheaper to implement • Will consume less battery power • Provides higher bandwidth • Reduces the number of IC pins • Allows for easier “plug and play” between devices
N5990A Test Automation Software
N5990A Test Automation Software
High Speed Digital Test
Enabling MIPI Physical Layer Test
July, 2008
Agilent MIPI D-PHY Physical Layer Test
– Camera – Display – Audio in /out – Mobile TV – DVB-H – Other IOs
Power Management
Enabling MIPI Physical Layer Test
Page 2
July, 2008
Emergence of Standard Digital Interconnects
• Calibrated test cases
• Easy post processing • SQL data base interface • Interaction with legacy code
Enabling MIPI Physical Layer Test
Page 9
J ul3 y, 2008 Ju ly
N5990A Test Automation Software and MIPI Frame Generator One button Rx and Tx compliance tests and characterization
• MIPI D-PHY Editor • Pre-canned test pattern
Enabling MIPI Physical Layer Test
Page 3
July, 2008
Agilent Solution Offering
Wireless Domain
Biblioteka Baidu
Wireless Protocol Layer Validation Wireless Physical Layer Validation Digital Protocol Layer Debug / Validation
Enabling MIPI Physical Layer Test
High Speed Test and Characterization
High Speed Digital Test
Enabling MIPI Physical Layer Test
July, 2008
The Explosion of Functions within Mobile Devices
RX
MIPI D-Phy DSI
Timing
Levels
Signal Integrity
2.5G 3GPP
TX BB-IC RX TX
DigRF v3
RX Tests:
Data bus timing Min. pulsewidth Sensitivity (min/max amplitude) Jitter Tolerance on Clock and Data Differential and common mode, termination switching
MIPI DPHY CSI
Wireless Domain
LTE WiMAX
RF IC
Standards inherited from the computer industry
DigRF
BB IC
BUT
• Breaking the GBit barrier requires dedicated jitter stress test – on clock and data separately
MIPI DPHY DSI
AP
Digital Domain
• Power safe requires wake up and therefore different signal extremes, low power and high speed
Wireless Handset
Mobile Industry specific standards