状态机例子-自动售货机
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Digital System Design
1
2011/6/21
Computer Faculty of Guangdong University of Technology
例:用三进程状态机实现一个简单自动售货机控制电路,电路框图如下。该电路有两个投币口(1元和5角),商品2元一件,不设找零。In[0]表示投入5角,In[1]表示投入1元,Out 表示是否提供货品。
自动 售货机
In[0] In[1] Clk Reset
Out
自动售货机顶层结构框图
Digital System Design
2
2011/6/21
Computer Faculty of Guangdong University of Technology
根据题意,可分析出状态机的状态包括: S0(00001):初始状态,未投币或已取商品 S1(00010):投币5角 S2(00100):投币1元 S3(01000):投币1.5元 S4(10000):投币2元或以上
用独热码表示状态编码,如上所示。相应状态转换图如下(按Moore 状态机设计)。
Digital System Design
3
2011/6/21
Computer Faculty of Guangdong University of Technology
xx/1
01/0 10/0
10/0
01/0
01/0
S1
S0
S4
S2
Reset
自动售货机状态转换图
10/0
S3
01/0
x1/0
Digital System Design
4
2011/6/21
Computer Faculty of Guangdong University of Technology
设计代码
第一个Always 块:状态转移。
`timescale 1ns/100ps
module saler_3always(Reset,Clk,In,Out); input Clk,Reset; input [1:0] In; output Out; reg Out;
reg [4:0] state, next_state;
parameter S0=5'b00001, S1=5'b00010, S2=5'b00100, S3=5'b01000,S4=5'b10000; always @(posedge Clk or posedge Reset)
Digital System Design
5
2011/6/21
Computer Faculty of Guangdong University of Technology
begin if (Reset) state<=S0; else
state<=next_state; end
第二个Always 块:状态转移的组合逻辑条件判断
always @(state or In) begin case(state)
S0:begin if (In[1]) next_state<=S2;
Digital System Design
6
2011/6/21
Computer Faculty of Guangdong University of Technology
else if(In[0]) next_state<=S1;
else
next_state<=S0; end S1:begin if (In[1]) next_state<=S3; else if(In[0]) next_state<=S2; else
next_state<=S1;
end S2:begin if (In[1]) next_state<=S4; else if(In[0]) next_state<=S3;
else
next_state<=S2; end S3:begin
if (In[0]|In[1]) next_state<=S4;
Digital System Design
7
2011/6/21
Computer Faculty of Guangdong University of Technology
else
next_state<=S3; end S4:begin
next_state<=S0;
end
default:next_state<=S0; endcase end
第三个Always 块:输出组合逻辑
always @(state ) begin
case(state) S0:begin
Out<=0; end S1:begin Out<=0;
Digital System Design
8
2011/6/21
Computer Faculty of Guangdong University of Technology
end S2:begin
Out<=0;
end S3:begin Out<=0; end
S4:begin
Out<=1;
end
default:Out<=0; endcase end endmodule
测试平台代码