Xilinx 开发板用户手册

SP605 Hardware User Guide

UG526 (v1.6) July 18, 2011

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Revision History

The following table shows the revision history for this document.

Date Version Revision

10/07/09 1.0Initial Xilinx release.

11/09/09 1.1•Updated Figure1-17 and Figure1-23.

•Changed speed grade from -2 to -3.

•Miscellaneous typographical edits.

02/01/10 1.1.1Minor typographical edits to Table1-24 and Table1-25.

05/18/10 1.2Updated Figure1-2. Added Note 6 to Table1-11. Updated board connections for

SFP_TX_DISABLE in Table1-12. Added note about FMC LPC J63 connector in 18. VITA

57.1 FMC LPC Connector. Updated U1 FPGA Pin column for FMC_LA00_CC_P/N in

Table1-28. Updated description of PMBus Pod and TI Fusion Digital Power Software

GUI in Onboard Power Regulation. Updated Appendix B, VITA 57.1 FMC LPC

Connector Pinout, and Appendix C, SP605 Master UCF.

06/16/10 1.3Updated 2. 128 MB DDR3 Component Memory. Added note 1 to Table1-30.

09/24/10 1.4Updated description of Fusion Digital Power Software in Onboard Power Regulation.

02/16/11 1.5Revised oscillator manufacturer information from Epson to SiTime in Table1-1. Revised

oscillator manufacturer information from Epson to SiTime on page page23. Deleted note

on page 44 referring to J55: “Note: This header is not installed on the SP605 as built.”

Revised values for R50 and R216 in Figure1-12. Revised oscillator manufacturer

information from Epson to SiTime on page page69.

07/18/11 1.6Corrected “jitter” to “stability” in section Oscillator (Differential), page23. Revised the

feature and notes descriptions for reference numbers 6 and 12 in Table1-1, page10.

Revised FPGA pin numbers for ZIO and RZQ in Table1-4, page14. Added Table1-29,

page52, Table1-31, page55, and table notes in Table1-30.

SP605 Hardware User Guide UG526 (v1.6) July 18, 2011