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SP605 Hardware User GuideUG526 (v1.6) July 18, 2011© Copyright 2009–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DISCLAIMERThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. 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Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:/warranty.htm#critapps.Revision HistoryThe following table shows the revision history for this document.Date Version Revision10/07/09 1.0Initial Xilinx release.11/09/09 1.1•Updated Figure1-17 and Figure1-23.•Changed speed grade from -2 to -3.•Miscellaneous typographical edits.02/01/10 1.1.1Minor typographical edits to Table1-24 and Table1-25.05/18/10 1.2Updated Figure1-2. Added Note 6 to Table1-11. Updated board connections forSFP_TX_DISABLE in Table1-12. Added note about FMC LPC J63 connector in 18. VITA57.1 FMC LPC Connector. Updated U1 FPGA Pin column for FMC_LA00_CC_P/N inTable1-28. Updated description of PMBus Pod and TI Fusion Digital Power SoftwareGUI in Onboard Power Regulation. Updated Appendix B, VITA 57.1 FMC LPCConnector Pinout, and Appendix C, SP605 Master UCF.06/16/10 1.3Updated 2. 128 MB DDR3 Component Memory. Added note 1 to Table1-30.09/24/10 1.4Updated description of Fusion Digital Power Software in Onboard Power Regulation.02/16/11 1.5Revised oscillator manufacturer information from Epson to SiTime in Table1-1. Revisedoscillator manufacturer information from Epson to SiTime on page page23. Deleted noteon page 44 referring to J55: “Note: This header is not installed on the SP605 as built.”Revised values for R50 and R216 in Figure1-12. Revised oscillator manufacturerinformation from Epson to SiTime on page page69.07/18/11 1.6Corrected “jitter” to “stability” in section Oscillator (Differential), page23. Revised thefeature and notes descriptions for reference numbers 6 and 12 in Table1-1, page10.Revised FPGA pin numbers for ZIO and RZQ in Table1-4, page14. Added Table1-29,page52, Table1-31, page55, and table notes in Table1-30.SP605 Hardware User Guide UG526 (v1.6) July 18, 2011SP605 Hardware User Guide 3UG526 (v1.6) July 18, 2011Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Chapter 1: SP605 Evaluation BoardOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Additional Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Related Xilinx Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101. Spartan-6 XC6SLX45T-3FGG484 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132. 128 MB DDR3 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164. Linear BPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18FPGA Design Considerations for the Configuration Flash . . . . . . . . . . . . . . . . . . . . . . . 205. System ACE CF and CompactFlash Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206. USB JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Oscillator (Differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24SMA Connectors (Differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258. Multi-Gigabit Transceivers (GTP MGTs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259. PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2810. SFP Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3011. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3112. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3313. DVI CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3414. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3615. Status LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Ethernet PHY Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39FPGA INIT and DONE LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4016. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41User Pushbutton Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42User DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43User SIP Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44User SMA GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4517. Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Power On/Off Slide Switch SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table of ContentsSP605 Hardware User Guide UG526 (v1.6) July 18, 2011FPGA_PROG_B Pushbutton SW3 (Active-Low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47SYSACE_RESET_B Pushbutton SW9 (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47System ACE CF CompactFlash Image Select DIP Switch S1 (Active-High) . . . . . . . . . . 48Mode DIP Switch SW1 (Active-High). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4918. VITA 57.1 FMC LPC Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5019. Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52AC Adapter and 12V Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Onboard Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Appendix A: Default Jumper and Switch Settings Appendix B: VITA 57.1 FMC LPC Connector Pinout Appendix C: SP605 Master UCF Appendix D: ReferencesPreface About This GuideThis manual accompanies the Spartan®-6 FPGA SP605 Evaluation Board and containsinformation about the SP605 hardware and software tools.Guide ContentsThis manual contains the following chapters:•Chapter1, SP605 Evaluation Board, provides an overview of and details about thecomponents and features of the SP605 board.•Appendix A, Default Jumper and Switch Settings.•Appendix B, VITA 57.1 FMC LPC Connector Pinout.•Appendix C, SP605 Master UCF.•Appendix D, References.Additional DocumentationThe following documents are available for download at/products/spartan6/.•Spartan-6 Family OverviewThis overview outlines the features and product selection of the Spartan-6 family.•Spartan-6 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and switching characteristic specifications for theSpartan-6 family.•Spartan-6 FPGA Packaging and Pinout SpecificationsThis specification includes the tables for device/package combinations and maximumI/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, andthermal specifications.•Spartan-6 FPGA Configuration User GuideThis all-encompassing configuration guide includes chapters on configurationinterfaces (serial and parallel), multi-bitstream management, bitstream encryption,boundary-scan and JTAG configuration, and reconfiguration techniques.•Spartan-6 FPGA SelectIO Resources User GuideThis guide describes the SelectIO™ resources available in all Spartan-6 devices.•Spartan-6FPGA Clocking Resources User GuideSP605 Hardware User Guide 5 UG526 (v1.6) July 18, 2011Preface:About This GuideThis guide describes the clocking resources available in all Spartan-6 devices,including the DCMs and PLLs.•Spartan-6 FPGA Block RAM Resources User GuideThis guide describes the Spartan-6 device block RAM capabilities.•Spartan-6 FPGA GTP Transceivers User GuideThis guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs.•Spartan-6 FPGA DSP48A1 Slice User GuideThis guide describes the architecture of the DSP48A1 slice in Spartan-6FPGAs andprovides configuration examples.•Spartan-6 FPGA Memory Controller User GuideThis guide describes the Spartan-6 FPGA memory controller block, a dedicatedembedded multi-port memory controller that greatly simplifies interfacingSpartan-6FPGAs to the most popular memory standards.•Spartan-6 FPGA PCB Designer’s GuideThis guide provides information on PCB design for Spartan-6 devices, with a focus onstrategies for making design decisions at the PCB and interface level.Additional Support ResourcesTo search the database of silicon and software questions and answers or to create atechnical support case in WebCase, see the Xilinx website at:/support. SP605 Hardware User GuideUG526 (v1.6) July 18, 2011Chapter1 SP605 Evaluation BoardOverviewThe SP605 board enables hardware and software developers to create or evaluate designstargeting the Spartan®-6 XC6SLX45T-3FGG484 FPGA.The SP605 provides board features common to many embedded processing systems. Somecommonly used features include: a DDR3 component memory, a 1-lane PCI Express®interface, a tri-mode Ethernet PHY, general purpose I/O and a UART. Additional userdesired features can be added through mezzanine cards attached to the onboard highspeed VITA-57 FPGA Mezzanine Connector (FMC) low pin count (LPC) connector.Features, page8 provides a general listing of the board features with details provided inDetailed Description, page10.Additional InformationAdditional information and support material is located at:•/sp605This information includes:•Current version of this user guide in PDF format•Example design files for demonstration of Spartan-6 FPGA features and technology•Demonstration hardware and software configuration files for the System ACE™ CFcontroller, Platform Flash configuration storage device, and linear flash chip•Reference Design Files•Schematics in PDF format and DxDesigner schematic format•Bill of materials (BOM)•Printed-circuit board (PCB) layout in Allegro PCB format•Gerber files for the PCB (Many free or shareware Gerber file viewers are available onthe Internet for viewing and printing these files.)•Additional documentation, errata, frequently asked questions, and the latest newsFor information about the Spartan-6 family of FPGA devices, including product highlights,data sheets, user guides, and application notes, see the Spartan-6 FPGA website at/support/documentation/spartan-6.htm.SP605 Hardware User Guide 7 UG526 (v1.6) July 18, 2011SP605 Hardware User GuideUG526 (v1.6) July 18, 2011Chapter 1:SP605 Evaluation BoardFeaturesThe SP605 board provides the following features (see Figure 1-2 and Table 1-1):• 1. Spartan-6 XC6SLX45T-3FGG484 FPGA • 2. 128 MB DDR3 Component Memory • 3. SPI x4 Flash • 4. Linear BPI Flash• 5. System ACE CF and CompactFlash Connector • 6. USB JTAG •7. Clock Generation •Fixed 200 MHz oscillator (differential)•Socket with a 2.5V 27MHz oscillator (single-ended)•SMA connectors (differential)•SMA connectors for MGT clocking (differential)•8. Multi-Gigabit Transceivers (GTP MGTs)•FMC LPC connector •SMA •PCIe•SFP module connector •9. PCI Express Endpoint Connectivity •Gen1 x1•10. SFP Module Connector•11. 10/100/1000 Tri-Speed Ethernet PHY •12. USB-to-UART Bridge •13. DVI CODEC •14. IIC Bus •IIC EEPROM - 1KB •D VI COD EC •DVI connector •FMC LPC connector •SFP Module connector •15. Status LEDs •Ethernet Status •FPGA INIT •FPGA D ONE •16. User I/O •USER LED GPIO •User pushbuttons •CPU Reset pushbutton •User D IP switch - GPIO •User SMA GPIO connectorsSP605 Hardware User Guide 9UG526 (v1.6) July 18, 2011Overview•17. Switches •Power On/Off slide switch •System ACE CF Reset pushbutton•System ACE CF bitstream image select DIP switch •Mode D IP switch•18. VITA 57.1 FMC LPC Connector •19. Power Management •AC Adapter and 12V Input Power Jack/Switch •Onboard Power Regulation•Configuration Options • 3. SPI x4 Flash (both onboard and off-board)• 4. Linear BPI Flash• 5. System ACE CF and CompactFlash Connector •6. USB JTAGBlock DiagramFigure 1-1 shows a high-level block diagram of the SP605 and its peripherals.Figure 1-1:SP605 Features and BankingSP605 Hardware User Guide UG526 (v1.6) July 18, 2011Chapter 1:SP605 Evaluation BoardRelated Xilinx DocumentsPrior to using the SP605 Evaluation Board, users should be familiar with Xilinx resources. See the following locations for additional documentation on Xilinx tools and solutions:•ISE: /ise•Answer Browser: /support •Intellectual Property: /ipcenterDetailed DescriptionFigure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document.The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1.Figure 1-2:SP605 Board Photo15e1316b197a15h1234815g8517c7c93, 14 (on backside)7b 101861216c1116a15f15c17d16d17b15b 15a17a19b15dUG526_02 _050610Table 1-1:SP605 FeaturesNumberFeatureNotesSchematic Page1Spartan-6 FPGAXC6SLX45T-3FGG484 FPGA 2–72DDR3 Component Memory Micron MT41J64M16LA-187E 93SPI Header Ext. x4SPI Flash x4 (on backside)Winbond W25Q64VSFIG184Linear BPI Flash x16Numonyx JS28F256P30T95195System ACE CompactFlashSocketXCCACE-TQ144I Controller206USB UART (USB-to-UARTBridge)Silicon Labs CP2103GM327Clock Generation200 MHz OSC, oscillator socket,SMA connectors13, 14a. 200 MHz oscillator SiTime 200 MHz 2.5V LVDS14b. Oscillator socket, single-ended, LVCMOSMMD Components 2.5V 27 MHz14c. SMA connectors SMA pair P(J41) / N(J38)138GTP port SMA x4 andMGT Clocking SMA (REFCLK)MGT RX,TX Pairs x4 SMA MGTREFCLK x2 SMA139PCIe 1-lane edge conn.(Gen 1)Card Edge Connector, 1-lane12 10SFP Module Cage/Connector AMP 136073-112 11Ethernet 10/100/1000Marvell M88E1111 EPHY11 12USB JTAG Conn. (USB Mini-B)USB JTAG Download Circuit15 13DVI Codec and Video Connector Chrontel CH7301C-TF16,17 14IIC EEPROM (on backside)ST Micro M24C08-WDW6TP1515Status LEDs10, 11, 14,18, 20, 25,27, 31, 33a. FMC Power Good10b. System ACE CF Status 11c. FPGA INIT and DONE14d. Ethernet PHY Status18e. JTAG USB Status20f. FPGA Awake27g. TI Power Good31h. MGT AVCC, DDR3 TermPwr Good3316a. User LEDs (4)Red LEDs (active-High)14b. User Pushbuttons (4)Active-High14c. User DIP Switch (4-pole)4-pole (active-High)14d. User SMA (2)GPIO x2 SMA13Number Feature Notes Schematic PageSP605 Hardware User Guide 1. Spartan-6 XC6SLX45T -3FGG484 FPGAA Xilinx Spartan-6 XC6SLX45T-3FGG484 FPGA is installed on the SP605 Evaluation Board.ReferencesSee the Spartan-6 FPGA Data Sheet. [Ref 1]ConfigurationThe SP605 supports configuration in the following modes:•JTAG (using the included USB-A to Mini-B cable)•JTAG (using System ACE CF and CompactFlash card)•Master SPI x4•Master SPI x4 with off-board device •Linear BPI FlashFor details on configuring the FPGA, see Configuration Options .Mode switch SW1 (see Table 1-32, page 57) is set to 10 = Slave SelectMAP to choose the System ACE CF default configuration.ReferencesSee the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]17SwitchesPower, Configuration, Pushbutton Switches14, 18, 20,25a. SP605 Power On-Off Slide Switch25b. FPGA Mode DIP Switch 18c. System ACE CFConfiguration DIP Switch 20d. FPGA PROG, CPU Reset, and System ACE CF Reset Pushbutton Switches14, 2018FMC LPC Connector Samtec ASP-134603-011019a. Power Management Controller2x TI UCD9240PFC 21, 26b. Mini-Fit Type 6-Pin, ATX Type 4-pin12V input power connectors25NumberFeatureNotesSchematic PageI/O Voltage RailsThere are four available banks on the XC6SLX45T-3FGG484 device. Banks 0, 1, and 2 areconnected for 2.5V I/O. Bank 3 is used for the 1.5V DDR3 component memory interface ofSpartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banksused by the SP605 board is summarized in Table1-2.Table 1-2:I/O Voltage Rail of FPGA BanksFPGA Bank I/O Voltage Rail0 2.5V1 2.5V2 2.5V3 1.5VReferencesSee the Xilinx Spartan-6 FPGA documentation for more information at/support/documentation/spartan-6.htm.2. 128 MB DDR3 Component MemoryThere are 128 MB of DDR3 memory available on the SP605 board. A 1-Gb MicronMT41J64M16LA-187E (96-ball) DDR3 memory component is accessible through Bank 3 ofthe LX45T device. The Spartan-6 FPGA hard memory controller is used for data transferacross the DDR3 memory interface’s 16-bit data path using SSTL15 signaling. The SP605board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides thestandard memory controller block (MCB) performance of 667Mb/s for DDR3 memory ina -3 speed grade device. Signal integrity is maintained through DDR3 resistor terminationsand memory on-die terminations (ODT), as shown in Table1-3 and Table1-4.Table 1-3:Termination Resistor RequirementsSignal Name Board Termination On-Die Termination MEM1_A[14:0]49.9Ω to V TT –MEM1_BA[2:0]49.9Ω to V TT –MEM1_RAS_N49.9Ω to V TT –MEM1_CAS_N49.9Ω to V TT –MEM1_WE_N49.9Ω to V TT –MEM1_CS_N100Ω to GND –MEM1_CKE 4.7KΩ to GND –MEM1_ODT 4.7KΩ to GND –MEM1_DQ[15:0] –ODTMEM1_UDQS[P,N], MEM1_LDQS[P,N] –ODTMEM1_UDM, MEM1_LDM –ODTSP605 Hardware User Guide Table 1-5 shows the connections and pin numbers for the DDR3 Component Memory.MEM1_CK[P ,N]100Ω differential at memorycomponent–Notes:1.Nominal value of V TT for DDR3 interface is 0.75V .Table 1-4:FPGA On-Chip (OCT) Termination External Resistor Requirements U1 FPGA PinFPGA Pin NumberBoard Connection for OCTZIO M7No Connect RZQK7100Ω to GROUNDTable 1-5:DDR3 Component Memory ConnectionsU1 FPGA PinSchematic Net NameMemory U42Pin NumberPin NameK2MEM1_A0N3A0K1MEM1_A1P7A1K5MEM1_A2P3A2M6MEM1_A3N2A3H3MEM1_A4P8A4M3MEM1_A5P2A5L4MEM1_A6R8A6K6MEM1_A7R2A7G3MEM1_A8T8A8G1MEM1_A9R3A9J4MEM1_A10L7A10/AP E1MEM1_A11R7A11F1MEM1_A12N7A12/BCN J6MEM1_A13T3NC/A13H5MEM1_A14T7NC/A14J3MEM1_BA0M2BA0J1MEM1_BA1N8BA1H1MEM1_BA2M3BA2R3MEM1_DQ0G2DQ6R1MEM1_DQ1H3DQ4P2MEM1_DQ2E3DQ0Table 1-3:Termination Resistor Requirements (Cont’d)Signal NameBoard TerminationOn-Die TerminationReferencesSee the Micron Technology, Inc. DDR3 SDRAM Specification for more information. [Ref 12]Also, see the Spartan-6 FPGA Memory Controller User Guide . [Ref 3]P1MEM1_DQ3F2DQ2L3MEM1_DQ4H7DQ7L1MEM1_DQ5H8DQ5M2MEM1_DQ6F7DQ1M1MEM1_DQ7F8DQ3T2MEM1_DQ8C2DQ11T1MEM1_DQ9C3DQ9U3MEM1_DQ10A2DQ13U1MEM1_DQ11D7DQ8W3MEM1_DQ12A3DQ15W1MEM1_DQ13C8DQ10Y2MEM1_DQ14B8DQ14Y1MEM1_DQ15A7DQ12H2MEM1_WE_B L3WE_B M5MEM1_RAS_B J3RAS_B M4MEM1_CAS_B K3CAS_B L6MEM1_ODT K1ODT K4MEM1_CLK_P J7CLK_P K3MEM1_CLK_N K7CLK_N F2MEM1_CKE K9CKE N3MEM1_LDQS_P F3LDQS_P N1MEM1_LDQS_N G3LDQS_N V2MEM1_UDQS_P C7UDQS_P V1MEM1_UDQS_N B7UDQS_N N4MEM1_LDM E7LDM P3MEM1_UDM D3UDM E3MEM1_RESET_BT2RESET_BTable 1-5:DDR3 Component Memory Connections (Cont’d)U1 FPGA PinSchematic Net NameMemory U42Pin NumberPin Name3. SPI x4 FlashThe Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACTconfiguration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flashthrough a 2.5V bank. The XC6SLX45T-3FGG484 is a master device when accessing anexternal SPI flash memory device.The SP605 SPI interface has two parallel connected configuration options (Figure1-3): anSPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device (U32) and a flashprogramming header (J17). J17 supports a user-defined SPI mezzanine board. The SPIconfiguration source is selected via SPI select jumper J46. For details on configuring theFPGA, see Configuration Options.Figure 1-3:J17 SPI Flash Programming HeaderFigure 1-4:SPI Flash Interface Topology SP605 Hardware User GuideReferencesSee the Winbond Serial Flash Memory Data Sheet for more information. [Ref 13] See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4]Table 1-6:SPI x4 Memory ConnectionsU1 FPGA Pin Schematic Net Name SPI MEM U32SPI HDR J17Pin #Pin NamePin #Pin NameAB2FPGA_PROG_B – –1–T14FPGA_D2_MISO31IO3_HOLD_B 2 –R13FPGA_D1_MISO2_R9IO2_WP_B3 – AA3SPI_CS_B– –4TMS AB20FPGA_MOSI_CSI_B_MISO015DIN 5TDI AA20FPGA_D0_DIN_MISO_MISO18IO1_DOUT6TDO Y20FPGA_CCLK16CLK7TCK– – – –8GND – – – –9VCC3V3J46.2(1)SPIX4_CS_B7CS_B––Notes:1.Not a U1 FPGA pin4. Linear BPI FlashA Numonyx JS28F256P30 Linear Flash memory (U25) on the SP605 (Figure1-5) provides32MB of non-volatile storage that can be used for configuration as well as softwarestorage. The Linear Flash is operated in asynchronous mode.For details on configuring the FPGA, see Configuration Options.Figure 1-5:Linear BPI Flash InterfaceTable 1-7:Linear Flash ConnectionsU1 FPGA Pin Schematic Net Name U25 BPI FLASHPin Number Pin NameN22FLASH_A029A1N20FLASH_A1 25A2M22FLASH_A2 24A3M21FLASH_A3 23A4L19FLASH_A4 22A5K20FLASH_A5 21A6H22FLASH_A6 20A7H21FLASH_A7 19A8L17FLASH_A8 8A9K17FLASH_A9 7A10G22FLASH_A106A11G20FLASH_A115A12K18FLASH_A124A13K19FLASH_A133A14H20FLASH_A142A15J19FLASH_A151A16 SP605 Hardware User GuideE22FLASH_A1655A17E20FLASH_A1718A18F22FLASH_A1817A19F21FLASH_A1916A20H19FLASH_A2011A21H18FLASH_A2110A22F20FLASH_A229A23G19FLASH_A2326A24AA20FPGA_D0_DIN_MISO_MISO134DQ0R13FPGA_D1_MISO236DQ1T14FPGA_D2_MISO339DQ2AA6FLASH_D 3 41D Q3AB6FLASH_D 4 47D Q4Y5FLASH_D 5 49D Q5AB5FLASH_D 6 51D Q6W9FLASH_D 7 53D Q7T7FLASH_D 8 35D Q8U6 FLASH_D 9 37D Q9AB19FLASH_D1040DQ10AA18FLASH_D1142DQ11AB18FLASH_D1248DQ12Y13FLASH_D1350DQ13AA12FLASH_D1452DQ14AB12FLASH_D1554DQ15V13FMC_PWR_GOO D _FLASH_RST_B 44RST_B R20FLASH_WE_B 14WE_B P22FLASH_OE_B 32OE_B P21FLASH_CE_B 30CE_B T19FLASH_ADV_B 46ADV_B T18FLASH_WAIT56WAITTable 1-7:Linear Flash Connections (Cont’d)U1 FPGA PinSchematic Net NameU25 BPI FLASH Pin NumberPin NameFPGA Design Considerations for the Configuration FlashThe SP605 has the P30 BPI flash connected to the FPGA dual use configuration pins and isnot shared. It can be used to configure the FPGA, and then controlled post-configurationvia the FPGA fabric. After FPGA configuration, the FPGA design can disable theconfiguration flash or access the configuration flash to read/write code or data.When the FPGA design does not use the configuration flash, the FPGA design must drivethe FLASH_OE_B pin High in order to disable the configuration flash and put the flashinto a quiescent, low-power state. Otherwise, the flash memory can continue to drive itsarray data onto the data bus causing unnecessary switching noise and powerconsumption.For FPGA designs that access the flash for reading/writing stored code or data, connectthe FPGA design or EDK embedded memory controller (EMC) peripheral to the flashthrough the pins defined in Figure1-5, page14.ReferencesSee the Numonyx StrataFlash Embedded Memory Data Sheet for more information. [Ref14]In addition, see the Spartan-6 FPGA Configuration User Guide for more information. [Ref2]5. System ACE CF and CompactFlash ConnectorThe Xilinx System ACE CompactFlash (CF) configuration controller allows a Type I orType II CompactFlash card to program the FPGA through the JTAG port. Both hardwareand software data can be downloaded through the JTAG port. The System ACE CFcontroller supports up to eight configuration images on a single CompactFlash card. Theconfiguration address switches allow the user to choose which of the eight configurationimages to use.The CompactFlash (CF) card shipped with the board is correctly formatted to enable theSystem ACE CF controller to access the data stored in the card. The System ACE CFcontroller requires a FAT16 file system, with only one reserved sector permitted, and asector-per-cluster size of more than one (UnitSize greater than 512). The FAT16 file systemsupports partitions of up to 2GB. If multiple partitions are used, the System ACE CFdirectory structure must reside in the first partition on the CompactFlash, with thexilinx.sys file located in the root directory. The xilinx.sys file is used by the SystemACE CF controller to define the project directory structure, which consists of one mainfolder containing eight sub-folders used to store the eight ACE files containing theconfiguration images. Only one ACE file should exist within each sub-folder. All foldernames must be compliant to the DOS 8.3 short file name format. This means that the foldernames can be up to eight characters long, and cannot contain the following reservedcharacters: < > " / \ |. This DOS 8.3 file name restriction does not apply to the actual ACEfile names.Other folders and files may also coexist with the System ACE CF project within the FAT16partition. However, the root directory must not contain more than a total of 16 folderand/or file entries, including deleted entries. When ejecting or unplugging theCompactFlash device, it is important to safely stop any read or write access to theCompactFlash device to avoid data corruption. SP605 Hardware User Guide。