C28X eCAN初始化代码

ECanaRegs.CANMD.all = 0x00000ffffL; ECanaRegs.CANOPC.all = 0x00000ffffL; ECanaRegs.CANME.all = 0x00000ffffL;
// mbox0~15 reciever,mailbox16~31 transmiter // Overwrite Protection for mbox0~15 // enble all mailboxs for tx or rx
pMbox = &ECanaMboxes.MBOX0; pLam = &ECanaLAMRegs.LAM0;
for(x=0;x<32;x++) {
pMbox[x].MSGID.all pMbox[x].MSGCTRL.all pMbox[x].MDL.all
= 0x040000000L; = 0x000000000L; = 0x000000000L;
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */ ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
struct ECAN_REGS ECanaShadow;
EALLOW;
/* Enable internal pull-up for the selected CAN pins */ // Pull-ups can be enabled or disabled by the user. // This will enable the pullups for the specified pins. // Comment out other unwanted lines.
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; ECanaShadow.CANMC.bit.SCB = 1; ECanaShadow.CANMC.bit.ABO = 1; ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaShadow.CANBTC.bit.BRPREG = 9; ECanaShadow.CANBTC.bit.TSEG2REG = 1; ECanaShadow.CANBTC.bit.TSEG1REG = 6;
ECanaShadow.CANBTC.bit.SAM = 1; ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3;
/* Configure bit timing parameters for eCANA*/
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ;
// Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA) // GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA)
/* Configure eCAN-A pins using GPIO regs*/ // This specifies which of the possible GPIO pins will be eCAN functional pins.
// Configure GPIO30 for CANRXA operation // Configure GPIO18 for CANRXA operation // Configure GPIO31 for CANTXA operation // Configure GPIO19 for CANTXA operation
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ;
// Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
// Enable pull-up for GPIO31 (CANTXA)
// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (CANTXA)
/* Set qualification for selected CAN pins to asynch only */ // Inputs are synchronized to SYSCLKOUT by default. // This will select asynch (no qualification) for the selected pins.
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
do {
ECanaShadow.CANES.all = ECanaRegs.CANES.all; } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;
// Enable pull-up for GPIO30 (CANRXA)
// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA)
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; ECanaShadow.CANTIOC.bit.TXFUNC = 1; ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; ECanaShadow.CANRIOC.bit.RXFUNC = 1; ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ // HECC mode also enables time-stamping feature
do {
ECanaShadow.CANES.all = ECanaRegs.CANES.all; } while(ECanaShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared..
ECanaRegs.CANMIL.all = 0x000000000L; ECanaRegs.CANMIM.all = 0x0FFFFFFFFL; ECanaRegs.CANGIM.all = 0x000007F01L;
第1页
pMbox[x].MDH.all
C28X eCAN初始化代码 by whicun@hotmail.com = 0x000000000L;
pLam[x].all }
= 0x0FFFFFFFFL;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again // as a matter of precaution.
{ int x; volatile struct MBOX *pMbox; volatile union CANLAM_REG *pLam;
Βιβλιοθήκη Baidu
/* Create a shadow register structure for the CAN control registers. This is needed, since only 32-bit access is allowed to these registers. 16-bit access to these registers could potentially corrupt the register contents or return false data. This is especially true while writing to/reading from a bit (or group of bits) among bits 16 - 31 */
ECanaShadow.CANBTC.all = 0;
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 500 kbps,TQ = 1/CANCLK*(BRPreg + 1),CANCLK=SYSCLKOUT/2, Bit-time = ((TSEG1reg + 1) + (TSEG2reg + 1) + 1)*TQ, */
C28X eCAN初始化代码 by whicun@hotmail.com 一段完整的ECAN实始化代码，在F28335 DSP上运行稳定，不了解eCAN实始化代码的朋友可以参考。 转换请保留此行文字：http://whicun.hellodsp.com http://blog.ednchina.com/whicun/
ECanaRegs.CANME.all = 0x0L;
/* Initialize all bits of 'Master Control Field' to zero */ // Some bits of MSGCTRL register come up in an unknown state. For proper operation, // all bits (including reserved bits) of MSGCTRL must be initialized to zero
enable ECanaRegs.CANGIF0.all= 0x00003FF00L;
// The mailbox interrupt is generated on interrupt line 0 // Mailbox 0~31 interrupt is enabled. // I1EN interrupt disable // MTOM and TCOIM disable // AAIM,WDIM,WUIM,RMLIM,BOIM,EPIM,I0EN and WLIM interrupt // All global interrupts are mapped to the ECAN0INT // Clear Global Interrupt Flag 0