FIR滤波器的实现
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_unsigned.all;
ENTITY FIR is
port(
clk,res,clr,set:in std_logic;
clk_regbt,clk_reg:buffer std_logic;
data_xn:in std_logic_Vector(7 downto 0);
data_yn:out std_logic_vector(18 downto 0));
end FIR;
architecture one of FIRis
TYPE arr1 is array (10 downto 0) of std_logic_vector(7 downto 0);
TYPE arr2 is array (10 downto 0) of std_logic_vector(7 downto 0);
TYPE arr3 is array (10 downto 0) of std_logic_vector(7 downto 0);
SIGNAL reg_xn: arr1;
SIGNAL reg_hn: arr2;
SIGNAL add_xn: arr3;
SIGNAL sum91:std_logic_vector(7 downto 0);
SIGNAL sum92:std_logic_vector(7 downto 0);
SIGNAL sum93:std_logic_vector(7 downto 0);
SIGNAL sum94:std_logic_vector(7 downto 0);
SIGNAL sum101:std_logic_vector(7 downto 0);
SIGNAL sum102:std_logic_vector(7 downto 0);
SIGNAL sum111:std_logic_vector(7 downto 0);
SIGNAL clk_en:std_logic;
SIGNAL counter:integer range 0 to 8;
SIGNAL count_bt:integer range 7 downto 0;
SIGNAL sum:std_logic_vector(18 downto 0);
SIGNAL result:std_logic_vector(18 downto 0);
begin
clk_regbt<=not clk and clk_en;
clk_reg<=not clk and not clk_en;
--总控制器部分
process(clk,res)
begin
if (res='1')then
counter<=0; count_bt<=0;
elsif (clk'event and clk='1') then
if(counter<8)then
clk_en<='1';
counter<=counter+1;
count_bt<=count_bt-1;
else
counter<=0;count_bt<=0;clk_en<='0';
end if;
end if;
end process;
--移数寄存器部分
process(clk_reg,res,clr)
begin
if(res='1' or clr='1')then
for i in 0 to 10 loop
reg_xn(i)<="00000000";
end loop;
elsif(clk_reg'event and clk_reg='0')then
for i in 10 to 1 loop
reg_xn(i)<=reg_xn(i-1);
end loop;
reg_xn(0)<=data_xn;
end if;
end process;
--乘法器部分
process(clk)
begin
if(clk'event and clk='0')then
for i in 0 to 10 loop
if(reg_hn(i)(count_bt)='1')then
add_xn(i)<=reg_xn(i);
else
add_xn(i)<="00000000";
end if;
end loop;
end if;
end process;
--加法树部分
process(clk_regbt,clk_reg,clr,set)
begin
if(clr='1'or set='1')then
sum<=(others=>'0');
data_yn<=(others=>'0');
elsif(clk_reg='1')then
data_yn<=result(18 downto 11)&"00000000000";
sum<=(others=>'0');
elsif(clk_regbt='1')then
sum91<=add_xn(0)+add_xn(1);
sum92<=add_xn(2)+add_xn(3);
sum93<=add_xn(4)+add_xn(5);
sum94<=add_xn(6)+add_xn(7);
sum101<=sum91+sum92;
sum102<=sum93+sum94;
sum111<=sum101+sum102;
sum<=result+sum111;
else
result<=sum(17 downto 0)&'0';
end if;
end process;
end one;