数电外教——SynchronousCounterDesign
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Q2Q1 Q0 0 1 Q2Q1 Q0 0 1 Q2Q1 00 X 01 10 11 X
10 X 11
Note: “Don’t cares” can be placed in cells corresponding to the invalid states of 000, 011, 100, and 110, as indicated by the red Xs.
Step 2. The next state table is developed from the state diagram.
Present State Next State
Q2 0
0 1 1
Q1 0
1 0 1
Q0 1
0 1 1
Q2 0
1 1 0
Q1 1
0 1 0
Q0 0
1 1 1
Step 3. The transition table for the J-K flip-flop is repeated
Design a counter with the irregular binary count sequence shown in the state diagram.
Step 1 • Although there are only four states, a 3-bit counter is required to implement this sequence because the maximum binary count is seven. • Since the required sequence does not include all possible binary states, the invalid states (0, 3, 4, and 6) can be treated as “don’t cares” in the design.
01 X
0 0 11 10 1 0
K2 map
0
11 10 X
11 10 X
K1 map
K0 map
Karnaugh maps for present-state J and K inputs
Step 5: Logic Expressions for Flip-Flop From the Karnaugh maps, Inputs
State diagram for a 3-bit Gray code counter.
Step 2: Next-State Table
The next state is the state that the counter goes to from its present state upon application of a clock pulse
Q2 0 0 0 1 1 1 1 0 Q1 0 1 1 1 1 0 0 0 Q0 1 1 0 0 1 1 0 0 J0 map
QN: present state QN+1: next state X: “don’t care”
Present State
Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 1 1 0 0 Q0 0 1 1 0 0 1 1 0
Q2Q1
Q0 00 01
0
1
X 0
X 1 10 11 X 0
11 10
X 1
K0 map
Karnaugh maps for present-state J and K inputs Q Q 0 1 Q Q Q 0 1 Q Q Q 0 1 Q
0 0 0 2 1 2 1 2 1
00 0 01 10 11 X 11 10 X Q2Q1 Q0 00 01 10 11 0
OUTPUT TRANSITIONS QN 0 0 1 1 QN+1 0 1 0 1 FLIP-FLOP INPUTS J 0 1 X X K X X 1 0
QN: present state QN+1: next state X: “don’t care”
J-K Flip-Flop Chapter 5.3.3
[Chapter 6.3]
Design of Synchronous Counters
Step 1: State Diagram
A counter is first described by a state diagram, which shows the progression of states through which the counter advances as it is clocked.
Examples of the mapping procedure
OUTPUT TRANSITIONS
QN 0 0 1 1 QN+1 0 1 0 1
FLIP-FLOP INPUTS
Q2Q1
J 0 1 X X K X X 1 0
Q0
0
1
00 1 01
11 10
X
0 X
1 X 11 10 0 X
Next StLeabharlann Baidute
RUN SIMULATION
Note: When all cells in a map are grouped, the expression is simply equal to 1.
Step 5. The expression for each J and K input taken from the maps
Step 6. Implement the counter
X X 1 X
X 1 X 0 0 X
01 X
11 10
X 1 10 X 0 11
K2 map
11 10 X
K1 map
K0 map
Step 5. Group the 1’s, taking advantage of as many of the “don’t care” states as possible for maximum simplification.
0 X
00 0 01 10 11 11 10 Q2Q1 Q0
1
00 1 01 10 11 11 10 Q2Q1 Q0 00
11 10
X
1 0
X X
X X 0
0
0 X 1 X
X
1
0
1
0 X
J0 map
J2 map
J1 map
0
1
X X X X
00 X 01 0 10 11
X 0 1 X
X 0 1 0 1 X
OUTPUT TRANSITIONS QN 0 0 1 1 QN+1 0 1 0 1 FLIP-FLOP INPUTS J 0 1 X X K X X 1 0
QN: present state QN+1: next state X: “don’t care”
Step 4. The J and K inputs are plotted on the present-state Karnaugh maps.
obtain the expressions for the J and K inputs of each flip-flop.
Step 6: Counter Implementation
RUN SIMULATION
Summary
1. Specify the counter sequence and draw a state diagram 2. Derive a next-state table from the state diagram 3. Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop. 4. Transfer the J and K states from the transition table to the Karnaugh maps. There is a Karnaugh map for each input of each flip-flop. 5. Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input. 6. Implement the expressions with combinatorial logic, and combine with flip-flops to create the counter.
Step 4: Karnaugh Maps
Karnaugh maps (K-maps) can be used to determine the logic required for the J and K inputs of each flip-flop in the counter. There is a Karnaugh map for the J input and a Karnaugh map for the K input of each flip-flop. In this procedure, each cell represents one of the present states in the counter sequence.
Present State Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 1 1 0 0 Q0 0 1 1 0 0 1 1 0 Q2 0 0 0 1 1 1 1 0 Next State Q1 0 1 1 1 1 0 0 0 Q0 1 1 0 0 1 1 0 0
Step 3: Flip-flop transition table
• The transition table for the J-K flip-flop is shown. All possible output transitions are listed by showing the Q output of the flipflop going from present states to next states. • QN is the present state of the flipflop (before the clock pulse) and QN+1 is the next state (after the clock pulse). • For each transition, the J and K inputs that will cause the transition to occur are listed. • The Xs indicate “don’t care condition (the input can be either a 1 or a 0).
Q0
0
1
0 X
00 X 01 10 11 11 10 Q2Q1 Q0
1
1 X
X X
X X X 1
J1 map
X X 01 1 X
00
11 10
X X X X
J0 map
X
1
11 10 Q2Q1 Q0 00
Q2Q1
Q0 00 01 10 11
J2 map
0
0
1
0
1
X X X X
00 X 01 1 10 11 X 11 10 X
10 X 11
Note: “Don’t cares” can be placed in cells corresponding to the invalid states of 000, 011, 100, and 110, as indicated by the red Xs.
Step 2. The next state table is developed from the state diagram.
Present State Next State
Q2 0
0 1 1
Q1 0
1 0 1
Q0 1
0 1 1
Q2 0
1 1 0
Q1 1
0 1 0
Q0 0
1 1 1
Step 3. The transition table for the J-K flip-flop is repeated
Design a counter with the irregular binary count sequence shown in the state diagram.
Step 1 • Although there are only four states, a 3-bit counter is required to implement this sequence because the maximum binary count is seven. • Since the required sequence does not include all possible binary states, the invalid states (0, 3, 4, and 6) can be treated as “don’t cares” in the design.
01 X
0 0 11 10 1 0
K2 map
0
11 10 X
11 10 X
K1 map
K0 map
Karnaugh maps for present-state J and K inputs
Step 5: Logic Expressions for Flip-Flop From the Karnaugh maps, Inputs
State diagram for a 3-bit Gray code counter.
Step 2: Next-State Table
The next state is the state that the counter goes to from its present state upon application of a clock pulse
Q2 0 0 0 1 1 1 1 0 Q1 0 1 1 1 1 0 0 0 Q0 1 1 0 0 1 1 0 0 J0 map
QN: present state QN+1: next state X: “don’t care”
Present State
Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 1 1 0 0 Q0 0 1 1 0 0 1 1 0
Q2Q1
Q0 00 01
0
1
X 0
X 1 10 11 X 0
11 10
X 1
K0 map
Karnaugh maps for present-state J and K inputs Q Q 0 1 Q Q Q 0 1 Q Q Q 0 1 Q
0 0 0 2 1 2 1 2 1
00 0 01 10 11 X 11 10 X Q2Q1 Q0 00 01 10 11 0
OUTPUT TRANSITIONS QN 0 0 1 1 QN+1 0 1 0 1 FLIP-FLOP INPUTS J 0 1 X X K X X 1 0
QN: present state QN+1: next state X: “don’t care”
J-K Flip-Flop Chapter 5.3.3
[Chapter 6.3]
Design of Synchronous Counters
Step 1: State Diagram
A counter is first described by a state diagram, which shows the progression of states through which the counter advances as it is clocked.
Examples of the mapping procedure
OUTPUT TRANSITIONS
QN 0 0 1 1 QN+1 0 1 0 1
FLIP-FLOP INPUTS
Q2Q1
J 0 1 X X K X X 1 0
Q0
0
1
00 1 01
11 10
X
0 X
1 X 11 10 0 X
Next StLeabharlann Baidute
RUN SIMULATION
Note: When all cells in a map are grouped, the expression is simply equal to 1.
Step 5. The expression for each J and K input taken from the maps
Step 6. Implement the counter
X X 1 X
X 1 X 0 0 X
01 X
11 10
X 1 10 X 0 11
K2 map
11 10 X
K1 map
K0 map
Step 5. Group the 1’s, taking advantage of as many of the “don’t care” states as possible for maximum simplification.
0 X
00 0 01 10 11 11 10 Q2Q1 Q0
1
00 1 01 10 11 11 10 Q2Q1 Q0 00
11 10
X
1 0
X X
X X 0
0
0 X 1 X
X
1
0
1
0 X
J0 map
J2 map
J1 map
0
1
X X X X
00 X 01 0 10 11
X 0 1 X
X 0 1 0 1 X
OUTPUT TRANSITIONS QN 0 0 1 1 QN+1 0 1 0 1 FLIP-FLOP INPUTS J 0 1 X X K X X 1 0
QN: present state QN+1: next state X: “don’t care”
Step 4. The J and K inputs are plotted on the present-state Karnaugh maps.
obtain the expressions for the J and K inputs of each flip-flop.
Step 6: Counter Implementation
RUN SIMULATION
Summary
1. Specify the counter sequence and draw a state diagram 2. Derive a next-state table from the state diagram 3. Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop. 4. Transfer the J and K states from the transition table to the Karnaugh maps. There is a Karnaugh map for each input of each flip-flop. 5. Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input. 6. Implement the expressions with combinatorial logic, and combine with flip-flops to create the counter.
Step 4: Karnaugh Maps
Karnaugh maps (K-maps) can be used to determine the logic required for the J and K inputs of each flip-flop in the counter. There is a Karnaugh map for the J input and a Karnaugh map for the K input of each flip-flop. In this procedure, each cell represents one of the present states in the counter sequence.
Present State Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 1 1 0 0 Q0 0 1 1 0 0 1 1 0 Q2 0 0 0 1 1 1 1 0 Next State Q1 0 1 1 1 1 0 0 0 Q0 1 1 0 0 1 1 0 0
Step 3: Flip-flop transition table
• The transition table for the J-K flip-flop is shown. All possible output transitions are listed by showing the Q output of the flipflop going from present states to next states. • QN is the present state of the flipflop (before the clock pulse) and QN+1 is the next state (after the clock pulse). • For each transition, the J and K inputs that will cause the transition to occur are listed. • The Xs indicate “don’t care condition (the input can be either a 1 or a 0).
Q0
0
1
0 X
00 X 01 10 11 11 10 Q2Q1 Q0
1
1 X
X X
X X X 1
J1 map
X X 01 1 X
00
11 10
X X X X
J0 map
X
1
11 10 Q2Q1 Q0 00
Q2Q1
Q0 00 01 10 11
J2 map
0
0
1
0
1
X X X X
00 X 01 1 10 11 X 11 10 X