计算机组成原理实验5
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实验五微程序控制器的设计及实现
Rom64_40.v
module rom64_40 (
addr,
q);
input [5:0] addr;
output [39:0] q;
reg [39:0] q;
always @(addr[5] or addr[4] or addr[3] or addr[2] or addr[1] or addr[0]) begin
case({addr[5],addr[4],addr[3],addr[2],addr[1],addr[0]})
6'h00 : q <= 40'h0c00000041;
6'h01 : q <= 40'h00000410a0;
6'h02 : q <= 40'h4010034002;
6'h03 : q <= 40'h4010028002;
6'h04 : q <= 40'h4020024004;
6'h05 : q <= 40'h4010028004;
6'h06 : q <= 40'h6c00020000;
6'h07 : q <= 40'h4400020006;
6'h08 : q <= 40'h501002080a;
6'h09 : q <= 40'h4410020808;
6'h0a : q <= 40'h641002080c;
6'h0b : q <= 40'h4410020815;
6'h0c : q <= 40'h7810020800;
6'h0d : q <= 40'h401002a01a;
6'h0e : q <= 40'h0020000c01;
6'h0f : q <= 40'h4410020832;
6'h10 : q <= 40'h000e810401;
6'h11 : q <= 40'h0180020014;
6'h12 : q <= 40'h0000000401;
6'h13 : q <= 40'h8000000401;
6'h14 : q <= 40'h0010002001;
6'h15 : q <= 40'h5010020816;
6'h16 : q <= 40'h440a7a0017;
6'h17 : q <= 40'h44099a0018;
6'h18 : q <= 40'h440eca0019;
6'h19 : q <= 40'h440f8a0000;
6'h1a : q <= 40'h401003401b;
6'h1b : q <= 40'h401003501c;
6'h1c : q <= 40'h401003501d;
6'h1d : q <= 40'h401002a01f;
6'h1e : q <= 40'h0000000000;
6'h1f : q <= 40'h4020025030;
6'h20 : q <= 40'h0000000000;
6'h21 : q <= 40'h000a780c01;
6'h22 : q <= 40'h0009980c01;
6'h23 : q <= 40'h000ec80c01;
6'h24 : q <= 40'h0008180c01;
6'h25 : q <= 40'h000e80800e;
6'h26 : q <= 40'h000fc08010;
6'h27 : q <= 40'h0000000112;
6'h28 : q <= 40'h0000000212;
6'h29 : q <= 40'h000fc02401;
6'h2a : q <= 40'h000e800401;
6'h2b : q <= 40'h0040002401;
6'h2c : q <= 40'h010*******;
6'h2d : q <= 40'h020*******;
6'h2e : q <= 40'h0000020401;
6'h2f : q <= 40'h0000000000;
6'h30 : q <= 40'h4020025031;
6'h31 : q <= 40'h4020020000;
6'h32 : q <= 40'h5010020833;
6'h33 : q <= 40'h64100c0834;
6'h34 : q <= 40'h7810020835;
6'h35 : q <= 40'h4c1002a036;
6'h36 : q <= 40'h400e834037;
6'h37 : q <= 40'h440e835038;
6'h38 : q <= 40'h480e835039;
6'h39 : q <= 40'h4c0e83503a;
6'h3a : q <= 40'h4c1002803b;
6'h3b : q <= 40'h702002483c;
6'h3c : q <= 40'h6c2002483d;
6'h3d : q <= 40'h582002483e;
6'h3e : q <= 40'h4420024800;
6'h3f : q <= 40'h0000000000;
default : begin end endcase
end
endmodule
rom64_40.vt
`timescale 1 ns/ 1 ps module rom64_40_vlg_tst(); reg [5:0] addr;
wire [39:0] q;
rom64_40 i1 (
.addr(addr),
.q(q)
);
integer i;
initial
begin
for(i=0;i<64;i=i+1)
begin
#50 addr=i;
end
end
endmodule
rom64_40.bsf
rom64_40.bsf仿真测试