VHDL程序设计题
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VHDL程序设计题
四、编程题(共50分)
1、请补全以下二选一VHDL程序(本题10分)
Entity mux is
port(d0,d1,sel:in bit;
q:out BIT ); (2)
end mux;
architecture connect of MUX is (4)
signal tmp1, TMP2 ,tmp3:bit; (6)
begin
cale:
block
begin
tmp1<=d0 and sel;
tmp2<=d1 and (not sel)
tmp3<= tmp1 and tmp2;
q <= tmp3; (8)
end block cale;
end CONNECT ; (10)
2、编写一个2输入与门的VHDL程序,请写出库、程序包、实体、构造体相关语句,将端口定义为标准逻辑型数据结构(本题10分)
&y
LIBRARY IEEE;
USE (2)
ENTITY nand2 IS
PORT (a,b:IN STD_LOGIC; (4)
y:OUT STD_LOGIC); (6)
END nand2;
ARCHITECTURE nand2_1 OF nand2 IS (8)
BEGIN
y <= a NAND b; --与y <=NOT( a AND b);等价(10)
END nand2_1;
3、根据下表填写完成一个3-8线译码器的VHDL程序(16分)。
LIBRARY IEEE;
USE decoder_3_to_8 IS
PORT (a,b,c,g1,g2a,g2b:IN STD_LOGIC;
y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); (2)END decoder_3_to_8;
ARCHITECTURE rtl OF decoder_3_to_8 IS
SIGNAL indata:STD_LOGIC_VECTOR (2 DOWNTO 0); (4)BEGIN
indata <= c & b & a;
(6)
PROCESS (indata,g1,g2a,g2b)
BEGIN
IF (g1 = '1' AND g2a = '0' AND g2b = '0' ) THEN
(8)
CASE indata IS
WHEN "000"=> y <= "";
WHEN "001" => y <= "";
WHEN "010" => y <= ""; (10)
WHEN "011" => y <= "";
WHEN "100" => y <= "";
WHEN "101" => y <= "";
WHEN "110" => y <= ""; (12) WHEN "111" => y <= "01111111";
WHEN OTHERS=> y <= "XXXXXXXX";
END CASE;
ELSE
y <= ""; (14)
END IF;
END PROCESS; (16)
END rtl;
4、三态门电原理图如右图所示,真值表如左图所示,请完成其VHDL程序构造体部分。
(本题14分)
LIBRARY IEEE;
USE tri_gate IS
PORT(din,en:IN STD_LOGIC;
dout : OUT STD_LOGIC);
END tri_gate ;
ARCHITECTURE zas OF tri_gate IS
BEGIN
PROCESS (din,en)
BEGIN
IF (en=‘1') THEN dout <= din;
ELSE dout <= ‘Z’;
END IF;
E ND PROCESS ;
END zas ;
四、编程题(共50分)
1、根据一下四选一程序的结构体部分,完成实体程序部分(本题8分)entity MUX4 is
p ort( (2)
s: in std_logic_vector(1 downto 0); (4)
d: in std_logic_vector(3 downto 0); (6)
y: out std_logic (8)
);
end MUX4;
architecture behave of MUX4 is
begin
process(s)
b egin
i f (s="00") then
y<=d(0);
e lsi
f (s="01") then
y<=d(1);
e lsi
f (s="10") then
y<=d(2);
e lsi
f (s="11") then
y<=d(3);
e lse
null;
e nd if;
end process;
end behave;
2、编写一个数值比较器VHDL程序的进程(不必写整个结构框架),要求使能信号g 低电平时比较器开始工作,输入信号p = q,输出equ为‘0’,否则为‘1’。(本题10分)process(p,q) (2)
b egin
if g='0' then (4)
if p = q then
equ <= '0'; (6)
else
equ <= '1'; (8)
end if;
else
equ <= '1'; (10)
end if;
e nd process;
3、填写完成一个8-3线编码器的VHDL程序(16分)。
Library ieee;
use eight_tri is
p ort(
b: in std_logic_vector(7 downto 0); (2)
en: in std_logic;
y: out std_logic_vector(2 downto 0) (4));
end eight_tri;
architecture a of eight_tri is (6)signal sel: std_logic_vector(8 downto 0);
b egin
s el<=en & b; (8)