Xilinx和Altera FPGAs的电源管理解决方案

ODUC
DATA SHEETS
APP REPORT
EVALUATION
T SBiblioteka Baidu
AMPLE
MODULE
ሞhttp://focus.ti.com.cn/cn/docs/prod/folders/print/tps74401. htmlฉइൽᄣԨĂຕ਍՗ĂᆌᆩԒߢࢅೠࠚఇ႙
࠲॰Ⴀీǖ • ੗Պ‫෉ײ‬ഔ‫ۯ‬/߶ጷ ࠀీ • ๼෇‫ۉ‬უ݄࿆:0.9V~5.5V • ೋዃ‫ۉ‬უ‫ྷݔ‬:2.375V~5.25V • ट‫گ‬VINVDO:195mV max@3A • ट‫گ‬VBIASVDO:1.62V max@3A • ๼‫ۉ؜‬უ:0.8~3.3V • ‫޶ټ‬ሜ/၍ୟ/࿒‫ڦ܈‬৛ඓ‫܈‬1% • ‫ܔ‬ඪᅪ๼‫ۉ؜‬ඹईኁ࿮๼‫ۉ؜‬ඹ‫ۼ‬࿘ۨ • ԍኤፌၭ/ፌ‫ୁۉ ٷ‬၌዆
GND
FB
R2
Startup Soft-Start
Track Soft-Start
COUT
VPG VOUT
Optional
PR S
‫ڤ‬ዝᅏഗ 2007౎‫ڼ‬2ल‫܈‬
XilinxࢅAltera FPGAs‫ۉڦ‬ᇸ࠶૙঴ਦ‫ݛ‬ӄ
PR S
३࣐੦዆ഗ
4.5V~15V๼෇,ཞօBuchk DC/DC੦዆ഗ TPS40190
ᆫ‫ۅ‬: • ‫گ‬ሯำߛ‫ୁۉ‬၍Ⴀ঴ਦ‫ݛ‬ӄ • Բ঍࣑঴ਦ‫ݛ‬ӄ߸ณ‫ڦ‬ӱ੣क़ • Բ঍࣑঴ਦ‫ݛ‬ӄ߸ณ‫ڦ‬ևॲ
ᆌᆩ: • Altera Cyclone II, Stratix II, Stratix II GX, Stratix III • Xilinx Spartan-3ׂ೗ፃ, Virtex-5 • Core ࢅ IOࠀ୲ցߴ • PLL ࢅ VCOࠀ୲ցߴ
࠲॰Ⴀీ
ᆌᆩ • Altera Cyclone II, Stratix II, Stratix II GX, Stratix III • Xilinx Spartan-3ׂ೗ፃ, Virtex-5 • Core ࢅ IO ࠀ୲ցߴ
• 4.5V~52V๼෇‫ۉ‬უ
VIN
• ‫ټ‬മၠց‫ۉڦ׋‬უ੦዆ఇ๕
IN3
FB1
EN1
SS1 EN2
3A Buck 2
IS2
SW2 FB2
SS2 EN1
300 mA LDO
OUT3 FB3
SS3
AGND
DGND
DGND
DGND
10 nF
0.033 0.033 Q2 15 μH D2
VCCINT
+
1.2 V @ 3 A
100 pF
Q1 5 μH D1 61.9 k
VCCO
ᆫ‫ۅ‬ǖ • ၭ႙‫ڇ‬ႊೌ঴ਦ‫ݛ‬ӄ • ଳऄ‫ࢫံڦ‬ຩႾ
FPGAᆌᆩǖ • Altera Cyclonellׂ೗ॆፃ • Xilinx Spartan-3ׂ೗ॆፃ
5 V_Input 100 pF
VCCAUX 1.5 nF
1.5 nF
TPS75003
IN1 3 A IS1
IN2 Buck 1 SW1
TPS40200
• 700mV‫ۉ‬უ֖੊ǖ1%‫ڦ‬৛‫܈‬ • ాև‫گ‬უ໮ۨ • ੗Պ‫ײ‬ೕ୲ǖ35KHz዁500KHz • ੗Պ‫ୁࡗײ‬ԍࢺ
1 RC
VIN 8
2 SS/SD
ISNS 7
RSENSE
• ೕ୲ཞօ • Կ࣍෉ഔ‫ۯ‬ • ण‫ׯ‬ൻ‫ۯ‬
࠲॰Ⴀీ:
ᆌᆩ: • Altera Cyclone II, Stratix II, Stratix II GX, Stratix III • Xilinx Spartan-3ׂ೗ፃ, Virtex-5 • Core ࢅ IO ࠀ୲ցߴ
• ๼෇߾ፕ‫ۉ‬უ‫ྷݔ‬:4.5V~15V
VDD
• ๼‫ۉ؜‬უ‫گ‬዁0.591V, ժ൐ᆶ+1%‫੊֖ڦ‬৛‫܈‬ • ߛၳ୲‫ڦ‬ཞօၯኟ
XilinxࢅAltera FPGAs‫ۉڦ‬ᇸ࠶૙঴ਦ‫ݛ‬ӄ
‫ڤ‬ዝᅏഗ 2007౎‫ڼ‬2ल‫܈‬
PR S
‫گ‬฿ኈۙবഗ
ߛႠీพೕLDOׂ೗ TPS791/792/793/794/795/796/786xx
ODUC
DATA SHEETS
APP REPORT
EVALUATION
T S
AMPLE
‫ۉ‬ᇸ࠶૙‫ڦ‬ዷᄻǖ Power.ti.com Altera FPGA‫ۉڦ‬ᇸ࠶૙‫ڦ‬঴ਦ‫ݛ‬ӄǖ http://focus.ti.com.cn/cn/analog/docs/gencontent.tsp?fa milyId=64&genContentId=1052 Xilinx FPGA ‫ݛ୲ࠀڦ‬ӄǖ http://focus.ti.com.cn/cn/analog/docs/gencontent.tsp?fa milyId=64&genContentId=1069 ‫ۉ‬ᇸ࠶૙຤ೝೠॏe-Storeఇ੷ǖ www.ti.com/home_b_estore ‫ۉ‬ᇸ࠶૙FPGAरຍኧ‫ۉڦ׼‬ጱᆰॲǖ Fpgasupport@list.ti.com
PR S
4.5V~52V๼෇Lj‫گ‬ኍຕBuck੦዆ഗ TPS40200
• ෉ഔ‫ࠃ༵ۯ‬ೝࣂĂᅟ੦዆‫ื༵୲ࠀڦ‬ • ०‫ڇ‬ದዃ-ፌၭࣅકቛևॲ
ODUC
DATA SHEETS
APP REPORT
EVALUATION
T S
AMPLE
MODULE
ሞhttp://focus.ti.com.cn/cn/docs/prod/folders/print/tps40200. htmlฉइൽᄣԨĂຕ਍՗ĂᆌᆩԒߢࢅೠࠚఇ႙
ᆫ‫ۅ‬: • ྺ௺ߌఇెࠀీׂิ‫گ‬ሯำࠀࡼ • ๑ᆩ߸ၭ‫ڦ‬Ă߸Սᅓ‫ڦ‬༩዆‫ۉ‬ඹ
ᆌᆩǖ • Altera Stratix ư GXLjMAXư • Xilinx Virtex5Lj CoolRunnerư • ‫گ‬ሯำRFᆌᆩ • PLLࢅVCOࠀ୲ցߴ
Typical Device Specifications
MODULE
ሞhttp://focus.ti.com.cn/cn/docs/prod/folders/print/ PARTnumber.htmlฉइ‫ڥ‬ᄣԨĂຕ਍՗ĂᆌᆩԒߢࢅೠࠚఇ႙ă DŽᆩTPS791/792/793/794/795/796/786xx༺࣑PARTnumberDž
࠲॰Ⴀీǖ • ๼෇‫ۉ‬უ‫ྷݔ‬ǖ2.7V~5.5V • Ⴊኟ๼‫ۉ؜‬უǖ1.8V~4.75Vࢅ੗ۙব‫ڦ‬1.2V~5.0V • ۨ‫ܮ‬๼‫ۉ؜‬ୟǖ100mA~1.5A • ༩዆࿘ۨ๼‫ۉ؜‬ඹ • 32_VRMS๼‫؜‬ሯำLj100Hz~100KHz • ੺໏ഔ‫้ۯ‬क़DŽ50̂sDž • ޶ሜ/၍ୟ/࿒‫܈‬৛ඓ‫܈‬:2% • ࢔ߛ‫ڦ‬PSRR:70dB@1KHzࢅ70dB@10KHz
CoolRunner®, XPLA3 CoolRunner-II
Xilinx
Spartan Family • IIE, /XL • 3, 3A, 3E
Virtex®, E, EM Virtex-II, Pro Virtex-4 Virtex-5
• ࠽‫ڦݘ‬ፇࢇԈઔLDO,੦዆ഗLjण‫ׯ‬FETገ࣑ഗࢅఇ੷ă • FPGA֖੊ยऺLjࠀ୲ยऺ‫ޜ‬ခLjยऺ෉ॲ • ჺ༪ࣷLjྪஏ࠽խࢅᆌᆩԴऻ • ੺໏‫د‬๼ᄣԨLjೠࠚఇ੷ • Ԩ‫ں‬ᆌᆩኧ‫׼‬ • ݀ႜअӵ
Device TPS79101
IOUT 100 mA
TPS79201
100 mA
TPS79301
200 mA
TPS79401
250 mA
TPS79501
500 mA
TPS79601
1.0 A
VDO (mV) 38 38 77 145 105 220
TPS78601
VIN 1 μF
1.5 A
340
TPS79501
‫ڤ‬ዝᅏഗ࠽‫ݘ‬ፇࢇ‫ߛڦ‬Ⴀీ‫ۉ‬ᇸ࠶૙ׂ೗ĂԨ‫ں‬रຍኧ‫ీࢅ׼‬०‫ڇ‬ ยऺ‫߾ڦ‬ਏ‫ࠃ༵ేߴీݘ࠽ڦ‬փཞ‫ڦ‬FPGAยऺLjඟేሞ๨‫ׇ‬ዐཨ෇ ߸‫้ڦܠ‬क़ă
ኄ߲ዷ༶ࣹणब߲‫ظ‬ႎยԢᅜඟ໱்ࢅFPGAࢅCPLDยԢ߾ፕഐઠ ‫ڟٳ‬ፌᆫࣅႠీLjԲසׂጲXilinxࢅAltera‫ׂڦ‬೗ăTIፌႎ‫ۉڦ‬ᇸ࠶ ૙ण‫ׯ‬ႊೌࢅ֖੊ยऺ༵ߛକ‫ۉ‬ᇸ‫ڦ‬ၳ୲Ljཞ้०ࣅକยऺă
TPS40190
• ෙ߲੗჋ስ‫܌ڦ‬ୟ‫܋‬ • ٗ‫܌‬ୟ࣍ৣዐీტ໏࣬ް • ྺNࠏ‫ڢ‬MOSFET༵ࠃ‫ڦ‬ण‫ׯ‬ጲਉघ૤ഗ • ాև෉ഔ‫ۯ‬
1 ENABLE HDRV 10
Shutdown
2 FB
SW 9
3 COMP BOOT 8
VOUT
4 VDD
LDRV 7
5 GND
BP5 6
ᆫ‫ۅ‬: • ߛႠీ,‫ׯگ‬Ԩ঴ਦ‫ݛ‬ӄ • ሎႹ‫ڇ‬๼෇ࠀ୲‫ݛ‬ӄ,փ‫܀‬૬‫ۉ‬ᇸࠃᆌႴᄲൻ‫ۯ‬੦዆ഗ • ༵ࠃࠀ୲ࠃᆌଳऄႠܸփሺे‫ۉ‬ୟްሗ‫܈‬ • ߸ณ‫ڦ‬કቛևॲ,०ࣅยऺ • ፌၭࣅ঍࣑໦฿,߀৊ၳ୲
+
3.3 V @ 3 A 100 pF
36.5 k 61.9 k
VCCAUX 10 μF2.5 V @ 300 mA
15.4 k
FPGAׂ೗‫ۉڦ‬ᇸ࠶૙঴ਦ‫ݛ‬ӄ
ే‫ڦ‬FPGAࢅCPLDยऺ‫ۉڦ‬ᇸ࠶૙঴ਦ‫ݛ‬ӄ
Altera
Max® Max II
Cyclone® Cyclone II
Stratix®, GX Stratix II, GX Stratix III
TM
Technology for Innovators
TM
ఇెׂ೗ణ୤
ాඹ
‫گ‬฿ኈۙኝഗ
ߛႠీRFLDOs
3
‫෉ټ‬ഔ‫߶ࢅۯ‬ጷࠀీ‫ڦ‬
‫گ‬฿ኈ၍Ⴀۙኝഗ
3
օ३੦዆ഗ
ཞօBuck DC/DC੦዆ഗ
4
੻‫ټ‬๼෇,‫࠶گ‬গ
Buck ੦዆ഗ
4
ण‫ׯ‬FETገ࣑ഗ
3~6‫ޚ‬๼෇,
3Ҿ DC/DC੦዆ഗ
ၭࡀఇ०‫ڇ‬ยऺ
9
12Vin‫୲ࠀگ‬,‫ׯ‬Ԩፌᆫࣅ
9
12Vinዐ‫ࡼࠀڪ‬,
०‫ڇ‬ยऺ
10
12Vinߛࠀࡼ,ߛၳ୲
10
5Vin‫ܠ‬ዘFPGAยऺ‫ڦ‬
ްሗဣཥ
11
XilinxࢅAltera FPGAs ‫ۉڦ‬ᇸ࠶૙঴ਦ‫ݛ‬ӄ
2007౎‫ڼ‬2ल‫܈‬
PR S
SpartanࢅCyclone‫ڇڦ‬ႊೌ঴ਦ‫ݛ‬ӄ TPS75003
Typical Device Specifications
Device TPS74201
IOUT (A) 1.5
TPS74301
1.5
TPS74401
3.0
VDO (mV) 55 55 110
TPS74401
VDD
IN
PG
CIN
EN
1 μF
BIAS
R3 OUT
VBIAS
SS
R1
CBIAS
1 μF
CSS
ODUC
DATA SHEETS
APP REPORT
EVALUATION
T S
AMPLE
MODULE
ీሞhttp://focus.ti.com.cn/cn/docs/prod/folders/print/tps75003.htmlइ‫ڥ‬ᄣ೗,ຕ਍՗,ᆌᆩ Ԓߢ,ೠࠚఇ੷ࢅ෉ॲ߾ਏ.
ዷᄲႠీ: • ଇ߲ၳ୲ྺ95%‫ڦ‬3-A buck੦዆ഗࢅᅃ߲300ࡹҾ‫ڦ‬LDO • ๼‫ۉ؜‬უ੗ۙ዁1.2v‫ڦ‬buck‫ۉ‬ୟࢅ1.0V‫ڦ‬LDO • ๼෇‫ۉ‬უ‫ྷݔ‬:2.2~6.5V • ߲߳ࠃᆌ‫܀‬૬੗ᆩ • Ԉጎǖ‫֨گ‬௬4.5mm*3.5mmOFN
5
4.5~20‫ޚ‬๼෇,
6Ҿ DC/DCገ࣑ഗ
5
‫୲ࠀگ‬ण‫ׯ‬FET੦዆ഗ
MSOP-10ዐ‫ڦ‬
1.2Ҿօ३ገ࣑ഗ
6
1ኍEasyScaleথ੨‫ڦ‬
ມཚ‫ڢ‬օ३ገ࣑ഗ
6
PTHࠀ୲ఇ੷
T2 ‫پܾڼ‬PTH
णዐሜࢁఇ੷
7
ࠀ୲ցߴᅼႾഗ
8ཚ‫୲ࠀڢ‬ցߴᅼႾഗ
ࢅ॔੦ഗ
8
֖੊ยऺ
5Vin‫୲ࠀگ‬,
• ߛ዁25-A‫ܔߴࠃ୲ࠀڦ‬EPS40190‫ۼ‬੗ᆩ • ሞ‫ٱ‬ဃ࣍ৣူፌၭࣅࠀ୲ࡼො,‫ٱ‬ဃ঴‫ࢫأ‬ጲ‫ۯ‬ዘഔ
ODUC
DATA SHEETS
APP REPORT
EVALUATION
T S
AMPLE
MODULE
ሞhttp://focus.ti.com.cn/cn/docs/prod/folders/print/tps40190. htmlฉइൽᄣԨĂຕ਍՗ĂᆌᆩԒߢࢅೠࠚఇ႙
IN
OUT
EN FB
GND
EN /EN

R1
R2
Packages SOT23 SOT23
SOT 23, WCSP MSOP8, SOT223
SOT223 SOT 223, DDPAK,
SON (2.8 V) SOT223, DDPAK
VOUT
C1
1 μF
‫෉ټ‬ഔ‫߶ࢅۯ‬ጷࠀీ‫ڦ‬ट‫گ‬฿ኈ၍Ⴀۙኝഗ TPS744xx