RK3066解决方案手册

RK3066Datasheet brief
Revision1.0
Feb.2012
Revision History Date Revision Description
2011-10-300.0Initial Release
2012-02-15 1.0Add package information
TABLE OF CONTENT
Revision History (2)
TABLE OF CONTENT (3)
Chapter1Introduction (4)
1.1Overview (4)
1.2Features (4)
1.3Block Diagram (15)
Chapter2Package information (16)
2.1Dimension (16)
2.2Ball Map (18)
2.3Pin Number Order (21)
2.4RK3066power/ground IO descriptions (26)
2.5RK3066function IO descriptions (28)
Chapter3Electrical Specification (40)
3.1Absolute Maximum Ratings (40)
3.2Recommended Operating Conditions (41)
3.3DC Characteristics (42)
3.4Electrical Characteristics for General IO (43)
3.5Electrical Characteristics for PLL (43)
3.6Electrical Characteristics for SAR-ADC (44)
3.7Electrical Characteristics for TS-ADC (44)
3.8Electrical Characteristics for USB OTG/Host2.0Interface (44)
3.9Electrical Characteristics for HDMI (45)
3.10Electrical Characteristics for DDR IO (45)
3.11Electrical Characteristics for eFuse (46)
CHAPTER1Introduction
1.1Overview
RK3066is a low power,high performance processor solution for mobile phones, personal mobile internet device and other digital multimedia applications,and integrates dual-core Cortex-A9with separately NEON and FPU coprocessor.
Many embedded powerful hardware engines provide optimized performance for high-end application.RK3066supports almost full-format video decoder by1080p@60fps,also support H.264/MVC/VP8encoder by1080p@30fps,high-quality JPEG encoder/decoder and special image preprocessor and postprocessor.
Embedded3D GPU makes RK3066completely compatible with OpenGL ES2.0and1.1, OpenVG1.1.Even support high quality3D video replay.Special2D hardware engine with MMU will maximize display performance.
RK3066has high-performance external memory interface(DDR3/LVDDR3/LPDDR/ LPDDR2)capable of sustaining demanding memory bandwidths,also provides a complete set of peripheral interface to support very flexible applications.
This document will provide guideline on how to use RK3066correctly and efficiently.
In them,the chapter1and chapter2will introduce the features,block diagram,signal descriptions and system usage of RK3066,the chapter3through chapter45will describe the full function of each module in detail.
1.2Features
1.2.1Processor
●Dual-core ARM Cortex-A9MPCore processor is a high-performance,low-power,
cached application processor
●Full implementation of the ARM architecture v7-A instruction set,ARM Neon
Advanced SIMD(single instruction,multiple data)support for accelerated media and signal processing computation
●Superscalar,variable length,out-of-order pipeline with dynamic branch prediction,8-
stage pipeline
●Include VFPv3hardware to support single and double-precision add,subtract,divide,
multiply and accumulate,and square root operations
●SCU ensures memory coherency between the two CPUs
●Integrated timer and watchdog timer per CPU
●Integrated32KB L1instruction cache,32KB L1data cache,4-waty set associative
●512KB unified L2Cache
●Trustzone technology support
●Full coresight debug solution
⏹Debug and trace visibility of whole systems
⏹ETM trace support
⏹Invasive and non-invasive debug
●Four separate power domain to support Internal power switch on/off and externally
turn on/off based on different application scenario
⏹PD_A9_0:1st Cortex-A9+Neon+FPU+L1I/D Cache
⏹PD_A9_1:2nd Cortex-A9+Neon+FPU+L1I/D Cache
⏹PD_DBG:CoreSight-DK for Cortex-A9
⏹PD_SCU:SCU+L2Cache controller,and including PD_A9_0,PD_A9_1,PD_DGB
●One isolated voltage domain to support DVFS
1.2.2Memory Organization
●Internal on-chip memory
⏹10KB BootRom
⏹64KB internal SRAM for security and non-security access,detailed size is
programmable
⏹2KB internal SRAM shared with NandC
●External off-chip memory①
⏹DDR3/LVDDR3,16/32bits data width,2ranks,2GB(max)address space per rank
⏹LPDDR,32bits data width,2ranks,2GB(max)address space per rank
⏹LPDDR2,32bits data width,2ranks,2GB(max)address space per rank
⏹Async SRAM/Nor Flash,8/16bits data width,2banks,1MB(max)address space per
bank
⏹Async Nand Flash(include LBA Nand),8/16bits data width,8banks
⏹Sync DDR Nand Flash,8bits data width,8banks
1.2.3Internal Memory
●Internal BootRom
⏹Size:10KB
⏹Support system boot from the following device:
◆8bits/16bits Async Nand Flash
◆SPI0interface
◆eMMC interface
⏹Support system code download by the following interface:
◆USB OTG
◆UART0in CPU system
●Internal SRAM
⏹Size:64KB
⏹Support security and non-security access
●512KB internal SRAM shared with L2Cache for Cortex-A9
1.2.4External Memory or Storage device
●Dynamic Memory Interface(DDR3/LVDDR3/LPDDR/LPDDR2)
⏹Compatible with JEDEC standard DDR3/LVDDR3/LPDDR/LPDDR2SDRAM
⏹Support up to2ranks(chip selects),maximum2GB address space per rank
⏹16bits/32bits data width is software programmable
⏹Programmable timing parameters support DDR3/LPDDR/LPDDR2SDRAM from
various vendor
⏹Low power modes,such as power-down and self-refresh for DDR3/LVDDR3/
LPDDR/LPDDR2SDRAM;clock stop and deep power-down for LPDDR/LVDDR3/
LPDDR2SDRAM
⏹Compensation for board delays and variable latencies through programmable
pipelines
⏹Programmable output and ODT impedance with dynamic PVT compensation
⏹Support one low-power work mode:power down DDR PHY and most of DDR IO
except two CS and two CKE output signals,make SDRAM still in self-refresh state to prevent data missing.
●Static Memory Interface(ASRAM/Nor Flash)
⏹Compatible with standard async SRAM or Nor Flash
⏹Support up to2banks(chip selects),maximum1MB address space per bank
⏹For bank0,8bits/16bits data width is software programmable;For bank1,16bits
data width is fixed
⏹Support separately data and address bus,also support shared data and address
bus to save IO numbers
●Nand Flash Interface
⏹Support8bits/16bits async nand flash,up to8banks
⏹Support8bits sync DDR nand flash,up to8banks
⏹Support LBA nand flash in async or sync mode
⏹Support up to60bits hardware ECC
⏹For async nand flash,support configurable interface timing,maximum data rate
is16bit/cycle
⏹Embedded AHB master interface to do data transfer by DMA method
⏹Also support data transfer by AHB slave interface together with external DMAC1
●eMMC Interface
⏹Compatible with standard INAND interface
⏹Support MMC4.41protocol
⏹Provide eMMC boot sequence to receive boot data from external eMMC device
⏹One AHB slave interface to complete data transfer together with external DMAC1
or CPU
⏹Support CRC generation and error detection
⏹Support host pull-up control,card detection and initialization,write protection
⏹Support block size from1to65535Bytes
⏹Data bus width is8bits
●SD/MMC Interface
⏹Compatible with SD3.0,MMC ver4.41
⏹One AHB slave interface to complete data transfer together with external DMAC1
or CPU
⏹Support CRC generation and error detection
⏹Embedded clock frequency division control to provide programmable baud rate
⏹Support host pull-up control,card detection and initialization,write protection
⏹Data bus width is flexible to support1bit/4bits for SD mode and1bit/4bits/8bits
for MMC mode
1.2.5System Component
●CRU(clock&reset unit)
⏹Support clock gating control for individual components inside RK3066
⏹Support global soft-reset control for whole SOC,also individual soft-reset for
every components
⏹Support flexible clock solution,including clock source,clock mux,clock frequency
division
⏹One oscillator with24MHz clock and4embedded PLLs
⏹Up to1.5GHz clock output for all PLLs
●PMU(power management unit)
⏹7work modes(slow mode,normal mode,idle mode,deep-idle mode,stop mode,
sleep mode,power-off mode)to save power by different frequency or auto
metical clock gating control or power domain on/off control
⏹Lots of wakeup sources in different mode
⏹Separate voltage domains
⏹Separate power domains,which can be power up/down by software based on
different application scenes
●Timer
⏹on-chip32bits Timers with interrupt-based operation
⏹Provide two operation modes:free-running and user-defined count
⏹Support timer work state checkable
⏹Fixed24MHz clock input
●PWM
⏹Four on-chip PWMs with interrupt-based operation
⏹Programmable4-bit pre-scalar from apb bus clock
⏹Embedded32-bit timer/counter facility
⏹Support single-run or continuous-run PWM mode
⏹Support maskable interrupt
⏹Provides reference mode and output various duty-cycle waveform
⏹Provides capture mode and measure the duty-cycle of input waveform
●WatchDog
⏹32bits watchdog counter width
⏹Counter clock is from APB bus clock
⏹Counter counts down from a preset value to0to indicate the occurrence of a
timeout
⏹WDT can perform two types of operations when timeout occurs:
◆Generate a system reset
◆First generate an interrupt and if this is not cleared by the service routine by
the time a second timeout occurs then generate a system reset
⏹Programmable reset pulse length
⏹Totally16defined-ranges of main timeout period
●Bus Architecture
⏹64-bit multi-layer AXI/AHB/APB composite bus architecture
⏹Five embedded AXI interconnect
●Interrupt Controller
⏹Support3PPI interrupt source and76SPI interrupt sources input from different
components inside RK3066
⏹Support16softwre-triggered interrupts
⏹Input interrupt level is fixed,only high-level sensitive
⏹Two interrupt output(nFIQ and nIRQ)to per Cortex-A9,both are low-level
sensitive
⏹Support different interrupt priority for each interrupt source,and they are always
software-programmable
●DMAC
⏹Micro-code programming based DMA
⏹The specific instruction set provides flexibility for programming DMA transfers
⏹Linked list DMA function is supported to complete scatter-gather transfer
⏹Support internal instruction cache
⏹Embedded DMA manager thread
⏹Support data transfer types with memory-to-memory,memory-to-peripheral,
peripheral-to-memory
⏹Signals the occurrence of various DMA events using the interrupt output signals
⏹Mapping relationship between each channel and different interrupt outputs is
software-programmable
⏹Two embedded DMA controller,DMAC0is for CPU system,DMAC1is for peri
system
⏹DMAC0features:
◆6channels totally
◆11hardware request from peripherals
◆2interrupt output
◆Dual APB slave interface for register config,designated as secure and non-
secure
◆Support trustzone technology and programmable secure state for each DMA
channel
⏹DMAC1features:
◆7channels totally
◆13hardware request from peripherals
◆2interrupt output
◆Not support trustzone technology
●Security system
⏹Support trustzone technology for the following components inside RK3066
1.2.6Video CODEC
●Shared internal memory and bus interface for video decoder and encoder②
●Video Decoder
⏹Real-time video decoder of MPEG-1,MPEG-2,MPEG-4,H.263,H.264,AVS,VC-1,
RV,VP6/VP8,Sorenson Spark,MVC
⏹Error detection and concealment support for all video formats
⏹Output data format is YUV420semi-planar,and YUV400(monochrome)is also
supported for H.264
⏹H.264up to HP level4.2:1080p@60fps(1920x1088)③
⏹MPEG-4up to ASP level5:1080p@60fps(1920x1088)
⏹MPEG-2up to MP:1080p@60fps(1920x1088)
⏹MPEG-1up to MP:1080p@60fps(1920x1088)
⏹H.263:576p@60fps(720x576)
⏹Sorenson Spark:1080p@60fps(1920x1088)
⏹VC-1up to AP level3:1080p@30fps(1920x1088)
⏹RV8/RV9/RV10:1080p@60fps(1920x1088)
⏹VP6/VP8:1080p@60fps(1920x1088)
⏹AVS:1080p@60fps(1920x1088)
⏹MVC:1080p@60fps(1920x1088)
⏹For AVS,4:4:4sampling not supported
⏹For H.264,Image cropping not supported
⏹For MPEG-4,GMC(global motion compensation)not supported
⏹For VC-1,upscaling and range mapping are supported in image post-processor
⏹For MPEG-4SP/H.263/Sorenson spark,using a modified H.264in-loop filter to
implement deblocking filter in post-processor unit
●Video Encoder
⏹Support video encoder for H.264(BP@level4.0,MP@level4.0,HP@level4.0),MVC
and VP8
⏹Only support I and P slices,not B slices
⏹Support error resilience based on constrained intra prediction and slices
⏹Input data format:
◆YCbCr4:2:0planar
◆YCbCr4:2:0semi-planar
◆YCbYCr4:2:2
◆CbYCrY4:2:2interleaved
◆RGB444and BGR444
◆RGB555and BGR555
◆RGB565and BGR565
◆RGB888and BRG888
◆RGB101010and BRG101010
⏹Image size is from96x96to1920x1088(Full HD)
⏹Maximum frame rate is up to30fps@1920x1080③
⏹Bit rate supported is from10Kbps to20Mbps
1.2.7JPEG CODEC
●JPEG decoder
⏹Input JPEG file:YCbCr4:0:0,4:2:0,4:2:2,4:4:0,4:1:1and4:4:4sampling
formats
⏹Output raw image:YCbCr4:0:0,4:2:0,4:2:2,4:4:0,4:1:1and4:4:4semi-
planar
⏹Decoder size is from48x48to8176x8176(66.8Mpixels)
⏹Maximum data rate④is up to76million pixels per second
●JPEG encoder
⏹Input raw image:
◆YCbCr4:2:0planar
◆YCbCr4:2:0semi-planar
◆YCbYCr4:2:2
◆CbYCrY4:2:2interleaved
◆RGB444and BGR444
◆RGB555and BGR555
◆RGB565and BGR565
◆RGB888and BRG888
◆RGB101010and BRG101010
⏹Output JPEG file:JFIF file format1.02or Non-progressive JPEG
⏹Encoder image size up to8192x8192(64million pixels)from96x32
⏹Maximum data rate④up to90million pixels per second
1.2.8Image Enhancement
●Image pre-processor
⏹Only used together with HD video encoder inside RK3066,not support stand-
alone mode
⏹Provides RGB to YCbCr4:2:0color space conversion,compatible with BT.601,
BT.709or user defined coefficients
⏹Provides YCbCr4:2:2to YCbCr4:2:0color space conversion
⏹Support cropping operation from8192x8192to any supported encoding size
⏹Support rotation with90or270degrees
●Video stabilization
⏹Work in combined mode with HD video encoder inside RK3066and stand-alone
mode
⏹Adaptive motion compensation filter
⏹Support scene detection from video sequence,encodes key frame when scene
change noticed
●Image post-processor(embedded inside video decoder)
⏹Combined with HD video decoder and JPEG decoder,post-processor can read
input data directly from decoder output to reduce bus bandwidth
⏹Also work as a stand-alone mode,its input data is from a camera interface or
other image data stored in external memory
⏹Input data format:
◆any format generated by video decoder in combined mode
◆YCbCr4:2:0semi-planar
◆YCbCr4:2:0planar
◆YCbYCr4:2:2
◆YCrYCb4:2:2
◆CbYCrY4:2:2
◆CrYCbY4:2:2
⏹Ouput data format:
◆YCbCr4:2:0semi-planar
◆YCbYCr4:2:2
◆YCrYCb4:2:2
◆CbYCrY4:2:2
◆CrYCbY4:2:2
◆Fully configurable ARGB channel lengths and locations inside32bits,such as
ARGB8888,RGB565,ARGB4444etc.
⏹Input image size:
◆Combined mode:from48x48to8176x8176(66.8Mpixels)
◆Stand-alone mode:width from48to8176,height from48to8176,and
maximum size limited to16.7Mpixels
◆Step size is16pixels
⏹Output image size:from16x16to1920x1088(horizontal step size8,vertical step
size2)
⏹Support image up-scaling:
◆Bicubic polynomial interpolation with a four-tap horizontal kernel and a two-
tap vertical kernel
◆Arbitrary non-integer scaling ratio separately for both dimensions
◆Maximum output width is3x input width
◆Maximum output height is3x input height
⏹Support image down-scaling:
◆Arbitrary non-integer scaling ratio separately for both dimensions
◆Unlimited down-scaling ratio
⏹Support YUV to RGB color conversioin,compatible with BT.601-5,BT.709and
user definable conversion coefficient
⏹Support dithering(2x2ordered spatial dithering for4,5,6bit RGB channel
precision
⏹Support programmable alpha channel and alpha blending operation with the
following overlay input formats:
◆8bit alpha+YUV444,big endian channel order with AYUV8888
◆8bit alpha+24bit RGB,big endian channel order with ARGB8888
⏹Support deinterlacing with conditional spatial deinterlace filtering,only
compatible with YUV420input format
⏹Support RGB image contrast/brightness/color saturation adjustment
⏹Support image cropping&digital zoom only for JPEG or stand-alone mode
⏹Support picture in pcture
⏹Support image rotation(horizontal flip,vertical flip,rotation90,180or270
degrees)
●Image Post-Processor(IPP)(standalone)
⏹memory to memory mode
⏹input data format and size
◆RGB888:16x16to8191x8191
◆RGB565:16x16to8191x8191
◆YUV422/YUV420:16x16to8190x8190
◆YUV444:16x16to8190x8190
⏹pre scaler
◆integer down-scaling(ratio:1/2,1/3,1/4,1/5,1/6,1/7,1/8)with linear filter
◆deinterlace(up to1080i)to support YUV422&YUV420input format
⏹post scaler
◆down-scaling with1/2~1arbitary non-integer ratio
◆up-scaling with1~4arbitary non-integer ratio
◆4-tap vertical,2-tap horizontal filter
◆The max output image width of post scaler is4096
⏹Support rotation with90/180/270degrees and x-mirror,y-mirror
1.2.9Graphics Engine
●3D Graphics Engine:
⏹Compatible with OpenGL ES1.1and2.0,OpenVG1.1.
⏹Embedded four shader cores with shared hierarchical tiler
⏹Unified sharder architecture
⏹Provide MMU and L2Cache with128KB size
⏹Pixel rate:1G pixel/s
●2D Graphics Engine:
⏹Bit Blit with Strength Blit,Simple Blit and Filter Blit
⏹High-performance stretch and shrink
⏹Monochrome expansion for text rendering
⏹ROP2,ROP3,ROP4full alpha blending and transparency
⏹Alpha blending modes including Java2Porter-Duff compositing blending rules,
chroma key,and pattern mask
⏹8K x8K raster2D coordinate system
⏹Programmable bicubic filter to support image scaling
⏹Source format:
◆ABGR8888,XBGR888,ARGB8888,XRGB888
◆RGB888,RGB565
◆RGBA5551,RGBA4444
◆YUV420planar,YUV420semi-planar
◆YUV422planar,YUV422semi-planar
◆BPP8,BPP4,BPP2,BPP1
⏹Destination formats:
ABGR8888,XBGR888,ARGB8888,XRGB888
◆RGB888,RGB565
◆RGBA5551,RGBA4444
◆YUV420planar,YUV420semi-planar only in filter and pre-scale mode
⏹YUV422planar,YUV422semi-planar only in filter and pre-scale mode
1.2.10Video IN/OUT
●Camera Interface
⏹2independent camera interface controller
⏹Support up to5M pixels
⏹8bits CCIR656(PAL/NTSC)interface
⏹8bits/10bits/12bits raw data interface
⏹YUV422data input format with adjustable YUV sequence
⏹YUV422,YUV420output format with separately Y and UV space
⏹Support picture in picture(PIP)
⏹Support simple image effects such as Arbitrary(sepia),Negative,Art freeze,
Embossing etc.
⏹Support static histogram statistics and white balance statistics
⏹Support image crop with arbitrary windows
⏹Support scale up/down from1/8to8with arbitrary non-integer ratio
●Display Interface
⏹independent two display controllers for HDMI and TFT dual panel display
⏹Support LCD or TFT interfaces up to1920x1080
⏹Support HDMI1.4output up to1080p@30fps
⏹Support TV interface with ITU-R BT.656(8bits,480i/576i/1080i)
⏹Parallel RGB LCD Interface:RGB888(24bits),RGB666(18bits),RGB565(15bits)
⏹Serial RGB LCD Interface:3x8bits with RGB delta support,3x8bits followed by
dummy data,16bits followed by8bits
⏹MCU LCD interface:i-8080with up to24bits RGB
⏹5display layers:
◆One background layer with programmable24bits color
◆One video layer(win0)
RGB888,ARGB888,RGB565,YUV422,YUV420,AYUV
maximum resolution is1920x1080
1/8to8scaling up/down engine with arbitrary non-integer ratio
256level alpha blending
Support transparency color key
Support3D display
◆One video layer(win1)
RGB888,ARGB888,RGB565,YUV422,YUV420,AYUV
maximum resolution is1920x1080
1/8to8scaling up/down engine with arbitrary non-integer ratio
256level alpha blending
Support transparency color key
◆One OSD layer(win2)
RGB888,ARGB888,RGB565,1/2/4/8BPP
256level alpha blending
transparency color key
◆Hardware cursor(win3)
2BPP
Maximum resolution64x64
3-color and transparent mode
2-color+transparency+tran_invert mode
16level alpha blending
⏹Support180rotation in combined mode with LCDC or separately mode
⏹3x256x8bits display LUTs
⏹Win0and Win1layer overlay exchangeable
⏹Support color space conversion:
YUV2RGB(rec601-mpeg/rec601-jpeg/rec709)and RGB2YUV
⏹Deflicker support for interlace output
⏹Support replication(16bits to24bits)and dithering(24bits to16bits/18bits)
operation
1.2.11Audio Interface
●I2S/PCM with8ch
⏹Up to8channels(4xTX,2xRX)
⏹Audio resolution from16bits to32bits
⏹Sample rate up to192KHz
⏹Provides master and slave work mode,software configurable
⏹Support3I2S formats(normal,left-justified,right-justified)
⏹Support4PCM formats(early,late1,late2,late3)
⏹I2S and PCM cannot be used at the same time
●I2S/PCM with2ch
⏹2independent2ch I2S/PCM interface
⏹Up to2channels(2xTX,2xRX)
⏹Audio resolution from16bits to32bits
⏹Sample rate up to192KHz
⏹Provides master and slave work mode,software configurable
⏹Support3I2S formats(normal,left-justified,right-justified)
⏹Support4PCM formats(early,late1,late2,late3)
⏹I2S and PCM cannot be used at the same time
●SPDIF
⏹Audio resolution:16bits/20bits/24bits
⏹Software configurable sample rates(48KHz,44.1KHz,32KHz)
⏹Stereo voice replay with2channels
1.2.12Connectivity
●SDIO interface
⏹Compatible with SDIO3.0protocol
⏹Support FIFO over-run and under-run prevention by stopping card clock
automatically
⏹4bits data bus width
●High-speed ADC&TS stream interface
⏹Support dual-channel8bits/10bits interface
⏹DMA-based and interrupt-based operation
⏹Support8bits TS stream interface
⏹Support PID filter operation
◆Combined with high-speed ADC interface to implement filter from original TS
data
◆Provide PID filter up to64channels PID simultaneously
◆Support sync-byte detection in transport packet head
◆Support packet lost mechanism in condition of limited bandwidth
●MAC10/100M Ethernet Controller
⏹IEEE802.3u compliant Ethernet Media Access Controller(MAC)
⏹10Mbps and100Mbps compatible
⏹Automatic retry and automatic collision frame deletion
⏹Full duplex support
⏹PAUSE full-duplex flow-control support
⏹Address filtering(broadcast,multicast,logical,physical)
⏹Support only RMII(Reduced MII)mode
⏹In RMII mode,clock can be from RK3066or external ethernet PHY
●SPI Controller
⏹Two on-chip SPI controller inside RK3066
⏹Support serial-master and serial-slave mode,software-configurable
⏹DMA-based or interrupt-based operation
⏹Embedded two32x16bits FIFO for TX and RX operation respectively
⏹Support2chip-selects output in serial-master mode
●Uart Controller
⏹Four on-chip uart controller inside RK3066
⏹DMA-based or interrupt-based operation
⏹Embedded two32Bytes FIFO for TX and RX operation respectively
⏹Support5bit,6bit,7bit,8bit serial data transmit or receive
⏹Standard asynchronous communication bits such as start,stop and parity
⏹Support different input clock for uart operation to get up to4Mbps or other
special baud rate
⏹Support non-integer clock divides for baud clock generation
⏹Auto flow control mode is only for UART0,UART1,UART2
●I2C controller
⏹Five on-chip I2C controller in RK3066
⏹Multi-master I2C operation
⏹Support7bits and10bits address mode
⏹Software programmable clock frequency and transfer rate up to400Kbit/s in the
fast mode
⏹Serial8bits oriented and bidirectional data transfers can be made at up to
100Kbit/s in the standard mode
●GPIO
⏹6groups of GPIO(GPIO0~GPIO4,GPIO6),32GPIOs per group in GPIO0~GPIO4,
and16GPIOs in GPIO6,totally have176GPIOs
⏹All of GPIOs can be used to generate interrupt to Cortex-A9
⏹GPIO6can be used to wakeup system from stop/sleep/power-off mode
⏹All of pullup GPIOs are software-programmable for pullup resistor or not
⏹All of pulldown GPIOs are software-programmable for pulldown resistor
or not
⏹All of GPIOs are pullup or pulldown in default except GPIO1[5]mux with
PWM3after power-on-reset
⏹All of GPIOs are always in input direction in default after power-on-reset
●USB Host2.0
⏹Compatible with usb host2.0specification
⏹Supports high-speed(480Mbps),full-speed(12Mbps)and low-speed(1.5Mbps)
mode
⏹Provides16host mode channels
⏹Support periodic out channel in host mode
●USB OTG2.0
⏹Compatible with USB otg2.0specification
⏹Supports high-speed(480Mbps),full-speed(12Mbps)and low-speed(1.5Mbps)
mode
⏹Support up to9device mode endpoints in addition to control endpoint0
⏹Support up to6device mode IN endpoints including control endpoint0
⏹Endpoints1/3/5/7can be used only as data IN endpoint
⏹Endpoints2/4/6can be used only as data OUT endpoint
⏹Endpoints8/9can be used as data OUT and IN endpoint
⏹Provides9host mode channels
●HDMI TX1.4
⏹HDMI version1.4a,HDCP revision1.4and DVI version1.0compliant transmitter
⏹Supports DTV from480i to1080i/p HD resolution,and PC from VGA to UXGA
⏹Supports3D and2k x4k video resolution output
⏹Programmable2-way color space converter
⏹Compliant with EIA/CEA-861D
⏹Deep color supported up to12bit per pixel.
⏹xvYCC Enhanced Colorimetry
⏹Gamut Metadata transmission
⏹Supports RGB,YCbCr digital video input format includes ITU.656
⏹36bit RGB/YCbCr4:4:416/20/24bit YCbCr4:2:28/10/12bit YCbCr4:2:2
(ITU.601and656)
⏹Supports standard SPDIF for stereo or compressed audio up to192KHz
⏹Support PCM,Dolby digital,DTS digital audio transmission through4bits I2S up
to8channel IEC60958or IEC61937compatible
⏹1bit audio format(Super Audio CD)
⏹High-bitrate compressed audio formats
⏹Master I2C interface for DDC connection
⏹Configuration registers programmable via parallel interface
⏹Wide range channel speed up to2.2Gbps
⏹Programmable PLL characteristics,channel delay,and transmitter pre-emphasis
rate
⏹Small ISI jitter by full differential data path
1.2.13Others
●Temperature Sensor
●SAR-ADC(Successive Approximation Register)
⏹4-channel single-ended10-bit SAR analog-to-digital converter
⏹Conversion speed range is from0.1to1MSPS
⏹SAR-ADC clock must be less than1MHz
⏹DNL less than±1LSB,INL less than±2.0LSB
⏹Power down current is about1uA
⏹Power supply is2.5V(±10%)for analog interface
●eFuse
⏹256bits(32x8)high-density electrical Fuse
⏹Programming condition:VQPS must be2.5V(±10%)
⏹Program time is about4~6us
⏹Read condition:VQPS must be0V or floating or2.5V(±10%)
⏹Provide power-down and standby mode
●Package Type
⏹TFBGA453(body:19mm x19mm;ball pitch:0.8mm)
1.3
The
CHAPTER2Package information
2.1Dimension
Fig.2
Fig.2RK3066TFBGA453Package Side View
Fig.4RK3066TFBGA453Package Bottom View
Fig.5RK3066TFBGA453Package Dimension
2.2Ball Map
2.3Pin Number Order
2.4RK3066power/ground IO descriptions
2.5RK3066function IO descriptions Rockchips Confidential28
Rockchips Confidential29
Rockchips Confidential30
④:It is die location.For examples,“Left side”means that all the related IOs are always in left side of die
⑤:Power supply means that all the related IOs is in these IO power domain.If multiple powers is included,they are connected together in one IO power ring
RK3066Datasheet brief Rev1.0 CHAPTER3Electrical Specification
3.1Absolute Maximum Ratings
damaged permanently.Long-term exposure to absolute maximum ratings conditions may affect device reliability.
3.2Recommended Operating Conditions
Operating Temperature-402585℃Notes:①：Symbol name is same as the pin name in the io descriptions
3.3DC Characteristics
3.4Electrical Characteristics for General IO
NF is the feedback divider value;NO is the output divider value
(i=2~3)
Input Low Voltage
V il_ddr
-0.30
DDR_VREF[i ]-0.13
(i=2~3)V
Output High Voltage
V oh_ddr
0.9*VDDIO_BL i
(i=0~3) 1.2N/A V
Output Low Voltage
V ol_ddr
N/A
00.1*VDDIO_BL i
(i=0~3)
V。