特性阻抗控制简介
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thickness decreases. (e) Use thinnest copper allowable consistent with other design requirements.
Impedance values decreases as the copper thickness increases.
Impedance control design guideline
(f) Keep controlled impedance conductors at least 2.5 mm from the edge of the reference plane.
(g) Avoid placing conductors over copper void areas greater than 5.0 mm square. (h) Route critical conductors on inner layer between reference plane or buried
特性阻抗控制簡介
內容
（1） 傳輸線種類 （2） 特性阻抗控制要項 （3）特性阻抗設計重點
傳輸線
(1) 微條線 ( Microstrip )
(2) 條線 ( Stripline )
傳輸線
(3) 共面波導及備地共面波導
( Coplanar Wave-Guide & Coplanar Wave-Guide with Ground )
(b) Type of line – For a given equal εr , spacing, and conductor width, impedance value will be greater for a microstrip than for a stripline.
(c) εr , Relative permittivity – Higher εr results in a lower impedance value (d) Dielectric thickness between signal and ground – Lower impedance as
Z0
Z1
Indicated Energy
ZL
Transmitted Energy
Z0
Z0
Indicated Energy
Z1
Transmitted Energy
Reflected Energy 1
Reflected Energy 2
Less Reflected Energy
PLATING COPPER SAVING 40%
3.0/4.0 2.5/3.5 3.8/4.8 3.5/4.5 3.0/4.0
71.93 79.11
74.92 82.12
Z0(O) 85
67.69 74.83
69.17 76.32
71.84 79.01
Z0 of L1 when S/M 0.8mil
Max
80
Leabharlann Baidu
80
2.5/3.5
74.83 82.02
Above data is calculated based on: 1. Unit : mil 2. Inner-layer 1 Oz Cu 3. Inner-layer Cu density around 60%
傳輸線佈線概念
(1) 傳輸線寬均一 (2)傳輸線線路不可修補
傳輸線線厚設計
(3) 面銅與孔銅厚度力求相近
Board thickness VS material
Prepreg
1080
2116 2116H 1506L 1506 7628 7628H
Before Lam After Lam
RC ( % ) Thk σ T h k σ 63+/-3 3.5 0.1 2.7 0.4 52+/-3 5.5 0.1 4.4 0.2 57+/-3 6 0.1 4.8 0.4 48+/-3 7.5 0.1 6.3 0.2 52+/-3 8 0.1 6.6 0.2 44+/-3 9 0.1 7.4 0.2 49+/-3 10 0.1 8.0 0.4
Reflected Wave
Digital Oscilloscope
Step Pulse Generator
Transmission Line Under Test
Incident Wave
特性阻抗控制要項計算 -- Example
L2 reference to L3 S/M THK (H1)
Microstrip Impedance Z0：75Ω+/-10%(67.5~82.5 Ω)
Trace THK : 1.2 mil εr : 4.2
LW/LS : 4/6 mil
0.4 mil
0.8 mil
傳輸線佈線概念
(4) 雜訊與干擾 4-1 串訊 ( cross talk )
厚板只能佈疏線
薄板可以佈密線
傳輸線佈線概念
4-2 密長之平行線互感 ( Mutual Inductance Noise )
太長太密的平行線因磁場的互感與電場 的互容而造成串訊(Crosstalk)的雜訊
•改善方法： •1.階梯式佈線 •2.逼薄介質曾
Impedance control capability
S/M thickness : 0.6 mil
Cu Thickness : 1.0mil
Dielectric thk. : 8.0 mil(7628)
MicroStrip design to reach 100 Ω
Differential design to reach 100 Ω
Line Width : 2.0 mil
Line Width/Space: 10.0/10.0 mil
Balanced line provide better noise immunity and improved timing
Impedance control design guideline
(a) Conductor cross section – Conductors, particularly on outer layer, are sensitive to width duo to plating and etching. Wider lines lower impedance while narrower lines raise it.
-------------------------------------------------------------減少串訊 (09) 盡量依照右圖原則擺放零件，將不同操作頻率之電路予以區隔
-------------------------------------------------------------減少串訊 (10) 訊號線與參考層盡量接近-----------------------------縮短迴路截面積
4-6 通孔設計
(1) 早期訊號不快，訊號線共用 一腳接地
(2) 高速傳輸時，接地愈多愈好
特性阻抗設計重點
4-7 盲孔
迴路未遭破壞傳輸才完整
迴路遭破壞訊號完整性(SI)不良
特性阻抗設計重點
盲孔之寄生電感遠小於通孔
Z0 = √ ( L / C )
特性阻抗控制要項
(1) PCB Layout 建議
傳輸線佈線概念
4-3 射頻干擾 ( Radio Frequency Interference )
•Fringing(層間耦合)
•20H:可消除70%的磁通量(Flux boundary) •100H:可消除98%的磁通量
傳輸線佈線概念
4-4 靜電釋放干擾 ( ESD )
4-5 EMI
傳輸線佈線概念
低速邏 輯
中速邏 輯
高速邏 輯
I/O connector
特性阻抗控制要項
(2) PCB 製作建議 (1) 使用 PCB常用原物料--------------------------材料穩定性 (2) 設計阻抗值應依照 PCB疊構能力-----------降低製程難度 (3) 同一層之傳輸線線寬應儘可能一致---------降低製程難度 (4) 銅鍍與面銅厚度盡量一致--------------------減少能量反射 (5) 力求最大之容許公差值-----------------------降低製造成本 (6) 使用差動阻抗-----------------------------------降低製造成本
outer layer. (i) Avoid “extreme” builds such as fine conductors or thick board construction. (j) Place test control coupon in the circuit area or use active conductors with
Z0 (Ohm)
Dielectric (7H6)28H + 8mil 1/1
W/W1(mil)
16.2mil 19.2mil
3.8/4.8
67.78 75.41
3.5/4.5
69.26 76.41
Z (O) 120
0120
110
110
85100
100
90
90
80
80
Z0 of L1 when S/M 0.4mil Max
(01) 善用 Delay line 設計-------------------------------------取得一致之正時 (02) 降低傳輸線長度------------------------------------------降低能量損耗 (03) 傳輸線若須轉折時，應以圓弧修正之---------------減少能量反射 (04) 以地線或接地層隔開傳輸線---------------------------減少串訊 (05) 加大傳輸線間之距離-----------------------------------減少串訊 (06) 避免平行佈線--------------------------------------------減少串訊 (07) 針對不同邏輯電路設計個別迴路，避免共用-----減少串訊 (08) 限制每一邏輯族 （ Logic Family）內之訊號線長度及數量
adjacent reference point (2.5 mm) as the test coupon. (k) Use different conductor codes for each controlled impedance.
•特性阻抗的量測 •時域反射儀 (Time Domain Reflectometry ; TDR)
A:Inner layer
copper THK
B:Plated hole
copper THK
C:Outer layer
copper THK
C
B Ａ
Ａ:0.6mil B:1.0mil
TRACE
0.6mil 1.0mil
C:1.8mil
1.2mil 0.6mil 1.8mil
C B
Ａ
Ａ:0.6mil B:0.6mil C:1.0mil
特性阻抗控制要項
(1) Z0 是 εr、介質層厚度、線寬、線厚之函數 (2) Z0 與介質層厚度成正比，與其餘各參數成反比
特性阻抗控制因子貢獻度
4% 5%
30%
T εr
W
H
61%
•H:Dielectric thickness •T:Cu thickness •W:Line width •εr:Dielectric constant
75
75
70 Min
65 16.2mil
3.8/4.8
3.5/4.5 70 3.0/4.0
2.5/3.5 65
19.2mil
Min 16.2mil
3.8/4.8 3.5/4.5 3.0/4.0 2.5/3.5
19.2mil
L2 trace must be controlled within 3.5 to 4.8 mil
Impedance values decreases as the copper thickness increases.
Impedance control design guideline
(f) Keep controlled impedance conductors at least 2.5 mm from the edge of the reference plane.
(g) Avoid placing conductors over copper void areas greater than 5.0 mm square. (h) Route critical conductors on inner layer between reference plane or buried
特性阻抗控制簡介
內容
（1） 傳輸線種類 （2） 特性阻抗控制要項 （3）特性阻抗設計重點
傳輸線
(1) 微條線 ( Microstrip )
(2) 條線 ( Stripline )
傳輸線
(3) 共面波導及備地共面波導
( Coplanar Wave-Guide & Coplanar Wave-Guide with Ground )
(b) Type of line – For a given equal εr , spacing, and conductor width, impedance value will be greater for a microstrip than for a stripline.
(c) εr , Relative permittivity – Higher εr results in a lower impedance value (d) Dielectric thickness between signal and ground – Lower impedance as
Z0
Z1
Indicated Energy
ZL
Transmitted Energy
Z0
Z0
Indicated Energy
Z1
Transmitted Energy
Reflected Energy 1
Reflected Energy 2
Less Reflected Energy
PLATING COPPER SAVING 40%
3.0/4.0 2.5/3.5 3.8/4.8 3.5/4.5 3.0/4.0
71.93 79.11
74.92 82.12
Z0(O) 85
67.69 74.83
69.17 76.32
71.84 79.01
Z0 of L1 when S/M 0.8mil
Max
80
Leabharlann Baidu
80
2.5/3.5
74.83 82.02
Above data is calculated based on: 1. Unit : mil 2. Inner-layer 1 Oz Cu 3. Inner-layer Cu density around 60%
傳輸線佈線概念
(1) 傳輸線寬均一 (2)傳輸線線路不可修補
傳輸線線厚設計
(3) 面銅與孔銅厚度力求相近
Board thickness VS material
Prepreg
1080
2116 2116H 1506L 1506 7628 7628H
Before Lam After Lam
RC ( % ) Thk σ T h k σ 63+/-3 3.5 0.1 2.7 0.4 52+/-3 5.5 0.1 4.4 0.2 57+/-3 6 0.1 4.8 0.4 48+/-3 7.5 0.1 6.3 0.2 52+/-3 8 0.1 6.6 0.2 44+/-3 9 0.1 7.4 0.2 49+/-3 10 0.1 8.0 0.4
Reflected Wave
Digital Oscilloscope
Step Pulse Generator
Transmission Line Under Test
Incident Wave
特性阻抗控制要項計算 -- Example
L2 reference to L3 S/M THK (H1)
Microstrip Impedance Z0：75Ω+/-10%(67.5~82.5 Ω)
Trace THK : 1.2 mil εr : 4.2
LW/LS : 4/6 mil
0.4 mil
0.8 mil
傳輸線佈線概念
(4) 雜訊與干擾 4-1 串訊 ( cross talk )
厚板只能佈疏線
薄板可以佈密線
傳輸線佈線概念
4-2 密長之平行線互感 ( Mutual Inductance Noise )
太長太密的平行線因磁場的互感與電場 的互容而造成串訊(Crosstalk)的雜訊
•改善方法： •1.階梯式佈線 •2.逼薄介質曾
Impedance control capability
S/M thickness : 0.6 mil
Cu Thickness : 1.0mil
Dielectric thk. : 8.0 mil(7628)
MicroStrip design to reach 100 Ω
Differential design to reach 100 Ω
Line Width : 2.0 mil
Line Width/Space: 10.0/10.0 mil
Balanced line provide better noise immunity and improved timing
Impedance control design guideline
(a) Conductor cross section – Conductors, particularly on outer layer, are sensitive to width duo to plating and etching. Wider lines lower impedance while narrower lines raise it.
-------------------------------------------------------------減少串訊 (09) 盡量依照右圖原則擺放零件，將不同操作頻率之電路予以區隔
-------------------------------------------------------------減少串訊 (10) 訊號線與參考層盡量接近-----------------------------縮短迴路截面積
4-6 通孔設計
(1) 早期訊號不快，訊號線共用 一腳接地
(2) 高速傳輸時，接地愈多愈好
特性阻抗設計重點
4-7 盲孔
迴路未遭破壞傳輸才完整
迴路遭破壞訊號完整性(SI)不良
特性阻抗設計重點
盲孔之寄生電感遠小於通孔
Z0 = √ ( L / C )
特性阻抗控制要項
(1) PCB Layout 建議
傳輸線佈線概念
4-3 射頻干擾 ( Radio Frequency Interference )
•Fringing(層間耦合)
•20H:可消除70%的磁通量(Flux boundary) •100H:可消除98%的磁通量
傳輸線佈線概念
4-4 靜電釋放干擾 ( ESD )
4-5 EMI
傳輸線佈線概念
低速邏 輯
中速邏 輯
高速邏 輯
I/O connector
特性阻抗控制要項
(2) PCB 製作建議 (1) 使用 PCB常用原物料--------------------------材料穩定性 (2) 設計阻抗值應依照 PCB疊構能力-----------降低製程難度 (3) 同一層之傳輸線線寬應儘可能一致---------降低製程難度 (4) 銅鍍與面銅厚度盡量一致--------------------減少能量反射 (5) 力求最大之容許公差值-----------------------降低製造成本 (6) 使用差動阻抗-----------------------------------降低製造成本
outer layer. (i) Avoid “extreme” builds such as fine conductors or thick board construction. (j) Place test control coupon in the circuit area or use active conductors with
Z0 (Ohm)
Dielectric (7H6)28H + 8mil 1/1
W/W1(mil)
16.2mil 19.2mil
3.8/4.8
67.78 75.41
3.5/4.5
69.26 76.41
Z (O) 120
0120
110
110
85100
100
90
90
80
80
Z0 of L1 when S/M 0.4mil Max
(01) 善用 Delay line 設計-------------------------------------取得一致之正時 (02) 降低傳輸線長度------------------------------------------降低能量損耗 (03) 傳輸線若須轉折時，應以圓弧修正之---------------減少能量反射 (04) 以地線或接地層隔開傳輸線---------------------------減少串訊 (05) 加大傳輸線間之距離-----------------------------------減少串訊 (06) 避免平行佈線--------------------------------------------減少串訊 (07) 針對不同邏輯電路設計個別迴路，避免共用-----減少串訊 (08) 限制每一邏輯族 （ Logic Family）內之訊號線長度及數量
adjacent reference point (2.5 mm) as the test coupon. (k) Use different conductor codes for each controlled impedance.
•特性阻抗的量測 •時域反射儀 (Time Domain Reflectometry ; TDR)
A:Inner layer
copper THK
B:Plated hole
copper THK
C:Outer layer
copper THK
C
B Ａ
Ａ:0.6mil B:1.0mil
TRACE
0.6mil 1.0mil
C:1.8mil
1.2mil 0.6mil 1.8mil
C B
Ａ
Ａ:0.6mil B:0.6mil C:1.0mil
特性阻抗控制要項
(1) Z0 是 εr、介質層厚度、線寬、線厚之函數 (2) Z0 與介質層厚度成正比，與其餘各參數成反比
特性阻抗控制因子貢獻度
4% 5%
30%
T εr
W
H
61%
•H:Dielectric thickness •T:Cu thickness •W:Line width •εr:Dielectric constant
75
75
70 Min
65 16.2mil
3.8/4.8
3.5/4.5 70 3.0/4.0
2.5/3.5 65
19.2mil
Min 16.2mil
3.8/4.8 3.5/4.5 3.0/4.0 2.5/3.5
19.2mil
L2 trace must be controlled within 3.5 to 4.8 mil