2014《数字逻辑设计》期末考试-试题及参考解答

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电子科技大学2013 -2014学年第 二 学期期 末 考试 A 卷

课程名称：_数字逻辑设计及应用__ 考试形式： 闭卷 考试日期： 20 14 年 07 月 10 日 考试时长：_120___分钟

课程成绩构成：平时 30 %， 期中 30 %， 实验 0 %， 期末 40 % 本试卷试题由___六__部分构成，共__8___页。

题号 一 二 三 四 五 六 七 八 九 十 合计得分

I. Fill out your answers in the blanks

(3’ X 10=30’)

1. A circuit with 10 flip-flops can store ( 10 ) bit binary numbers, that is, include ( 1024 或 210 ) states at most.

2. A 5-bit linear feedback shift-register (LFSR) counter with no self-correction can have ( 31 或 25-1 ) normal states.

3. A modulo-24 counter circuit needs ( 5 ) D filp-flops at least. A modulo-500 counter circuit needs ( 3 ) 4-bit counters of 74x163 at least.

4. If an 74x148 priority encoder has its 1, 3, 4, and 5 inputs at the active level, the active LOW binary output is ( 010 ) .

5. State/output table for a sequential circuit is shown as Table 1. X is input and Z n is output. Assume that the initial state is S 0, if the input sequence is X = 01110101, the output sequence should be ( 11001100 或110011000 ). 【可以确定的输出序列应该有9位】

.

3 ) up/down counter.

n+1n 21

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7. A serial sequence generator by feedback shift registers 74x194 is shown in Figure 1, assume the initial state is Q2Q1Q0 = 100, the feedback function LIN = Q2’Q1’ + Q2Q0’, the output sequence in Q2 is ( 100110循环输出 ).

Figure 1

8. When the input is 01100000 of an 8 bit DAC, the corresponding output voltage is 3.76V. The output voltage range for the DAC is ( 0 ~ 9.99 或

5

6

8

2

2

1

2

76

.3

+

−

×或

96

255

76

.3× )V. 【本题并未对误差范围进行要求，一般可保留2位小数。由于考试时没有计算器，写出算式也可】

II. Please select the only one correct answer in the following questions.(2’ X 5=10’)

1. The output signal of ( A ) circuit is 1-out-of-M code.

A. binary decoder

B. binary encoder

C. seven-segment decoder

D. decade counter

2. An asynchronous counter differs from a synchronous in ( B).

A. the number of states in its sequence

B. the method of clocking

C. the type of flip-flop used

D. the value of the modulus

3. There are ( D) unused states for an n-bit Jonson counter.

A. n

B. 2n

C. 2n-n

D. 2n-2n

4. The capacity of a memory that has 12 bits address bus and can store 8 bits at each address is ( A).

A. 32768

B. 8192

C. 20

D. 256

5. Consider the following 4×4 “two-dimensional arbiter” shown in Figure 2 with inputs R0,0,R0,1,R0,2,R0,3,

R1,0,R1,1,R1,2,R1,3, · · · R3,0,R3,1,R3,2,R3,3 (“requests”) and outputs G0,0,G0,1,G0,2,G0,3,

G1,0,G1,1,G1,2,G1,3, · · · G3,0,G3,1,G3,2,G3,3 (“grants”). Wi,0’s and N0,j ’s are also inputs, and Ei,4’s and