74ls74说明资料

Figure 2. Set and Clear to Output Delays, Set and Clear Pulse Widths
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14
1
A F
N
–T–
SEATING PLANE
H
G
SN74LS74A
PACKAGE DIMENSIONS
N SUFFIX PLASTIC PACKAGE
Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.
M
J
0.25 (0.010) M T B S A S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
Limits
Symbol
Parameter
VIH
Input HIGH Voltage
Min Typ Max Unit
Test Conditions
2.0
V
Guaranteed Input HIGH Voltage for All Inputs
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for All Inputs
4
10
2 D SD Q 5 12 D SD Q 9
3 CP
11 CP
CD Q 6
CD Q 8
1
13
VCC = PIN 14 GND = PIN 7
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SN74LS74A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
i, h (q) = (or output) one set-up time prior to the HIGH to LOW clock transition.
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SN74LS74A
PACKAGE DIMENSIONS
–A–
14 1
G
D SUFFIX PLASTIC SOIC PACKAGE
CASE 751A–03 ISSUE F
8
–B– P 7 PL 0.25 (0.010) M B M
7
C
R X 45 _
F
–T–
SEATING PLANE
D 14 PL
K
Limits
Symbol
fMAX
tPLH tPHL
Parameter Maximum Clock Frequency
Clock, Clear, Set to Output
Min Typ Max Unit
25
33
MHz
13
25
ns
25
40
ns
Test Conditions
Figure 1 Figure 1
Device
Package
Shipping
SN74LS74AN 14 Pin DIP 2000 Units/Box
SN74LS74AD
14 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
CASE 646–06 ISSUE M
8
B
7
L C
K
J
D 14 PL
M
0.13 (0.005) M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
– 20
–100 mA
ICC
Power Supply Current
8.0
mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
VCC = MAX VCC = MAX
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Input High Current
Data, Clock
IIH
Set, Clear
Data, Clock
Set, Clear
– 0.65 – 1.5
V
VCC = MIN, IIN = – 18 mA
25
ns
Figure 1
25
ns
Figure 2
20
ns
VCC = 5.0 V
Figure 1
20
ns
th
Hold Time
5.0
ns
Figure 1
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SN74LS74A
AC WAVEFORMS
D*
1.3 V
1.3 V
th(L)
ts(L)
tW(H)
th(H)
ts(H) tW(L)
MODE SELECT – TRUTH TABLE
OPERATING MODE
INPUTS
SD
SD
D
OUTPUTS
Q
Q
Set Reset (Clear) *Undetermined Load “1” (Set) Load “0” (Reset)
L
H
X
H
L
H
L
X
L
H
L
L
X
H
H
H
H
h
H
L
H
H
l
L
H
* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then we cannot guarantee to meet the minimum level for VOH.
VCC = 5.0 V CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
tW (H) tW (L)
ts
Clock Clear, Set
Data Setup Time — HIGH Data Setup Time — LOW
Figure 1. Clock to Output Delays, Data Set-Up and Hold Times, Clock Pulse Width
SET CLEAR
Q Q
tW
1.3 V
1.3 V
tPLH 1.3 V
tPHL 1.3 V
tW
1.3 V
1.3 V
tPHL
1.3 V
tPLH
1.3 V
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LOW POWER SCHOTTKY
14 1 PLASTIC N SUFFIX CASE 646
14 1
SOIC D SUFFIX CASE 751A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
2.7 3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
0.25 0.4 0.35 0.5
V
IOL = 4.0 mA
V
IOL = 8.0 mA
VCC = VCC MIN, VIN = VIL or VIH per Truth Table
MILLIMETERS
1.3 V
1.3 V
CP
1
tPHL
fMAX
tPLH
Q 1.3 V
1.3 V
tPLH
tPHL
1.3 V
1.3 V
Q
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Publication Order Number: SN74LS74A/D
SN74LS74A
LOGIC DIAGRAM (Each Flip-Flop)
SET (SD)4 (10)
CLEAR (CD) 1 (13)
CLOCK 3 (11) D 2 (12)
Q 5 (9)
Q 6 (8)
LOGIC SYMBOL
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
20
µA
VCC = MAX, VIN = 2.7 V
40
0.1 0.2
mA VCC = MAX, VIN = 7.0 V
Input LOW Current
IIL
Data, Clock
Set, Clear
– 0.4 mA VCC = MAX, VIN = 0.4 V – 0.8
IOS
Output Short Circuit Current (Note 1)
G 0.100 BSC
2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.290 0.310 7.37
M ––– 10_ –––
7.87
10_
N 0.015 0.039 0.38 1.01
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VCC
Supply Voltage
TA
Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0
25
70
°C
IOH
Output Current – High
IOL
Output Current – Low
– 0.4 mA
8.0
mA
ORDERING INFORMATION
SN74LS74A
Dual D-Type Positive Edge-Triggered Flip-Flop
The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.