CS207-Spring 01 Digital Logic Design

CS207-Spring 01 Digital Logic Design Computer Science & Engineering

December, 2001 K. YETONGNON

UTEB 352

Selected Review questions

This problem set includes several exercises to help you study materials not covered by the first two exams. If you have any questions, send me an email (kokou@). Good luck on your review.

Solutions

Important : Review all problems and questions from Exam1, Exam2 and the first set of review questions ( the one you use to review for exam2).

The Final exam is cumulative (it covers materials from homeworks, project and previous exams). 50% of the exam will be devoted simple class note questions(these question can easily be answered if you review all class material (homeworks, project, previous exams).

A.State diagrams

Exercise 1

Draw a state diagram for a mealy type state machine specified as follows:

-Denote "a" the initial state of the machine

-set the initial output to the initial input (the input is presented to the machine bit by bit) -The output changes value only when three successive inputs have the same value and that value is opposite to the current output. For example, if the current output is 1 and the machine detects three consecutive 0 it changes the output to 0.

Repeat the above for a Moore type machine.

Answer:

Starting from an initial 0 input the sequence detector works as follows. S0 is the initial state. If the current output is 0, we will change the output to 1 if we detect 3 consecutive 1's. This is handled by states S1, S2 and S3. In S1 we wait for a 1 to move to state S2, where we are looking for a second 1. If we get 0, we go back to S1 and start all over and if we get a 1, we go to S3. In S3 we wait for the final third 1. If we get 0 instead, we go to S1 to start all over and if get 1, we go to a state where we are reading to detect an output change from 1 to 0. Detecting 3 consecutive 0 to change the output from 1 to 0 is symmetrical to what we have just done. This is handled by states S1', S2' and S3'.

Now you can adapt this solution to derive a state diagram for a Moore state machine.

Exercise 2

Draw a state diagram for a 3 bit UP/Down counter specified as. The counter has a an input U that determines the direction of the generated count sequence. When the control input U=1, the counter counts up in the sequence 0,1,2,3,4,5,6,7. When U=0, the counter counts down in the sequence 0,7,6,5,4,3,2,1

Anwer:

This exercise is quite easy, but you should note that there is no specific output. The transitions are labelled with the input values (0 to count down and 1 to count up). The state diagram is given by:

A.Analysis of clocked synchronous state machine

Exercises

Problem 7.17 on page 648 of text.

Problem 7.18 on page 648 of text.

Problem 7.19 on page 649 of text.

Answer:

These problems are similar to the discussion in the text book.

Review the analysis sections in your book. These problems are similar to the discussion in the text.

B.Design of clocked synchronous machine

Answer: Exercise 1 and 2 are straightforward. Go over the design steps given in text and your class notes. The solutions are very similar.