A 1-V 5.2-GHz CMOS Synthesizer for WLAN Applications

A 1-V 5.2-GHz CMOS Synthesizerfor WLAN ApplicationsGerry C.T.Leung and Howard C.Luong ,Senior Member,IEEEAbstract—A 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented.Novel circuit designs are demon-strated in the system for low-voltage applications including design of voltage-controlled oscillator and design of programmable di-vider.Implemented in a0.18-m CMOS process and operated at 1-V supply voltage,the synthesizer measures phase noise of 136dBc/Hz at a frequency offset of 20MHz and spur performance of less than 80dBc at an offset of 11MHz.The synthesizer dissipates 27.5mW from a single 1-V supply and occupies a chip area of 1.03mm 2.Index Terms—Clock generation,integer-,low power,low voltage,oscillator,phase-locked loop (PLL),receiver,synthesizer,transceiver,VCO,WLAN.I.I NTRODUCTIONOVER the last decade,single-chip integration using low-cost CMOS technology has become a major research area.Advanced CMOS processes have enabled implementation of high data rate wireless systems [1],[2].However,to ensure device reliability with the technology scaling and to maintain compatibility with digital circuits in mixed-signal systems,it is always desirable and still remains a challenge to design RF integrated circuits,in particular frequency synthesizers,with low supply voltages and low power consumption.On-chip voltage multipliers and dc-to-dc boost converters have been proposed to increase the low supply voltage for digital circuits to a higher voltage level to power analog circuits to maintain the same performance [3].However,such voltage converters would inevitably occupy large chip area,consume extra power,and contribute switching noise to the system.This is the main reason why novel analog design techniques suitable for low supply voltages are needed and have become more and more attractive.This paper presents novel architecture and design of a 1-V 5.2-GHz CMOS frequency prescaler and its integration to realize a 1-V 5.2-GHz fully integrated CMOS frequency synthesizer for WLAN 802.11a transceivers.II.S YNTHESIZER A RCHITECTUREBasic architectures to implement an RF frequency synthe-sizer includeinteger-,fractional-,and dual-loop.Among them,integer-architecture is the simplest,but the main prob-lems are its smaller reference frequency and high division ratioManuscript received January 8,2004;revised June 9,2004.This work was supported by the Hong Kong Innovation and Technology Fund under Grant ITS/033/02.The authors are with the Department of Electrical and Electronic Engi-neering,The Hong Kong University of Science and Technology,Clearwater Bay,Kowloon,Hong Kong (e-mail:eeluong@t.hk).Digital Object Identifier10.1109/JSSC.2004.835830of the divider in the feedback loop.On the other hand,be-cause the channel spacing of IEEE 802.11a is 20MHz,which is relatively wide,these problems are no longer concerns.As a consequence,integer-architecture is adopted for this synthe-sizer.Nevertheless,in order to be able to operate the synthesizer at a 1-V supply with low power consumption,high-frequency building blocks such as voltage-controlled oscillators and di-viders impose design challenge.Fig.1shows the system architecture of the proposed syn-thesizer targeting for WLAN 802.11a transceiver systems with the data rate as high as 54Mb/s [4].It comprises a quadrature voltage-controlled oscillator (QVCO)for generating in-phase and quadrature-phase outputs,a programmable divider,a phase-frequency detector (PFD),two charge pumps (CPs),and a third-order dual-path loop filter.With a reference frequency of 10MHz,the division ratio is from 498to 512in steps of 2to achieve a frequency step of 20MHz.A novel prescaler design is proposed based on the phase-switching technique to relax the speed requirement under low-voltage supply [5].Three digital bits are implemented to simultaneously select the division ratio in the prescaler and provide coarse frequency tuning to the QVCO to select channels in both the lower band (5.15–5.25GHz)and the middle band (5.25–5.35GHz).As a result,the QVCO can be designed with a small VCO gain()to ensure low phase noise and good spur performance under a low supply voltage.In addition,for smaller VCO gain,the on-chip capacitors in the loop filter can also be reduced to minimize the chip area provided that the resistors in the loop filter are scaled up accordingly to maintain the same zero and pole locations and thus the loop stability.III.C IRCUIT I MPLEMENTATIONA.Programmable Frequency DividerAs shown in Fig.1,the proposed programmable frequency di-vider is implemented based on the phase-switching approach to relax the requirement of digital circuits at a low-voltage supply and to minimize the power consumption because only one di-vide-by-2circuit needs to operate at the highest frequency.Suc-cessive asynchronous dividers work at lower frequencies and can be designed with smaller device sizes and smaller power consumption.B.Divide-by-2There are two main reasons why the design of the first fre-quency divider is the most critical and challenging compared to other building blocks in the synthesizer.First,the divider needs0018-9200/04$20.00©2004IEEEFig.1.Block diagram of the proposed prescaler and synthesizer.to be able to operate properly at the synthesizer ’s highest fre-quency (5.2GHz).Moreover,the divider needs to have an input frequency range at least as wide as the frequency tuning range of the QVCO to cover all the channels in the presence of process and temperature variation(500MHz).To realize a frequency divider with such stringent performance under low supply volt-ages and low power consumption,divider architecture using D-latches in a master –slave configuration is employed as shown in Fig.2[4].The sizes of the hold-transistor and evaluate-tran-sistor are designed tobem mandm m,respectively,to operate at 6-GHz range.Such design margin guarantees that the divider is able to work well under process variation.The PMOS loads are dynamically biased either in the linear region or in the cut-off region depending on the input clock signal level in order to extend the operating frequency of the divider.The current consumption of the divide-by-2is around 4mA.The maximum input frequency versus the input signal amplitude is illustrated in Fig.3.As the clock signals are from the QVCO outputs whose dc voltage is around the supply voltage,level shifters are required to bias properly the gates of the loading transistors and of the current sources.The divider can overcome the speed limitation problem and achieve high performance under 1-V supply voltage without using a voltage doubler.C.Divide-by-4Phase-switching operation is proposed to perform at a fre-quencyofratherthan or higher to enable the dig-ital circuits to work at lower frequencies to minimize their power dissipation.Backward-phase-selection scheme is also used to avoid glitches from happening during phase switching.How-ever,by using the conventional approach,the division step that is available by the programmable divider is larger [5].In order to relax the speed requirements of the phase-selection circuits and to achieve required division resolution,the divider outputs need to be designed to provide finer clock phases.An approach of using two divide-by-2circuits working in par-allel configuration is shown in Fig.4(a)[6].The total number of outputs of Divider-2a and Divider-2b is eight,but there are two possible output patterns as illustrated in Fig.4(b).This is because the initial outputs of the Divider-2a and Divider-2b can be either one or zero as depicted in Fig.5.Because Divider-2a and Divider-2b can only synchronize the input of Divider-1,the phase relation between I-channel of the Divider-2a and Di-vider-2b can be either 45or 135.Since the phase selection selects the output phases from P7to P0and then repeats again,one of the two possible patterns shown in Fig.4(b)would lead to incorrect phase switching and thus incorrect division ratio of the programmable divider.Extra circuits are therefore needed to detect such random behavior.The configuration of the high-frequency dividers together with phase-switching circuits in the proposed programmable divider is shown in Fig.6.As the phase-switching circuitis designed to operateat,a divide-by-4circuit is proposed to operate at a frequencyofas well.The divide-by-4used in the synthesizer has advantages over the conventional approach using a cascade of two divide-by-2dividers.First,if a parallel configuration is employed,one extradivider operatingatwould be required.The proposedLEUNG AND LUONG:A 1-V 5.2-GHz CMOS SYNTHESIZER FOR WLAN APPLICATIONS1875Fig.2.Schematic of the proposed divide-by-2circuit.Fig.3.Maximum input frequency versus minimum input amplitude of the proposed divider-by-2.approach can save the divider operatingat and thus save area.Second,there exists only one possible phase pattern for the divide-by-4.Operating as a ring oscillator,the divide-by-4circuit is injection-locked by the output signals of the previous divider.As a result,this injection-locked oscillator can oscillateat frequencyofwith only one unique phase pattern.In other words,no extra phase-detection circuit is required.The divide-by-4circuit is accomplished by cascading four D-latches as shown in Fig.6to generate eight clock phases that are 45out of phase from each other.The total phase shift is 360for oscillation.The transistor M1converts the input voltage of CLK to current to bias the input devices M3and M4.The negative transconductance cell formed by M5and M6isto hold the output value once CLKB is high.The current is fi-nally converted to the output voltage by the load M7and M8.Because the current is synchronized with the input signal CLK,the output value toggles based on the input values D and DB when CLK signal is active as shown in Fig.7.As such,a di-vide-by-4function is achieved.D.Phase-Switching CircuitsDue to the uncertainty of the delay of the flip-flops,glitches may happen during the phase selection,which would result in an incorrect division ratio [5].Backward-phase-selection scheme can solve the problem of glitches during the phase selection,but it would require the circuits to work at higher frequencies during the phase transitions in addition to careful design of the switching control [6].The proposed phase-selection circuitry,as illustrated in Fig.8,uses an 8-bit shift register to control the phase-selection circuit with only one of the input phases from the divide-by-4being selected.No glitch happens during tran-sition.A single-stage 8-to-1multiplexer is employed to shorten the delay from the input to the output.Even if the phase selection suffers from a finite rising time due to low-voltage operation,the phase can be switched successfully and correctly as long as the current stage of the phase-selection circuit is not turned off before the next stage is completely on.In the proposed design shown in Fig.8,the sensing PMOS transistor is included to ensure that this is the case.Fig.9depicts an example of the phase switching from Stage 1,PS[1],to Stage 2,PS[2],of the phase-selection circuit.When the “ready ”signal from PS[2]becomes 0because CLK 45and CLK 180are on,the “next_ready ”signal in PS[1]is also 0,and Stage 1is turned off.This illustrates that,during the phase transition,PS[1]is turned off after PS[2]is on,which allows a smooth phase transition.Simulation results1876IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.39,NO.11,NOVEMBER2004Fig.4.(a)Dividers in parallel configuration with eight output clock phases.(b)Two possible output pattern of the eight clockphases.Fig.5.Two possible output pattern of dividers in parallel configuration due to different initial status.verify that without the sensing transistor,the output of the phase-selection circuitry suffers from a serious problem with an unacceptably low swing during the phase switching as illustrated in Fig.10(a).The swing is limited because of the finite rising time and because of the intrinsic delay of the digital circuits under low-voltage supply.The problem is completely eliminated,as illustrated in Fig.10(b),by adding the sensing PMOS without increasing power consumption.E.Modulus-Control and Phase-Control CircuitsThe modulus-control circuit for the programmable divider in Fig.4is implemented using a combination of NOR gates as shown in Fig.11.Due to the high-speed requirement under low-voltage supply,pseudo design is employed for all logic gates.On the other hand,the phase-control circuit is imple-mented using eight D-latches as shown in the Fig.12with the output of the last stage being cross-coupled back to the input of the first stage.The phase shift is controlled by the outputs of the modulus-control circuit.F .Quadrature LC OscillatorFig.13shows the schematic of the quadrature LC os-cillator [7].It consists of two identical LC VCOs with negative-transconductancecellsand to com-pensate for the losses in the LC tanks.The LC VCOs are directlycoupled and cross-coupledbyand to achieve four outputs that are 90out of phase.The current consumption of the VCO is 13mA.The transconductance of the devices for the oscillator core and for the coupling transistors are 14mS and 16mS,respectively.Based on simulation results,the coupling ratio between the coupling transistors and oscillator core is at least 0.5to guarantee single-frequency oscillation.In the proposed design,the frequency tuning is achieved by both coarse tuning and fine tuning as shown in Fig.13.To achieve the required frequency tuning range of more than 200MHz with low supply and control voltages,p-n junctions and MOS capacitors are not used.Instead,the frequency tuning is based on varying the transconductance of the couplingtransistorsand [8].Employing this type of tuning,the inductance can be maximized for a given current consumption to increase the oscillating amplitude and thus toreduce the phase noise.Inaddition,and are inserted to achieve rail-to-rail frequency tuning with a low VCOgain.However,when the control voltage is in the middle of the supply,the VCO gain becomes nonlinear because the two transistors operate in the weak inversion.In order to compensate for this nonlinearity,the threshold voltage of the PMOS device is reduced to keep the device in strong inversion at the middle of the supply.The threshold voltage of a MOS transistor as a function of the bulk-source voltageis(1)whereis the threshold voltagewhen,is the body-effect coefficient,andis the surface potential at strong inversion.By biasing the bulk at a voltage larger than the source voltage,the threshold voltage can be decreased.However,this biasing scheme may result in a large amount of leakage current to the substrate.To overcome the problem,current-driven-bulk (CDB)technique is proposed to turn on the p-n junction from the source to the bulk for the PMOS with limited current flow [9].With the CDB technique,the threshold voltage can be reduced,and the PMOS transistor can work in the strong inversion in the voltage range around half of the supply voltage (0.5V).LEUNG AND LUONG:A 1-V 5.2-GHz CMOS SYNTHESIZER FOR WLAN APPLICATIONS1877Fig.6.(a)Schematic of programmable divider.(b)Schematic ofdivide-by-4.Fig.7.Simulation result of divide-by-4.The coarse frequency tuning is employed to minimize the VCO gain by using three binary-weighted channel-selectionbits together with the channel-selectiontransistorsand as shown in Fig.13[10].As a result,the is smallerwhile the total tuning range can still cover the interested band asshown in Fig.14.Such a small VCO gain is good for noise and spurious performance of the synthesizer.The offset adjustment for the discrete frequency step can be calibrated by varying the current source M7.The oscillator is designed to work in the current-limited regime to achieve low phase noise.The sideband noise of the oscillators is mainly limited by the loss in the tank.For higher loss,a larger transconductance is needed to be able to compen-sate and sustain the loop gain for a stable oscillation.Therefore,it is always beneficial to use a tank with the quality factor()as high as possible.One solution to increasethe of the tank to improve the phase noise for a given power or to minimize the power for a given phase noise is to use bond wires in placeof on-chip inductors [11].Sincetheof bond wires can be as high as 40,the VCO performance could be significantly improved.However,such a solution is not attractive due to the problems with controllability,repeatability,and reliability of the bond wires.For high-frequency operation,the required inductance is small in which a small number of turns of the planar inductor can be realized.As such,the metal loss as well as substrate loss can be less due to the fact that the length of metal is shorter and the overlapping area between inductor and substrate is smaller.Moreover,the advanced CMOS process provides thick top metal which can also benefit the quality factor of the on-chip inductor.Therefore,the on-chip inductor is considered for use in the oscillator design.1878IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.39,NO.11,NOVEMBER2004Fig.8.Architecture and schematic of the proposed phase-selectioncircuitry.Fig.9.Timing diagram of the phase-selectioncircuitry.Fig.10.Output of the phase selection circuit during phase switching.(a)Without sensing PMOS.(b)With sensing PMOS.G.Loop Filter,Charge Pumps,and PFDThe loop filter is constructed based on a dual-path loop filter [12]to reduce the on-chip capacitance to about 70pF andthusFig.11.Schematic of the modulus-controlcircuit.Fig.12.Schematic of the phase-control circuit.minimize the chip area.The design parameters used in the loop filter are listed in Table I.The loop filter is designed to main-tain the outputs of the charge pumps at the same potential to minimize the charge-sharing problem to reduce spurious tones at the output of the synthesizer.The complementary outputs of UP/UPB,and DOWN/DOWNB generated by the PFD are de-signed to have some finite rise time and fall time so that the sink and source currents to the loop filter can be well matched.LEUNG AND LUONG:A 1-V 5.2-GHz CMOS SYNTHESIZER FOR WLAN APPLICATIONS1879Fig.13.Schematic of theQVCO.Fig.14.QVCO frequency tuning with both fine and coarse tuning.TABLE IC OMPONENT P ARAMETERS U SED FOR THE SYNTHESIZERIV .E XPERIMENTAL R ESULTSThe proposed synthesizer has been fabricated in a0.18-m six-metal CMOS process.Fig.15shows themicrophotographFig.15.Chip photo of the proposed 5.2-GHz synthesizer for WLAN.of the fabricated chip.The core chip area is 1.03mm .The total power consumption under a 1-V supply is 27.5mW.A.Measurement of the QVCOThe measured tuning range of the QVCO is plotted in Fig.16.Together with the coarse tuning by the three channel-selection bits,the QVCO achieves a total frequency tuning range morethan 200MHz with thegainbeing around 75MHz/V .As expected,for each setting of the digital bits,the tuning range of the QVCO is quite linear over the whole operation region of the dual-path loop filter.The lump-element model,which is used to characterize the inductor,is depicted in Fig.17.At high frequencies,magnetic coupling should be taken into account.Lenz ’s law indicates that eddy current is generated under influence of magnetic flux,which tends to oppose the original field.The resultant induc-tance of the on-chip inductor is therefore reduced while the se-1880IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.39,NO.11,NOVEMBER2004Fig.16.Measured tuning range of theQVCO.Fig.17.Lumped-element model of the inductor including magnetic coupling from substrate.ries resistance is effectively increased.Moreover,these changes are frequency dependent.To take into account this phenomenon to achieve more accurate model and simulation,two extra ele-ments,inductanceandresistance ,are added inthe -equivalent model as illustrated in Fig.17.Fig.18shows the measurement results of the on-chip inductor,from which the in-ductance is measured to be around 1nH and the quality factor is about 7at 5.2GHz.A very good fitting for the inductor is achieved thanks to the use of the complicated model.B.Measurement of the SynthesizerTo overcome process variation,the VCO employs 2-bit switched-capacitor array (SCA)for tuning.The nominal center frequency of the QVCO is shifted from 5.2to 6.0GHz due to inaccurate modeling and over-estimation of the parasitic capacitance.By turning on the SCA,the operating frequency is shifted down to around 5.5GHz,resulting in a coarse tuning range of over 500MHz.To test the performance of the synthesizer,the reference is set at 11MHz for all the closed-loop measurements.With the robustness of the proposed architecture for the programmable divider,the synthesizer works properly even with a supply voltage as low as 0.85V .The output spectrum of the QVCO in the locked state is shown in Fig.19.To verify the functionality of the programmable divider,the division ratio is set to be 498.The outputfrequencyFig.18.Measured results of the on-chip inductance for the WLANsynthesizer.Fig.19.Measured output spectrum of the synthesizer.is measured to be 5.478GHz with a reference clock at 11MHz.The prescaler works properly without any glitch problem.From the output spectrum,the spur performance is better than 80dBc at an 11-MHz frequency offset from the carrier.The phase-noise performance of the frequency synthesizer is shown in Fig.20.The measured phase noise at a 20-MHz offset is 136dBc/Hz.The in-band phase noise is around 65dBc/Hz while the designed in-band phase noise of the syn-thesizer is expected to be 75dBc/Hz.The noise degradation is mainly contributed by the phase noise of the signal generator.With a better reference signal,either from a crystal or from a signal generator followed by a frequency divider,the in-band phase noise could and should be significantly improved.For switching from the first channel to the last channel,the settling time is measured to be about51s as shown in Fig.21.Due to the scope ’s limited resolution,the frequency accuracy for the settling cannot be measured directly,but it can be roughly estimated to be around 100kHz.LEUNG AND LUONG:A 1-V 5.2-GHz CMOS SYNTHESIZER FOR WLAN APPLICATIONS 1881TABLE IIS UMMARY AND C OMPARISON OF THE P ROPOSED S YNTHESIZER ’S PERFORMANCEFig.20.Phase-noise measurement of thesynthesizer.Fig.21.Measured result of settling time of the synthesizer.The measured performance of the proposed synthesizer is summarized in Table II together with that of the most recent state-of-the-art synthesizers for comparison.V .C ONCLUSIONA 1-V 5.2-GHz synthesizer has been demonstrated in a stan-dard0.18-m CMOS technology.Several design techniques have been proposed to achieve robust performance for the prescaler and for the synthesizer even when the supply is as low as 0.85V .At 1V ,the phase noise of the whole synthesizer is measured to be 136dBc/Hz at 20-MHz frequency offset.In addition,the spurious tone is measured to be less than 80dBc at 11-MHz offset.The synthesizer can settle within51s while consuming 27.5mW and occupying an active chip area of 1.03mm .R EFERENCES[1]T.H.Lee,H.Samavati,and H.R.Rategh,“5-GHz CMOS wirelessLANs,”IEEE Trans.Microwave Theory Tech.,vol.50,pp.268–280,Jan.2002.[2]P.Zhang et al.,“A direct conversion CMOS transceiver for IEEE802.11a WLANs,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers ,Feb.2003,pp.354–355.[3]G.Dehng,C.Yang,J.Hsu,and S.Liu,“A 900-MHz 1-V CMOSfrequency synthesizer,”IEEE J.Solid-State Circuits ,vol.35,pp.1211–1214,Aug.2000.[4]G.C.T.Leung and H.C.Luong,“1-V 5.2-GHz 27.5-mW fully-inte-grated CMOS WLAN synthesizer,”in Proc.Eur.Solid-State Circuits Conf.(ESSCIRC),Sept.2003,pp.103–106.[5]J.Craninckx,“A 1.75-GHz/3-V dual-modulus divide-by-128/129prescaler in 0.7- m CMOS,”IEEE J.Solid-State Circuits ,vol.31,pp.890–897,July 1996.[6]K.Shu,E.Sanchez-Sinencio,J.Silva-Martinez,and S.Embabi,“A2.4-GHz monolithic fractional-N frequency synthesizer with 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in-tegrated CMOS dual-loop frequency synthesizer,”IEEE J.Solid-StateCircuits,vol.37,pp.1012–1020,Aug.2002.[13]I.Bouras and A.Yamanaka et al.,“A digitally calibrated5.15–5.825GHz transceiver for802.11a wireless LAN’s in0.18 m CMOS,”inIEEE Int.Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers,Feb2003,pp.352–353.[14] D.Su et al.,“A5GHz CMOS transceiver for IEEE802.11a wirelessLAN,”IEEE J.Solid-State Circuits,vol.37,pp.1688–1694,Dec.2002.[15] F.Herzel,F.Fischer,and H.Gustat,“An integrated CMOS RF synthe-sizer for802.11a wireless LAN,”IEEE J.Solid-State Circuits,vol.38,pp.1767–1770,Aug.2003.Gerry C.T.Leung received the B.S.and M.S.degrees in electrical and electronics engineeringfrom the Hong Kong University of Science andTechnology(HKUST),Hong Kong,in2001and2003,respectively.He was engaged in the development of RF andhigh-speed clock systems with Innovative SystemCorporation Limited in2003.Since2004,he hasbeen with ON Semiconductor Ltd.,Hong Kong,as an IC Design Engineer.His research interestsare in high-speed high-performance analog and RF integratedcircuits.Howard C.Luong(S’88–M’91–SM’02)receivedthe B.S.,M.S.,and Ph.D.degrees in electricalengineering and computer sciences(EECS)from theUniversity of California at Berkeley in1988,1990,and1994,respectively.Since September1994,he has been with theElectrical and Electronics Engineering faculty at theHong Kong University of Science and Technology,where he is currently an Associate Professor.In2001,he took a one-year sabbatical leave to workwith Maxim Integrated Products,Sunnyvale,CA,on wireless products.His research interests are in high-performance RF,analog, and mixed-signal integrated circuits and systems for wireless communication and portable applications.He has been involved in various professional activities internationally.Prof.Luong served as an Associate Editor for the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS II(TCAS II)from1999to2002.He received the Fac-ulty Teaching Excellence Appreciation Award from the School of Engineering of Hong Kong University of Science and Technology in1996,1997,and2000.。