L1119L-33-TN3-O-T中文资料

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艾特顿199333产品说明书

Eaton 199333Eaton Moeller® series U-PKZ0 Undervoltage release PKZ0(4), PKE, AC, 120 V 60 Hz, Push in terminalsGeneral specificationsEaton Moeller® series U-PKZ0 Accessory Undervoltage Release199333U-PKZ0(120V60HZ)-PI401508197417768 mm 91 mm 24 mm 0.134 kgCE Marked RoHS conformCannot be combined with A-PKZ0 shunt releaseProduct NameCatalog Number Model CodeEANProduct Length/Depth Product Height Product Width Product Weight Compliances Catalog Notes0,7- 0,35 x Uc3 VA, Coil in a cold state and 1.0 x Us5 VA, Pull-in power, Coil in a cold state and 1.0 x Us0 VMotor safety switch0.85 - 1.1 V x Uc0 V42 V0 V20 - 1424 V250 V3 VA, Coil in a cold state and 1.0 x UsEMERGENCY STOP or EMERGENCY switching-off device in accordance with IEC/EN 60204 when combined with circuit breaker55 °C480 V120 V Save time and space thanks to the new link module PKZM0-XDM32ME Motor Starters in System xStart - brochureProduct Range Catalog Switching and protecting motorsSwitching and protecting motors - catalogDA-DC-00004316.pdfDA-DC-00004917.pdfDA-DC-00004916.pdfDA-DC-00004913.pdfDA-DC-00004887.pdfDA-DC-00004889.pdfDA-DC-00004888.pdfDA-DC-00004881.pdfDA-DC-00004919.pdfDA-DC-00004918.pdfDA-DC-00004880.pdfDA-DC-00004912.pdfDA-DC-00004885.pdfeaton-manual-motor-starters-undervoltage-u-pkz0-accessory-dimensions.epsETN.U-PKZ0(120V60HZ)-PI.edzIL03407011ZIL122024ZUWIN-WIN with push-in technologya_pkz_pi.stpa_pkz_pi.dwgDrop-out voltagePower consumption, sealing, 60 HzPower consumption, pick-up, 50 HzRated control supply voltage (Us) at AC, 50 Hz - min Suitable forPick-up voltageRated control supply voltage (Us) at DC - minRated operational voltage (Ue) at AC - minRated control supply voltage (Us) at AC, 50 Hz - max Terminal capacity (solid/stranded AWG)Rated operational voltage (Ue) at DC - minRated operational voltage (Ue) at DC - maxPower consumption, sealing, 50 HzSuitable asAmbient operating temperature - maxRated operational voltage (Ue) at AC - maxRated control supply voltage (Us) at AC, 60 Hz - min BrochuresCatalogsCertification reports Declarations of conformityDrawingseCAD modelInstallation instructions Installation videosmCAD modelEaton Corporation plc Eaton House30 Pembroke Road Dublin 4, Ireland © 2023 Eaton. All Rights Reserved. Eaton is a registered trademark.All other trademarks areproperty of their respectiveowners./socialmedia5 VA, Pull-in power, Coil in a cold state and 1.0 x Us 0 V-25 °C120 V Motor protective circuit-breakerSpring clamp connectionACPower consumption, pick-up, 60 HzRated control supply voltage (Us) at DC - max Ambient operating temperature - min Rated control supply voltage (Us) at AC, 60 Hz - max Used withNumber of contacts (normally open contacts)Electric connection type Number of contacts (normally closed contacts)Number of contacts (change-over contacts)Voltage type。

(整理)国内外不锈钢焊条对照表

SAFINOX
E1-26-21Mo2-16 A412
RCND
25.20
E2-16-35Mo3Mn4W3Nb-15 A607
Nicrex 330
中国 GB E1-13-16 E1-13-15
E00-19-10-16
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韩国比利时
瑞典
国际标准化组织
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号 HYUNDAI ARCOS ESAB AVESTA
R347
E19.9NbLAR Nicrex
SAFINOX
A132 E19.9NbR
NDR
EZ19.9NbLR23 RCN 18.8Nb
Chromoid
1
Nicrex
NDL A137 E19.9Nb B Chromoid
SAFINOX BCN 347
2
A202
E19.12.3RMP E19. 12.3R
A302 E23.12R
RCN
24.12
E1-23-13Mo2-16 A312 E23.12.2LR
EZ23.12.3LR23
SAFINOX
E2-26-21-16
A402 E25.20R
RCN
25.20
E2-26-21-15
SAFINOX A407 E25.20R Nicrex 1 EZ25.20 B20 BCN 310
R26
E0-18-12Mo2-15
A20 E19 123 Phoeni 4402Kb 7 B20+ x 4403K
FOX AS4 TS-309
E0-19-13Mo3-16
A24 E19 2 134LR26
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33099资料

Document Number: MC33099Rev. 6.0, 1/2007Freescale Semiconductor Technical Data© Freescale Semiconductor, Inc., 2007. All rights reserved.Adaptive Alternator Voltage RegulatorThe 33099 is designed to regulate the output voltage in diode-rectified alternator charging systems common to automotiveapplications. The 33099 provides either an analog or digital fixed frequency duty cycle (ON/OFF ratio) control of an alternator’s field current. Load Response Control (LRC) of the alternator field current is accomplished by selecting the duty cycle for prevailing engine conditions to eliminate engine speed hunting and vibrations caused by abrupt torque loading of the engine owing to sudden electrical loads being applied to the system at low engine RPM. Four LRC rates are selectable by connecting pins 7 and 8 to ground.The 33099 uses a feedback voltage to establish an alternator field current that is in harmony with system load currents. The output voltage is monitored by an internal voltage divider scheme and compared to an internal voltage ramp referenced to a bandgapvoltage. This approach provides precision output voltage control over a wide range of temperature, electrical loads, and engine RPM.Features•External High-Side MOSFET Control of a Ground-Referenced Field Winding•LRC Active During Initial Start •V set at ±0.1 V @ 25°C•<0.1 V Variation Over Engine Speeds of 2,000 to 10,000 RPM •<0.2 V Variation Over 10% to 95% of Maximum Field Current •Controlled MOSFET and Field Flyback Diode Recovery Characteristics for Minimum RFI•Trimmed Devices Available at 14.6 V and 14.8 V (typical) V set •Pb-Free Packaging Designated by Suffix Code EGFigure 1. 33099 Simplified Application DiagramVOLTAGE REGULATOR33099ORDERING INFORMATIONDeviceTemperature Range (T A )PackageMC33099DW/R2-40°C to 125°C16 SOICWMC33099CDW/R2MCZ33099EG/R216 SOICW (Pb-FREE)MCZ33099CEG/R233099 Figure 2. 33099 Simplified Internal Block DiagramAnalog Integrated Circuit Device DataAnalog Integrated Circuit Device Data 33099PIN CONNECTIONSPIN CONNECTIONSFigure 3. 33099 Pin ConnectionsTable 1. PIN Function DescriptionPin NumberPin Name Formal Name Definition1GATE GATE DRIVE Controls the GATE of the MOSFET to control the alternator field current.2BAT BATTERY Primary power connection to the system battery.3GND GROUND Source lamp current and digital ground.4LAMP DRAIN LAMP DRAIN Controls the Fault Lamp current.5LAMP GATE LAMP GATE Controls the Fault Lamp internal driver as an override function.6IGN IGNITION Controls the ON or OFF function of the regulator.78LRC2LRC1LOAD RESPONSE CONTROL 2LOAD RESPONSE CONTROL 1Inputs for selecting the LRC rate.9AGND ANALOG GROUNDGround connection for analog circuitry.10REMOTEREMOTE Provides for external Kelvin connection to system battery.11, 14NC NO CONNECT No internal connection to this pin.12LRC TEST LOAD RESPONSE CONTROL TEST Provides acceleration of LRC rate for testing.13PHASE FILTER PHASE FILTER Provides access to Phase Resistive Divider for External Phase Filter capacitance.15PHASE PHASE SENSE INPUTInput for phase voltage.16SOURCESOURCECoupled to source of MOSFET to provide a GATE voltage reference and to monitor for source shorts to ground.Analog Integrated Circuit Device Data33099ELECTRICAL CHARACTERISTICS MAXIMUM RATINGSELECTRICAL CHARACTERISTICSMAXIMUM RATINGSTable 2. Maximum RatingsAll voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.RatingSymbolValueUnitELECTRICAL RATINGS Power Supply VoltageLoad Dump Transient Voltage (1)Negative Voltage (2)V BAT +V MAX -V MIN2440-2.5VESD VoltageHuman Body Model (3)Machine Model (3) (4)V ESD1V ESD2±2000±200V THERMAL RATINGSOperating Junction Temperature T J 150°C Operating Ambient Temperature Range T A - 40 to 125°C Storage Temperature RangeT STG- 45 to 150°CPower Dissipation and Thermal Characteristics Maximum Power Dissipation @ T A = 125°C Thermal Resistance, Junction-to-AmbientP D R ΘJA 64085mW °C/W Peak Package Reflow Temperature During Reflow (5), (6)T PPRTNote 6°CNotes1.125 ns wide square wave pulse.2.Maximum time = 2 minutes.3.ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, R ZAP = 1500 Ω). ESD2 testing is performed inaccordance with the Machine Model (C ZAP = 200 pF, R ZAP = 0 Ω).4.ESD2 voltage capability of PHASE FILTER pin is greater than 150 V. All other device pins are as indicated.5.Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.6.Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL),Go to , search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.Analog Integrated Circuit Device Data 33099ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSTable 3. Static Electrical CharacteristicsCharacteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, - 40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbol MinTypMaxUnit Regulation Voltage @ 50% Duty Cycle V rem = V set or V rem < V Trem MC33099V rem = V set or V rem < V Trem MC33099CV SET14.5514.314.814.615.0514.85VRegulation Voltage Range 10% < DC < 95%DVSET–210300mVRegulation Voltage Temperature Coefficient (TC) V rem = V bat or V rem < V TremTC (V SET )-13-11-9mV/°CPower Up/Down IGN Threshold Voltage V TIGN 0.91.251.6V Operating Drain Current (Ignition ON) V ign > V Tign , V rem = V ph = V set , T A = 25°CV ign > V Tign , V rem = V ph = V set , -40°C ≤ T A ≤ 125°C I Q1(ON)I Q2(ON)––6.56.58.08.4mAStandby Drain Current (Ignition OFF)V ign < V Tign , V ph = 0 V, V rem = V bat = 12.6 V, T A = 25°CV ign < V Tign , V ph = 0 V, V rem = V bat = 12.6 V, -40°C ≤ T A ≤ 125°C I Q1(OFF)I Q2(OFF)––0.61.0 1.53.4mARemote Loss Voltage Threshold V TREM 4.2 4.5 4.8V Phase Detection Threshold Voltage V TPH 3.754.04.25V Undervoltage Threshold Voltage V set = 14.8 typical MC33099V set = 14.6 typicalMC33099CV TUV10.910.3511.3510.9511.611.55VOvervoltage Threshold Voltage V set = 14.8 typical MC33099V set = 14.6 typicalMC33099CV TOV16.1515.816.6516.417.1517.0VOvervoltage Threshold Voltage TC TC(V TOV )–-12.4–mV/°C Load Dump Threshold Voltage V set = 14.8 typical MC33099V set = 14.6 typicalMC33099CV TLD18.918.4519.2519.1519.819.85VLoad Dump Threshold Voltage TC TC(V TLD )–-14.3–mV/°C Secondary Regulation V set = 14.8 typical MC33099V set = 14.6 typical MC33099CV SET218.017.6518.518.1518.818.75VSecondary Regulation TCTC(V SET2)–-13.4–mV/°C Secondary Load Dump Threshold Voltage V set = 14.8 typical MC33099V set = 14.6 typicalMC33099CV T L D223.523.52423.852524.65VSecondary Load Dump Threshold Voltage TCTC(V T L D2)–-17.9–mV/°CAnalog Integrated Circuit Device Data33099ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSLamp Drain Short Circuit Threshold Voltage (7)V T D SC 1.8 2.25 2.85V Lamp Drain Short Circuit Current I DSC 2.02.53.0Amps Lamp Drain ON Voltage I lamp = 0.4 AV D(SAT)–0.3 2.5VLamp Drain-to-GATE Clamping Voltage V DG –48.4855V Lamp GATE Override ResistanceR LG – 4.6–k ΩLamp Driver Thermal Shutdown Temperature Limit (7)T LIM –185–°C GATE Drive Source Current I PU 240300340µA GATE Drive Sink CurrentI PD 400480560µA GATE Drive GATE-to-Source Clamping Voltage V GS 101215V Minimum Charge Pump GATE Drive Voltage V bat = V source = V setV G(MIN)21.523.4–VSource Short Circuit Threshold Voltage V TSSC 1.852.32.75V Remote Input Resistance V rem = V setR REM–68–k ΩPhase Input Resistance V ph = V setR PH–60–k ΩIGN Input Pull-Down Current V ign = 1.25 V I IGN407390µALRC Input Current V lrc = 0 VI LRC354555µANotes7.Not 100% tested.Table 3. Static Electrical Characteristics (continued)Characteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, - 40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbol Min Typ Max UnitAnalog Integrated Circuit Device Data33099ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSTable 4. Dynamic Electrical CharacteristicsCharacteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, - 40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted.Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbol MinTypMaxUnit Duty Cycle Regulation Output Frequency f OSC / 256F DC300375440HzPhase Rotation Detection Frequency F 144.284953.8Hz Low / H igh RPM Transition Phase Frequency F 2267.5296325Hz GATE Duty Cycle at Startup and WOT f ph > f 2DC START3031.2534.5%Minimum GATE LRC Duty Cycle f ph < f 2DC (LRC)MIN2931.2533.5%Minimum GATE Duty Cycle V bat > V reg(max)DC MIN2.13.13.3%LRC Increasing GATE Duty Cycle Rate Low RPM Mode (f ph < f 2)LRC1 at GND, LRC2 at GND LRC1 Open, LRC2 at GND LRC1 at GND, LRC2 Open LRC1 Open, LRC2 Open High RPM Mode (f ph > f 2)R LRC1R LRC2R LRC3R LRC4R LRC (MAX)–––––9.3112.4518.7137.42616–––––%/sIgnition Turn OFF Delay (Lamp ON)T I D (OFF)–10.2–ms Lamp Short Circuit ON Polling Frequency F LSC –98.6–Hz Lamp Short Circuit ON Duty Cycle DC L – 1.56–%Lamp OFF Polling Frequency F L (OFF)–98.6–Hz Lamp Polling OFF Duty CycleDC L (OFF)– 1.56–%Field Short Circuit ON Polling Frequency F F SC –98.6–Hz Field Short Circuit Polling ON Duty CycleDC F–1.56–%Analog Integrated Circuit Device Data33099FUNCTIONAL DESCRIPTION INTRODUCTIONFUNCTIONAL DESCRIPTIONINTRODUCTIONThe 33099 is specifically designed for regulation of an automotive system voltage using diode-rectified alternator charging systems commonly found in automotiveapplications. The 33099 provides either an analog or digital duty cycle control of an ON/OFF ratio of an alternator field current at a fixed frequency. This provides for a LoadResponse Control (LRC) of the alternator field current at low engine RPM to eliminate engine speed hunting and vibration owing to abrupt torque loading of the engine when a sudden electrical load is applied to the system. Four LRC rates are selectable using a combination of pins 7 and 8 being connected to ground.The 33099 provides a regulated voltage feedback system to activate the alternator field current in response to system load current. The output voltage is monitored by an internal voltage divider scheme and compared to an internal voltage ramp referenced to a bandgap voltage. The 33099 regulates the system voltage to 14.8 V for the DW suffix and to 14.6 V for the CDW suffix by generating a pulse width modulation (PWM) voltage waveform at the GATE of an externalMOSFET to provide an average alternator field coil current as a function of the internal voltage comparison.Analog Integrated Circuit Device Data 33099TYPICAL APPLICATIONSINTRODUCTIONTYPICAL APPLICATIONSINTRODUCTIONThe 33099 is an alternator voltage regulator designed with internal level shifting resistors to control the voltage in a 12 V automotive system that uses a three-phase alternator with a rotating field winding. The system shown in Figure 4 includesan alternator with its associated field coil, stator coils and rectifiers, an automotive battery, a fault indicator lamp, an ignition switch, a field flyback diode, and the 33099.Figure 4. 33099 Simplified ApplicationThe 12 V system voltage (V BAT ) is connected to a REMOTE input by a remote wire, which provides the IC regulator with an external Kelvin connection directly to the battery to provide REMOTE voltage, V rem . The systemvoltage at the BAT pin is also sensed by an internal Local IC connection as Local voltage V l . The Local connection is provided in the event the remote wire or remote connection becomes faulty such as being resistive, an open, or shorted to ground.The PHASE input is normally connected to a tap on one corner of the alternator's stator winding, which provides an AC phase voltage (V ph ) for the IC to determine the rotational frequency (f ph ) of the alternator rotor. Two frequencycomparators (F1 and F2) monitor voltage V ph to determine a phase rotation detection frequency (f 1) and a Low/ H igh RPM transition phase frequency (f 2), respectively. A PHASE FILTER pin is provided for externally providing a filter capacitance for filtering phase input noise.The regulated DC system set voltage (V set ) is achieved by employing feedback to compare a ratioed value of V set to an internal IC bandgap voltage reference having a negative temperature coefficient (TC). The GATE drive of an external N-channel MOSFET is regulated by the IC to control the field current in the alternator field coil as an alternating ON or OFF state dependent on load current conditions affecting voltage V set . The external MOSFET receives GATE-to-sourcevoltage drive from between the GATE and SOURCE output pins of the IC. The GATE-to-source voltage is a Pulse WidthAnalog Integrated Circuit Device Data33099TYPICAL APPLICATIONSModulated (PWM) waveform having a variable ON / O FF duty cycle ratio that is determined by an analog or a digital duty cycle control circuitry that responds to variations in thesystem voltage due to variations in system load current. The PWM waveform has a duty cycle regulation output frequency of about 395 Hz (f dc ) defined by an 8-bit division of an internal 101 kHz oscillator clock frequency (f osc ). The GATE voltage at the GATE pin is due to a charge pump GATE voltage (V g ) generated by voltage multiplication using an internal charge pump voltage regulator. The high GATE-to-source voltage applied to the external MOSFET during the ON cycle of the PWM waveform minimizes a low drain-to-source ONresistance (R DS(ON) ) and associated drain-to-source voltage V d(SAT) to maximize the field current while minimizing the associated power dissipation in the MOSFET.A unique feature of the 33099 is the combinational use of analog and digital duty cycle controllers to provide a Load Response Control (LRC) duty cycle function when rotor frequency f ph is less than frequency f 2. A classic analog duty cycle function is provided at the GATE output whenfrequency f ph is greater than frequency f 2. During the LRC mode when f 1 < f ph < f 2, a sudden decrease in the system voltage due to a sudden increase in system load current will cause the analog duty cycle to rapidly increase to as great as 100%. However, the LRC circuitry causes the digital duty cycle to increase to 100% at a controlled predetermined LRC rate and overrides the analog duty cycle. Thus the alternator response time is decreased in the LRC mode and prevents the alternator from placing a sudden high torque load on the automobile engine during this slow RPM mode. This can occur when a high current accessory is switched on to the 12 V system, producing a sudden drop in system voltage. When frequency f ph is greater than frequency f 2, the slow LRC response is not in effect and the analog duty cycle controller controls the PWM voltage waveform applied to the external MOSFET to regulate the system voltage. By selectively coupling the LRC1 and LRC2 pins to ground or leaving them open, the user can program four different LRC rates (R lrc1-R lrc4) from 9.37%/sec to 37.4%/sec. During an initial ignition ON and engine start-up, the LRC rate is also in effect to minimize alternator torque loading on the engine during start, even when a Wide Open Throttle (WOT) condition (f ph > f 2) occurs.An internal N-Channel MOSFET is provided on the IC to directly drive lamp current as a fault indicator. The fault lamp is connected between the low side of the ignition switch and the LAMP DRAIN pin of the IC. A fault is indicated during an undervoltage battery condition when frequency f ph is greater than frequency f 2, during an overvoltage battery condition, and when frequency f ph is less than frequency f 1. Frequency f ph < f 1 when an insufficient alternator output voltage results or a slow or non-rotating rotor occurs due to a slipping or broken belt. An external LAMP GATE pin is also provided for the internal lamp driver to allow the user to override the internal IC fault logic and externally drive the internal lamp drive MOSFET.When a loose wire or battery pin corrosion causes the Remote voltage to decrease but is not a Remote Open condition, the system voltage will increase, causing anovervoltage Lamp fault indication, and is regulated at a secondary value of about 18.5 V.During a system load dump condition, load dumpprotection circuitry prevents GATE-to-source drive to the external MOSFET and to the internal lamp drive MOSFET. This ensures that neither the field current nor the lampcurrent is activated during load dump conditions. A drain-to-GATE voltage clamp is also provided for the internal lamp driver for further protection of this driver during load dump.An ignition pin (IGN) is provided to activate the regulator from the standby mode into a normal operating mode when the ignition switch is ON and an ignition voltage (V ign ) is greater than a power up/down ignition threshold voltage (V Tign ). When the ignition switch is OFF, voltage V ign is less than voltage V Tign , and the regulator is switched into a low current standby mode, when frequency f ph < f 1. The IGN pin can either be coupled to the low side of the ignition switch or to the low side of the lamp. When the IGN pin is connected to the low side of the lamp, the lamp must be shunted by a resistor to ensure that ignition ON is sensed, even with an OPEN lamp fault condition. When the lamp in ON, lamp current is polled OFF periodically at an ignition pollingfrequency in order for the IGN pin to periodically sense that the ignition voltage is high even though the lamp is ON. An ignition input pull-down current (I ign ) is provided to pull voltage V ign to ground when the IGN pin is OPEN or terminated on a high resistance.Two ground pins are provided by the 33099 to separate sensitive analog circuit ground (AGND) from noisy digital and high-current ground (GND).ALTERNATOR REGULATOR BIASING AND POWER UP/DOWNThe biasing of the regulator is derived from the BAT pin voltage V bat . In the normal operating mode when the ignition switch is ON and voltage V ign is greater than V Tign (about 1.25 V), a 5.0 V V DD voltage regulator biases the IC logic and provides bias to a bandgap shunt voltage regulator. The bandgap regulator maintains a reference voltage (V ref ) of approximately 2.0 V with an internal negative temperature coefficient (-TC) as well as a 1.25 V Zero TemperatureCoefficient (OTC) reference voltage. Additional bias currents and reference voltages, including a charge pump GATE voltage V g , are also generated from voltage V bat . Thetypically ignition ON drain current (I Q1(on) ) is about 6.5 mA at 25°C. When the ignition switch is OFF and voltage V ign is less than V Tign , the regulator is in a low current standby mode, having a standby drain current of about 0.7 mA (I Q1(off) ) at 25°C. During the sleep mode, some internal voltage regulators and bias currents are either terminated or minimized. However, the V DD regulator and the bandgap voltage regulator continue to maintain voltages V DD for the logic, the 2.0 V V ref , and the 1.25 V reference voltage. In addition, all logic is reset in the standby mode.After switching the ignition switch to the ON position, voltage V ign will exceed voltage V Tign , causing comparator C ign to switch states, providing an ignition-ON signal to the Ignition Delay circuit. After an Ignition start Delay Time of 500 ms, the Ignition Delay circuit activates additional currentAnalog Integrated Circuit Device Data 33099TYPICAL APPLICATIONSfor the V DD regulator and activates all other voltageregulators and bias currents. After engine start, the LRC mode is activated, independent of the phase frequency or independent of a Wide Open Throttle condition. When the battery system voltage increases to V set , the regulator resumes the normal operational mode. After switching the ignition switch to the OFF position, voltage V ign decreases below voltage V Tign , causing the comparator C ign to provide an ignition-OFF signal to the Ignition Delay Circuit. After phase frequency f ph < f 1 due to ignition turn OFF, supply currents and voltages are reduced in the regulator to provide the standby drain current drain. However, voltage V DD for logic and voltage V ref for reference voltages remain active to be able to sense an ignition input voltage.In some applications, the ignition input is connected to the low side of the fault lamp as shown in Figure 4, page 9. When the lamp driver circuitry is generating a lamp ON signal, a lamp polling signal causes the Lamp Drain output to be periodically GATED OFF. As a result, voltage V ign > V Tign during the lamp OFF polling period, causing comparator C ign to periodically provides an ignition-ON signal to the Ignition Delay Circuit. During the Lamp On condition, the Ignition Delay Circuit provides a minimum ignition turn-off delay (t id(off)) such that all currents and regulator voltages remain ON between the Lamp Off polling pulses.BATTERY AND ALTERNATOR OUTPUT VOLTAGE SENSINGThe system battery voltage is directly sensed by theREMOTE input using a remote wire as a Kelvin connection. The Remote input resistance (R rem ) at the REMOTE input is typically 68 k Ω. The voltage at the Remote Sense input (V rs ) is a ratioed value of the Remote voltage (V rem ). The intended ratio of V rem / V rs is about 7.45. The BAT pin voltage (V bat ) is also sensed as an internal Local voltage (V l ). A Local Sense voltage (V ls ) is a ratioed value of voltage V l , where the intended ratio of V l / V ls is also 7.45. The Local internalconnection is provided for fault protection against the remote wire being grounded or exhibiting a high remote wireresistance due to being disconnected or due to a corrosive or loose connection. Thus the Local connection ensures that alternator regulation of the system voltage continues in well-defined states for all possible Remote input fault conditions.LOCAL AND REMOTE VOLTAGE PROCESSING AND SWITCHINGDuring Remote operation both the external Remote input connection and internal Local connection sensesapproximately the same regulated system voltage of V set = 14.8 V. For this case, voltages V rs and V ls are approximately 2.0 V. Because the remote switching comparator C rs isreferenced to 0.6 V, both switches S1 and S2 are OPEN and remain open when voltage V rs > 0.6 V or when voltage V rem is greater than the remote loss threshold voltage (V Trem ). Voltage V rs is coupled to the input of a unity-gain combiner / b uffer CB1. Voltage V ls is buffered and coupled to the output of a unity-gain Local Buffer (LB) and ratioed by the R5 /(R4+R5) resistor divider to provide an input voltage to a unity-gain combiner / b uffer CB2. Thus the voltage at the input of the combiner CB2 is normally 0.8 V ls (or 1.6 V typically), while voltage V rs on the input of CB1 is typically 2.0 V.Because voltage V o reflects the highest voltage at the input of either combiner, voltage V o will be voltage V rs in Remote operation with Remote connected to V bat . For this case, voltage V rs is filtered by a 300 Hz low-pass filter andtranslated to the FB buffer output. Voltage V rs at the FB buffer output is then compared to a digital-to-analog converter output voltage ramp (V dac ) for duty cycle regulation.During a Remote fault condition when the remote sense line is OPEN or grounded, voltage V rs at the Remote Sense input will be zero, causing comparator C rs to activate switches S1 and S2 to a CLOSED position. As a result, voltage V ls is coupled through buffer LB directly to the input of combiner CB2. Because the voltage V ls on the input of combiner CB2 is greater than voltage V rs (= 0 V) on the input of combiner CB1, voltage V ls is coupled to the output of the combiners as voltage V o . Thus in this fault case, voltage V ls is filtered and translated to the FB buffer output for being compared to voltage ramp V dac for regulation.During a remote fault condition in which the resistance of the Remote sense wire increases due to the corrosion or a loose connection, a finite external remote fault resistance occurs causing voltage V rem to decrease, but voltage V rem remains greater than voltage V Trem . As a result, switches S1 and S2 remain in an OPEN condition, while the system voltage will increase due to the effective increase in the Remote resistor divider ratio. As a result, voltage V l increases until the voltage at the input of combiner CB2 isapproximately 2.0 V, or V ls is about 1.2 (2.0 V), or 2.25 V due to the R4 / R 5 divider ratio. Because the local divider ratio translates voltage V ls to V bat by about factor 7.4, the final regulated output voltage for this condition is 7.4 (2.25), or 18.5 V. This is the secondary regulation voltage (V set2). When the system voltage increases to the OvervoltageThreshold (V Tov ), a fault indication occurs by the lamp. Thus this particular Remote fault condition produces a fault indication, but regulates to prevent an extreme system overvoltage condition. When the Remote fault resistance becomes great enough to cause voltage V rem < V Trem , the regulated system voltage returns to the local regulation as described for an OPEN or grounded Remote input.INTERNAL CLOCK OSCILLATOR AND 8-BIT COUNTERAn internal clock oscillator is provided having a typical oscillation frequency (f osc ) of 101 kHz. The output of the oscillator is coupled to an 8-bit counter that provides 8 counting bits to the logic and the four most significant counting bits (MSB) to the LRC circuitry and to a digital-to-analog converter (DAC) waveform generator. The output MSB frequency (f msb ) of the 8-bit divider is about 395 Hz (f msb = f osc / 256), which determines the PWM frequency at the GATE output. An external LRC TEST pin is provided for accelerating internal testing of the LRC function and logic. Under normal operation, the LRC TEST pin is grounded by an internal 10 k Ω resistance to ground. Under accelerated test conditions, the LRC TEST voltage is 5.0 V, and a fourth bit (f osc /16) from the 8-bit divider is used to determine the。

REF3333中文资料

元器件交易网
BurrĆBrown Products from Texas Instruments
REF3312, REF3318 REF3320, REF3325 REF3330, REF3333
SBOS392A – AUGUST 2007 – REVISED SEPTEMBER 2007
NOISE Output Voltage Noise
OUTPUT VOLTAGE Initial Accuracy
NOISE OutputБайду номын сангаасVoltage Noise
OUTPUT VOLTAGE Initial Accuracy
NOISE Output Voltage Noise
OUTPUT VOLTAGE Initial Accuracy
Boldface limits apply over the specified temperature range, –40°C to +125°C. At TA = +25°C and ILOAD = 0mA, unless otherwise noted.
PARAMETER
OUTPUT VOLTAGE Initial Accuracy
MAX +0.15 +0.15 +0.15 +0.15 +0.15 +0.15
UNITS
V % μVPP
V % μVPP
V % μVPP
V % μVPP
V % μVPP
V % μVPP
Copyright © 2007, Texas Instruments Incorporated
f = 0.1Hz to 10Hz REF3330 (3.0V) VIN = 5V

L1119L-33-AA3-O-T中文资料

UNISONIC TECHNOLOGIES CO., LTDL1119 CMOS IC1.5A LOW DROPOUT REGULATORSDESCRIPTIONThe UTC L1119 is a fast ultra low-dropout linear regulator that developed in CMOS process which allows low quiescent current operation independent of output load current. This CMOS process also allows the device to operate under extremely low dropout conditions.The UTC L1119 allows to operate from a 2.5V~7.0V input supply. Wide range of preset output voltage options are available and respond very fast to step changes in load which makes them suitable for low voltage microprocessor applications.FEATURES* Low ground current* Load regulation of 0.04%* Output current of 1.5A DC is guaranteed * Accurate output voltage.(± 1.5%)* Extremely low output capacitor requirements * Over temperature/ Over current protection*Pb-free plating product number: L1119L-xxORDERING INFORMATIONOrder Number Pin AssignmentNormal Lead Free Plating Package 1 2 3PackingL1119-xx-AA3-A-R L1119L-xx-AA3-A-R SOT-223 G O I Tape Reel L1119-xx-AA3-C-R L1119L-xx-AA3-C-R SOT-223 G I O Tape Reel L1119-xx-AB3-A-R L1119L-xx-AB3-A-R SOT-89 G O I Tape Reel L1119-xx-AB3-B-R L1119L-xx-AB3-B-R SOT-89 O G I Tape Reel L1119-xx-AB3-C-R L1119L-xx-AB3-C-R SOT-89 G I O Tape Reel L1119-xx-AB3-D-R L1119L-xx-AB3-D-R SOT-89 I G O Tape Reel L1119-xx-TN3-D-R L1119L-xx-TN3-D-R TO-252 I G O Tape Reel L1119-xx-TN3-D-T L1119L-xx-TN3-D-T TO-252 I G O TubeMARKING INFORMATIONBLOCK DIAGRAMGNDABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL RATINGSUNIT Input Supply Voltage V IN-0.3 ~ +7.5 VOutput Voltage V OUT-0.3 ~ +7.5 VOutput Current I OUT Short Circuit ProtectedPower Dissipation P D InternallyLimitedOperating Junction Temperature T OPR-40 ~ +125Storage Temperature T STG-65 ~ +150Note Absolute maximum ratings are those values beyond which the device could be permanently damaged.Absolute maximum ratings are stress ratings only and functional device operation is not implied.RECOMMENDED OPERATING RATINGSPARAMETER SYMBOL RATINGSUNIT Input Supply Voltage V IN 2.5 ~ 7.0 VMaximum Operating Current (DC) I OPR(MAX) 1.5 A Operating Junction Temperature T J-40 ~ +125Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.Absolute maximum ratings are stress ratings only and functional device operation is not implied.ELECTRICAL CHARACTERISTICS(T J=25°C, V IN =V OUT+1V, I L=10mA, C OUT=33µF,unless otherwise specified.)PARAMETER SYMBOL TESTCONDITIONSMINTYPMAX UNITI L = 150 mA 38 45Dropout Voltage (Note) V DI L = 1.5 A 870mVPeak Output Current I PEAK 2.0 2.5 AI L = 150 mA 4 9Ground Pin Current I GNDI L = 1.5 A 5 14mAOutput Voltage Tolerance V OUT 10 mA ≤ I L≤ 1.5AV OUT +1 ≤ V IN≤ 7.0V-1.5 0 +1.5 %Line Regulation ∆V OUT V OUT+1V<V IN<7.0V 0.1 % Load Regulation ∆V OUT10 mA < I L < 1.5 A 1.5 % SHORT CIRCUIT PROTECTIONShort Circuit Current I SC 4.5 A AC PARAMETERSOutput Noise Density ρN(l/f) f = 120Hz 0.8 µVBW = 10Hz – 100kHz 150Output Noise Voltage eNBW = 300Hz – 300kHz 100µV(rms)V IN = V OUT + 1.5VC OUT =100uF, V OUT = 3.3V 60Ripple Rejection RRV IN = V OUT + 0.3VC OUT =100uF, V OUT = 3.3V 40dBOVER TEMPERATURE PROTECTIONShutdown Threshold T SHDN165 °C Thermal Shutdown Hysteresis T HYS 10 °C Note: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential, since the minimum input voltage is 2.5V.TYPICAL CHARACTERISTICS(V IN =V OUT +1V, V OUT =2.5V, C OUT =33µF, I OUT =10mA, C IN =68µF, Ta =25°C.)-40-200204060801001201400.050.10.150.20.25Temperature (℃)D r o p -O u t (V )Drop-Out Voltage vs Temperature (I L )-40-200204060801001201400.150.1750.20.225Temperature (℃)D r o p -O u t (V )Drop-Out Voltage vs Temperature (V OUT )0.125V OUT vs Temperature0.00D e l t a V O U T (%)-0.10-0.20-0.30-0.40-0.50-0.60-0.70-0.80-0.90-75-50-25255075100125Temperature (℃)100.01010Frequency (Hz)N o i s e ( V / H z )Noise Density1.0000.10010010001000001000003V IN (V)V O U T (V )Input Voltage vs Output Voltage2.50.51.5211234TYPICAL CHARACTERISTICS(Cont.)100Frequency (Hz)Output Noise Density100010000100000100Output Noise Density100010000100000Frequency (Hz)10-1090Frequency (Hz)Ripple Rejection vs Frequency1M100K10K1K1001020304050607080R i p p l e R e j e c t i o n (d B )Load Transient Response20 I O U T (A)VO U T (V )Line Transient Response10 s/DIV V I N (V )V O U T (V )Line Transient Response10 s/DIVV I N (V )V O U T (V )TYPICAL CHARACTERISTICS(Cont.)Line Transient Response10s/DIVV I N (V )V O U T (V )Line Transient Response10 3.253.33.35V I N (V )V O U T (V ) 5.34.33.453.4。

AUO_G173HW01_v0_20110530

() Preliminary Specification(V) Final SpecificationModule 17.3” FHD Color TFT-LCD Model Name G173HW01 V0Customer Date Approved byNote: This Specification is subject to change without notice.Checked &Approved by DateVito Huang2011/5/30 Prepared byVivian Huang2011/5/30Audio Video Business Group /AU Optronics corporationContents1. Handling Precautions (4)2. General Description (5)2.1 Display Characteristics (5)3. Functional Block Diagram (10)4. Absolute Maximum Ratings (11)4.1 Absolute Ratings of TFT LCD Module (11)4.2 Absolute Ratings of Environment (11)5. Electrical characteristics (12)5.1 TFT LCD Module (12)5.2 Backlight Unit (14)6. Signal Characteristic (15)6.1 Pixel Format Image (15)6.2 The Input Data Format (16)6.4 Interface Timing (19)6.5 Power ON/OFF Sequence (20)7. Connector & Pin Assignment (21)7.1 TFT LCD Module (21)7.2 Backlight Unit (22)8. Reliability Test (23)9. Shipping Label (24)10. Packing Form (25)10.1 Packaging material (25)10.2 External packaging material required (25)10.3 Palletizing sequence (26)10.4 Packing instruction (27)11. Outline Drawing (28)Record of RevisionVersion & Date PageOld DescriptionNew Description0.0 2011/1/20 All First Edition for Customer0.1 2011/1/31 12 IDD unit: A IDD unit: mA 14 VCC Max: 12.6V VCC Max: 13.4V14 Operation LifeLED life time1.0 2011/5/30 5 White Luminance(cd/m 2): 500(Typ.) White Luminance(cd/m 2): 400(Typ.) 5 Optical Response Time(ms): 8(Typ.)Optical Response Time(ms): 40(Typ.)5 Power Consumption(Watt): TBD(Typ.) Power Consumption(Watt): 17(Typ.) 5 Weight(g): TBD(Typ.) Weight(g): 1080(Typ.)6 Update Viewing Angle 6 Update Optical Response Time6 Update Color / Chromaticity Coordinates6Update White Luminance 12 IDD (mA): 350(Typ), 600(Max) IDD (mA): 1200(Typ), 1400(Max) 12 PDD (Watt): TBD(Typ), 2(Max) PDD (Watt): 5(Typ), 6(Max)12Update the diagram of Vin rising time 14 P VCC (Watt): 11.88(Typ), 13.39(Max) P VCC (Watt): 12(Typ), 15(Max) 14 Update LED Forward Voltage 14 Update Note6 description 25 Update Shipping Label25 Update Packing Form28Update Outline Drawing1. Handling Precautions1) Since front polarizer is easily damaged, please be cautious and not to scratch it.2) Be sure to turn off power supply when inserting or disconnecting from input connector.3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots.4) When the panel surface is soiled, wipe it with absorbent cotton or soft cloth.5) Since the panel is made of glass, it may be broken or cracked if dropped or bumped on hard surface.6) To avoid ESD (Electro Static Discharde) damage, be sure to ground yourself before handling TFT-LCD Module.7) Do not open nor modify the module assembly.8) Do not press the reflector sheet at the back of the module to any direction.9) In case if a module has to be put back into the packing container slot after it was taken out from the container, do not press the center of the LED light bar edge. Instead, pressat the far ends of the LED light bar edge softly. Otherwise the TFT Module may be damaged.10) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the Interface Connector of the TFT Module.11) TFT-LCD Module is not allowed to be twisted & bent even force is added on module in a very short time. Please design your display product well to avoid external force applying to module by end-user directly.12) Small amount of materials without flammability grade are used in the TFT-LCD module. The TFT-LCD module should be supplied by power complied with requirements of Limited Power Source (IEC60950 or UL1950), or be applied exemption.13) Severe temperature condition may result in different luminance, response time and lamp ignition voltage.14) Continuous operating TFT-LCD display under low temperature environment may accelerate lamp exhaustion and reduce luminance dramatically.15) The data on this specification sheet is applicable when LCD module is placed in landscape position.16) Continuous displaying fixed pattern may induce image sticking. It’s recommended to use screen saver or shuffle content periodically if fixed pattern is displayed on the screen.2. General DescriptionG173HW01 V0 is a Color Active Matrix Liquid Crystal Display composed of a TFT-LCD panel, a LED driver circuit, and a LED backlight system. The screen format is intended to support the FHD (1920(H) x 1080(V)) screen and 16.7M colors (RGB 6-bits + HiFRC data). All input signals are LVDS interface compatible. Inverter card of backlight is not included.2.1 Display CharacteristicsThe following items are characteristics summary on the table under 25 ℃condition:Items Unit Specifications Screen Diagonal [mm] 17.3W (17.25)Active Area [mm] 381.888 (H) x 214.812 (V)Pixels H x V 1920(x3) x 1080Pixel Pitch [mm] 0.1989 (per one triad) x 0.1989Pixel Arrangement R.G.B. Vertical StripeDisplay Mode Normally WhiteWhite Luminance [cd/m2] 400 (Typ.)Contrast Ratio 600 : 1 (Typ)Optical ResponseTime [msec] 40 (Typ, on/off)Nominal Input Voltage VDD [Volt] 3.3 VPower Consumption [Watt] 17 (Typ)Weight [Grams] 1080 (Typ)Physical Size (H x V x D) [mm] 403 (H) x 240 (V) x 12.5 (D) (Typ) Electrical Interface Dual channel LVDSSurface Treatment Hard-coating (3H), Glare treatment Support Color 16.7M colors (RGB 6-bit data + HiFRC data)Temperature Range (Ta) Operating Storage (Non-Operating) [o C][o C]0 to +70-20 to +70RoHS Compliance RoHS Compliance2.2 Optical CharacteristicsThe optical characteristics are measured under stable conditions at 25℃ (Room Temperature):ItemUnit Conditions Min.Typ.Max.NoteHorizontal (Right) CR = 10 (Left) 70 70 80 80 -Viewing Angle [degree]Vertical (Up) CR = 10 (Down) 50 70 60 80 - 1Luminance Uniformity [%] 13 Points 75 80 - 2, 3Rising - 37 50 Falling - 3 10 Optical Response Time[msec] Rising + Falling -4060 4, 5 Red x 0.590 0.640 0.690 Red y 0.296 0.346 0.396 Green x 0.264 0.314 0.364 Green y 0.574 0.624 0.674 Blue x 0.100 0.150 0.200 Blue y 0.004 0.054 0.104 White x 0.255 0.305 0.355 Color / Chromaticity Coordinates (CIE 1931)White y0.268 0.318 0.368 4 White Luminance (At LED=100mA) [cd/m2 ]320 400 - 4 Contrast Ratio 500 600 - 4 NTSC%72Optical Equipment: BM-5A, BM-7, PR880, or equivalentNote 1: Definition of viewing angleViewing angle is the measurement of contrast ratio≧10, or ≧5, at the screen center, over a 180° horizontal and 180° vertical range (off-normal viewing angles). The 180° viewing angle range is broken down as follows; 90° (θ) horizontal left and right and 90° (Φ) vertical, high (up) and low (down). The measurement direction is typically perpendicular to the display surface with the screen rotated about its center to develop the desired measurement viewing angle.Note 2: 13 points positionNote 3:Note 4: Measurement methodThe LCD module should be stabilized at given temperature for 30 minutes to avoid abrupt temperature change during measuring. In order to stabilize the luminance, the measurement should be executed after lighting Backlight for 30 minutes in a stable, windless and dark room.Note 5: Definition of response time:The output signals of photo detector are measured when the input signals are changed from “Full Black” to “Full White” (rising time), and from “Full White” to “Full Black” (falling time), respectively. The response time is interval between the 10% and 90% of amplitudes. Please refer to the figure as below.3. Functional Block DiagramThe following diagram shows the functional block of the 17.3 inches Color TFT-LCD Module:4. Absolute Maximum RatingsAbsolute maximum ratings of the module are as following:4.1 Absolute Ratings of TFT LCD ModuleItem Symbol Min Max Unit Logic/LCD Drive Voltage Vin -0.3 +3.6 [Volt]4.2 Absolute Ratings of EnvironmentItem Symbol Min Max Unit Operating Temperature TOP 0 +70 [o C] Operation Humidity HOP 5 95 [%RH] Storage Temperature TST -20 +70 [o C] Storage Humidity HST 5 95 [%RH] Note: Maximum Wet- and no condensation.5. Electrical characteristics 5.1 TFT LCD Module5.1.1 Power Specification Input power specifications are as follows:SymbleParameter Min.Typ.Max.UnitConditionVDD Logic/LCD DriveVoltage 3.0 3.3 3.6 [Volt] ±10%IDD Input Current - 1200 1400 [mA] VDD= 5.0V, All Black Pattern At 75Hz, +30%PDD VDD Power - 5 6 [Watt] VDD= 5.0V, All Black Pattern At 75Hz , Note 1IRush Inrush Current- - 2000 [A] Note 2VDDrpAllowable Logic/LCD Drive Ripple Voltage --100[mV] p-pVDD= 3.3V, All Black Pattern At 75HzNote 1: The variance of VDD power consumption is ±30%. Note 2: Measurement conditions:Vin rising time0V5.1.2 Signal Electrical Characteristics Input signals shall be low or Hi-Z state when VDD is off. Note: LVDS Signal Waveform.5.2 Backlight UnitFollowing characteristics are measured under a stable condition using a inverter at 25℃. (Room Temperature): Symbol Parameter Min.Typ.Max.Unit RemarkVCC Input Voltage 10.8 12 13.4 [Volt]I VCC Input Current - 0.99 - [A] 100% PWM DutyP VCC Power Consumption - 12 15 [Watt]100% PWM DutyF PWM Dimming Frequency 200 - 20K [Hz]Swing Voltage 3 3.3 5.5 [Volt]Dimming duty cycle 5 - 100 %I F LED Forward Current-100 -[mA] Ta = 25o C- (3.3) (3.7) [Volt]I F = 100mA, Ta = 0o C- 3.2 3.6 [Volt]I F = 100mA, Ta = 25o C V F LED Forward Voltage- (3.1) (3.5) [Volt]I F = 100mA, Ta = 70o C P LED LED Power Consumption- (10.24)11.52 [Watt]LED Life Time50,000 - - Hrs I F=100mA, Ta= 25o CNote 1: Ta means ambient temperature of TFT-LCD module.Note 2: VCC, I VCC, P VCC are defined for LED backlight.(100% duty of PWM dimming)Note 3: I F, V F are defined for one channel LED. There are four LED channel in back light unit.Note 4: If G173HW01 V0 module is driven by high current or at high ambient temperature & humidity condition. The operating life will be reduced.Note 5: Operating life means brightness goes down to 50% initial brightness. Minimum operating life time is estimated data.Note 6: LED lifetime is definition: brightness is decreased to 50% of the initial value. LED lifetime is restricted under6. Signal Characteristic6.1 Pixel Format ImageFollowing figure shows the relationship of the input signals and LCD pixel format.1st2nd1919th1920th1stLine1080thLin6.2 The Input Data FormatNote1: Normally, DE, VS, HS on EVEN channel are not used. Note2: 8-bit in6.3 Signal DescriptionThe module using a pair of LVDS receiver SN75LVDS82(Texas Instruments) or compatible. LVDS is a differential signal technology for LCD interface and high speed data transfer device. Transmitter shall be SN75LVDS83(negative edge sampling) or compatible. The first LVDS port(RxOxxx) transmits odd pixels while the second LVDS port(RxExxx) transmits even pixels.PIN #SIGNAL NAME DESCRIPTION1 RxOIN0- Negative LVDS differential data input (Odd data)2 RxOIN0+ Positive LVDS differential data input (Odd data)3 RxOIN1- Negative LVDS differential data input (Odd data)4 RxOIN1+ Positive LVDS differential data input (Odd data)5 RxOIN2- Negative LVDS differential data input (Odd data, H-Sync,V-Sync,DSPTMG)6 RxOIN2+ Positive LVDS differential data input (Odd data, H-Sync,V-Sync,DSPTMG)7 VSS Power Ground8 RxOCLKIN- Negative LVDS differential clock input (Odd clock)9 RxOCLKIN+Positive LVDS differential clock input (Odd clock)10 RxOIN3- Negative LVDS differential data input (Odd data)11 RxOIN3+ Positive LVDS differential data input (Odd data)12 RxEIN0- Negative LVDS differential data input (Even data)13 RxEIN0+ Positive LVDS differential data input (Even data)14 VSS Power Ground15 RxEIN1- Negative LVDS differential data input (Even data)16 RxEIN1+ Positive LVDS differential data input (Even data)17 VSS Power Ground18 RxEIN2- Negative LVDS differential data input (Even data)19 RxEIN2+ Positive LVDS differential data input (Even data)20 RxECLKIN- Negative LVDS differential clock input (Even clock)21 RxECLKIN+ Positive LVDS differential clock input (Even clock)22 RxEIN3- Negative LVDS differential data input (Even data)23 RxEIN3+ Positive LVDS differential data input (Even data)24 VSS Power Ground25 VSS Power Ground26 VSS Power Ground27 VSS Power Ground28 VDD +3.3V Power Supply29 VDD +3.3V Power Supply30 VDD +3.3V Power SupplyNote1: Start from left sideRxOIN0-VDDNote2: Input signals of odd and even clock shall be the same timing. Note3: Please follow PSWG.6.4 Interface Timing6.4.1 Timing CharacteristicsBasically, interface timings should match the 1920X1080 / 60Hz manufacturing guide line timing.Note : DE mode only6.4.2 Timing Diagram6.5 Power ON/OFF SequenceVDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from any system shall be Hi-Z state or low level when VDD is off.Power Sequence TimingPower Sequence TimingValueUnitsParameterMin. Typ. Max.T1 0.5 - 10T2 0 - 50T3 200 - --T4 0.5 - 10T5 10 - -T6 10 - -msT7 0 - -T8 10 - -T9 - - 10T10 110 - -T11 0 50T12 0 10T13 500 - -7. Connector & Pin AssignmentPhysical interface is described as for the connector on module.These connectors are capable of accommodating the following signals and will be following components.7.1 TFT LCD Module7.1.1 ConnectorConnector Name / Designation Interface Connector / Interface card Manufacturer HRSType Part Number MDF76TW-30S-1HMating Type Part Number MDF76-30P-1C7.1.2 Pin AssignmentPin#Signal Name Pin#Signal Name1 RxOIN0-2 RxOIN0+3 RxOIN1-4 RxOIN1+5 RxOIN2-6 RxOIN2+7 VSS 8 RxOCLKIN-9 RxOCLKIN+ 10 RxOIN3-11 RxOIN3+ 12 RxEIN0-13 RxEIN0+ 14 VSS15 RxEIN1- 16 RxEIN1+17 VSS 18 RxEIN2-19 RxEIN2+ 20 RxECLKIN-21 RxECLKIN+ 22 RxEIN3-23 RxEIN3+ 24 VSS25 VSS 26 VSS27 VSS 28 VDD29 VDD 30 VDD7.2 Backlight UnitPhysical interface is described as for the connector on module. These connectors are capable of accommodating the following signals and will be following components.7.2.1 ConnectorConnector Name / Designation Lamp Connector / Backlight lamp Manufacturer HRSType Part Number DF14A-6P-1.25HMating Type Part Number DF14-6S-1.25C7.2.2 Pin AssignmentPin No. Symbol DescriptionPin1 VLED 12V inputPin2 VLED 12V inputPin3 GND GNDPin4 GND GNDPin5 On/OFF 3.3-5V:ON, 0V:OFFPin6 Dimming PWM8. Reliability TestEnvironment test conditions are listed as following table.Items Required Condition Note Temperature Humidity Bias (THB) Ta= 50℃, 80%RH, 240hoursHigh Temperature Operation (HTO)Ta= 70℃, 240hoursLow Temperature Operation (LTO) Ta= 0℃, 240hoursHigh Temperature Storage (HTS) Ta= 70℃, 240hoursLow Temperature Storage (LTS) Ta= -20℃, 240hoursVibration Test (Non-operation) Acceleration: 1.5 GWave: Random Frequency: 10 - 200 - 10 Hz Sweep: 30 Minutes each Axis (X, Y, Z)Shock Test (Non-operation) Acceleration: 50 GWave: Half-sineActive Time: 20 msDirection: ±X,±Y,±Z (one time for each Axis)Drop Test Height: 60 cm, package testThermal Shock Test (TST) -20℃/30min, 60℃/30min, 50 cycles 1Contact Discharge: ± 8KV, 150pF(330Ω ) 1sec,8 points, 25 times/ point.ESD (Electro-Static Discharge)Air Discharge: ± 15KV, 150pF(330Ω ) 1sec8 points, 25 times/ point.2Note 1: The TFT-LCD module will not sustain damage after being subjected to 100 cycles of rapid temperature change. A cycle of rapid temperature change consists of varying the temperature from -20℃to 60℃, and back again. Power is not applied during the test. After temperature cycling, the unit is placed in normal room ambient for at least 4 hours before power on.Note 2: According to EN61000-4-2, ESD class B: Some performance degradation allowed. No data lost.Self-recoverable. No hardware failures.9. Shipping LabelUnit: mm10. Packing Form10.1 Packaging materialFILM PROTECTBAG ANTI-STATICTAPETAPE CREPED PAPERPACKING CARTONLABEL SPECLABEL CARTON.CUSHION PACKING10.2 External packaging material required‧Carton : 524mm*321mm*360mm, weight (carton + cushion): 1250g‧Pallet : 1140mm*980mm*140mm‧Stretch film : 500mm (W)*300M (L)‧Corner angle : L type fiber board‧PET band : 19mm (W)‧ Label : 220mm*200mm10.3 Palletizing sequencepcs / box box / layer layer / pallet pcs / pallet Shipping by air 10 2*3 3 180 Shipping by sea 10 2*3 3 180A U O P T R O N I C S C O R P O R A T I O NP r o d u c t S p e c i f i c a t i o nm e n t v e r s i o n 1.0 27/29G 173H W 01 V 0P a c k i n g i n s t r u c t i o nA U O P T R O N I C S C O R P O R A T I O NP r o d u c t S p e c i f i c a t i o nm e n t v e r s i o n 1.0 28/29G 173H W 01 V 0A U O P T R O N I C S C O R P O R A T I O NP r o d u c t S p e c i f i c a t i o nm e n t v e r s i o n 1.0 29/29G 173H W 01 V 0。

1103a-33tg1技术参数

主题：1103a-33tg1技术参数1. 产品概述1103a-33tg1是一款高性能的柴油发动机，适用于各类商用车辆、工程机械以及动力设备。

该发动机采用先进的柴油喷射技术，具有高效、节能、环保的特点。

下面将详细介绍1103a-33tg1的技术参数。

2. 发动机类型1103a-33tg1属于柴油发动机，采用直列四缸、涡轮增压、中冷技术。

该设计使得发动机在动力输出和燃油经济性方面表现出色。

3. 排量和缸径1103a-33tg1的排量为3.3升，缸径为106毫米。

这样的排量和缸径设计，使得发动机在不同负载下都能够提供充足的动力输出。

4. 最大功率1103a-33tg1的最大净功率为75kW，最大毛功率为87kW。

这一参数表明该发动机可在各种工况下提供稳定、高效的动力输出。

5. 最大扭矩1103a-33tg1的最大扭矩为320N.m，在低速工况下提供充足的动力输出，保证了车辆和设备的良好启动和加速性能。

1103a-33tg1采用了先进的共轨柴油喷射系统，能够精确控制燃油喷射的压力和时间，从而实现更加高效的燃烧，降低燃油消耗和排放。

7. 排放标准1103a-33tg1符合国家V阶段排放标准，通过优化燃烧控制和废气处理系统，将废气排放降至最低，保护环境、符合绿色环保的发展理念。

8. 应用领域1103a-33tg1适用于各种商用车辆、工程机械和动力设备，广泛应用于公交车、货车、挖掘机、装载机、发电机组等领域。

9. 总结1103a-33tg1发动机具有较高的性能、可靠的质量和先进的技术，适用于各种商用车辆和动力设备。

其符合国家V阶段排放标准，环保节能。

1103a-33tg1发动机的推出，将为各行各业的用户提供更加安全、可靠和环保的动力选择。

1103a-33tg1技术参数：10. 散热系统1103a-33tg1配备了高效的散热系统，确保发动机长时间运行时的稳定性和安全性。

通过优化的散热器设计和风道结构，有效地降低了发动机的工作温度，保证了发动机在高负荷工况下的可靠性。

Silicon Digital Attenuator HMC1119数据手册说明书

0.25 dB LSB, 7-Bit, Silicon DigitalAttenuator, 0.1 GHz to 6.0 GHz Data Sheet HMC1119Rev. C Document FeedbackInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2018 Analog Devices, Inc. All rights reserved. Technical Support FEATURESAttenuation range: 0.25 dB LSB steps to 31.75 dBLow insertion loss:1.1 dB at 1.0 GHz1.3 dB at2.0 GHzTypical step error: less than ±0.1 dBExcellent attenuation accuracy: less than ±0.2 dBLow phase shift error: 6° phase shift at 1.0 GHzSafe state transitionsHigh linearity1 dB compression (P1dB): 31 dBm typicalInput third-order intercept (IP3): 54 dBm typicalRF settling time (0.05 dB final RF output): 250 nsSingle supply operation: 3.3 V to 5.0 VESD rating: Class 2 (2 kV human body model (HBM))24-lead, 4 mm × 4 mm LFCSP package: 16 mm2 APPLICATIONSCellular infrastructureMicrowave radios and very small aperture terminals (VSATs) Test equipment and sensorsIF and RF designsFUNCTIONAL BLOCK DIAGRAMVGND65432112962-1Figure 1.GENERAL DESCRIPTIONThe HMC1119 is a broadband, highly accurate, 7-bit digital attenuator, operating from 0.1 GHz to 6.0 GHz with 31.5 dB attenuation control range in 0.25 dB steps.The HMC1119 is implemented in a silicon process, offering very fast settling time, low power consumption, and high ESD robustness. The device features safe state transitions and is optimized for excellent step accuracy and high linearity over frequency and temperature range. The RF input and output are internally matched to 50 Ω and do not require any external matching components. The design is bidirectional; therefore, the RF input and output are interchangeable. The HMC1119 has an on-chip regulator that can support a wide supply operating range from 3.3 V to 5.0 V with no performance change in electrical characteristics. The HMC1119 incorporates a driver that supports serial (3-wire) and parallel controls of the attenuator.The HMC1119 comes in a RoHS-compliant, compact, 4 mm ×4 mm LFCSP package.A fully populated evaluation board is available.HMC1119Data SheetRev. C | Page 2 of 15TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Specifications ............................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings ....................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Interface Schematics..................................................................... 7 Typical Performance Characteristics ............................................. 8 Insertion Loss, Return Loss, State Error, Step Error, andRelative Phase ................................................................................8 Input Power Compression and Third-Order Intercept ......... 10 Theory of Operation ...................................................................... 11 Serial Control Interface ............................................................. 11 RF Input Output ......................................................................... 11 Parallel Control Interface .......................................................... 12 Power-Up Sequence ................................................................... 12 Applications Information .............................................................. 13 Evaluation Printed Circuit Board ............................................ 13 Packaging and Ordering Information ......................................... 15 Outline Dimensions ................................................................... 15 Ordering Guide .. (15)REVISION HISTORY4/2018—Rev. B to Rev CChanges to Figure 23 ...................................................................... 12 Change to PCB Description, Table 7 ............................................ 13 Updated Outline Dimensions . (15)9/2017—Rev. A to Rev. BChanged CP-24-16 to HCP-24-3 ................................. Throughout Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 8/2017—Rev. 0 to Rev. AAdded Timing Specifications Section ............................................. 4 Moved Table 2 .................................................................................... 4 Changes to Figure 5 and Figure 6 .................................................... 7 Changes to Serial Control Interface Section ............................... 11 Moved Figure 22 and Table 6 ........................................................ 11 Changes to Figure 23 ...................................................................... 12 Moved Parallel Control Interface Section, Direct Parallel Mode Section, Latched Parallel Mode Section, Power-Up Sequence Section, and Power-Up States Section ......................................... 12 Updated Outline Dimensions . (15)9/2016—Revision 0: Initial VersionData SheetHMC1119Rev. C | Page 3 of 15SPECIFICATIONSELECTRICAL SPECIFICATIONSV DD = 3.3 V to 5.0 V , T A = 25°C, 50 Ω system, unless otherwise noted. Table 1.ParameterTest Conditions/Comments Min Typ Max Unit FREQUENCY RANGE0.1 6.0 GHz INSERTION LOSS 0.1 GHz to 1.0 GHz 1.1 1.8 dB 0.1 GHz to 2.0 GHz 1.3 2.0 dB 0.1 GHz to 4.0 GHz 1.6 2.3 dB0.1 GHz to 6.0 GHz 2.0 2.8 dB ATTENUATION 0.2 GHz to 6.0 GHzRange Delta between minimum and maximum attenuation states31.75dB AccuracyReferenced to insertion loss; all attenuation states−(0.05 + 4% of attenuation setting) +(0.05 + 4% of attenuation setting) dB Step Error All attenuation states±0.1 dB Overshoot Between all attenuation states ≤0.1 dB RETURN LOSSAll attenuation states ATTNIN, ATTNOUT 1.0 GHz 23 dBm 2.0 GHz 22 dBm 4.0 GHz 19 dBm6.0 GHz 17 dBm RELATIVE PHASE 1.0 GHz 6 Degrees 2.0 GHz 18 Degrees 4.0 GHz 38 Degrees6.0 GHz 58 Degrees SWITCHING CHARACTERISTICSt RISE , t FALL 10%/90% RF output60 ns t ON , t OFF50% CTL to 10%/90% RF output 150 ns Settling Time 50% CTL to 0.05 dB final RF output 250 ns50% CTL to 0.10 dB final RF output 200 ns INPUT LINEARITYAll attenuation states, 0.2 GHz to 6 GHz 0.1 dB Compression (P0.1dB) 30 dBm 1 dB Compression (P1dB)31 dBm Input Third-Order Intercept (IP3) Two-tone input power = 16 dBm/tone, ∆f = 1 MHz 54 dBm SUPPLY CURRENT (I DD ) V DD = 3.3 V 0.3 mAV DD = 5.0 V 0.6 mA CONTROL VOLTAGE THRESHOLD <1 µA typical Low V DD = 3.3 V 0 0.5 VV DD = 5.0 V 0 0.8 V High V DD = 3.3 V 2.0 3.3 VV DD = 5.0 V 3.5 5.0 V RECOMMENDED OPERATING CONDITIONS Supply Voltage Range (V DD )3.0 5.4 V Digital Control Voltage Range For P/S, CLK, SERNIN, LE, D0 to D6 pins 0 V DD V RF Input PowerAll attenuation states, T CASE = 85°C 24 dBm Case Temperature (T CASE )−40+85°CHMC1119 Data SheetTIMING SPECIFICATIONSSee Figure 23 and Figure 24 for the timing diagrams.Table 2.Parameter Description Min Typ Max Unitt SCK Minimum serial period, see Figure 23 70 nst CS Control setup time, see Figure 23 15 nst CH Control hold time, see Figure 23 20 nst LN LE setup time, see Figure 23 15 nst LEW Minimum LE pulse width, see Figure 24 10 nst LES Minimum LE pulse spacing, see Figure 23 630 nst CKN Serial clock hold time from LE, see Figure 23 0 nst PH Hold time, see Figure 24 10 nst PS Setup time, see Figure 24 2 nsRev. C | Page 4 of 15Data SheetHMC1119Rev. C | Page 5 of 15ABSOLUTE MAXIMUM RATINGSTable 3.ParameterRating RF Input Power (T CASE = 85°C) 25 dBmDigital Control Inputs (P/S, CLK, SERNIN, LE, D0 to D6) −0.3 V to V DD + 0.5 V Supply Voltage (V DD )−0.3 V to +5.5 V Continuous Power Dissipation (P DISS ) 0.31 W Thermal Resistance (at Maximum Power Dissipation) 156°C/WTemperatureChannel Temperature 135°CStorage−65°C to +150°C Maximum Reflow Temperature 260°C (MSL3 Rating) ESD Sensitivity (HBM)2 kV (Class 2)Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.ESD CAUTIONHMC1119Data SheetRev. C | Page 6 of 15PIN CONFIGURATION AND FUNCTION DESCRIPTIONSV SERNIN NOTES1. THE EXPOSED PAD AND GND PINS MUST BE CONNECTED TO RF DC GROUND.CLK LE GND ATTNOUT GNDG N G N G N G N G N G N D 6D 5D 4D 3D 2D 112962-002Figure 2. Pin ConfigurationTable 4. Pin Function DescriptionsPin No. Mnemonic Description1, 19 to 24 D0, D6 to D1 Parallel Control Voltage Inputs. These pins attain the required attenuation (see Table 6). There is no internal pull-up or pull-down on these pins; therefore, these pins must always be kept at a valid logic level (V IH or V IL ) and must not be left floating. 2 V DD Supply Voltage Pin.3P/S Parallel/Serial Control Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (V IH or V IL ) and must not be left floating. For parallel mode, set Pin 3 to low; for serial mode, set Pin 3 to high.4, 6 to 13, 15 GND Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB) RF/dc ground. See Figure 4 for the GND interface schematic.5 ATTNIN Attenuator Input. This pin is dc-coupled and matched to 50 Ω. A blocking capacitor is required. Select the value of the capacitor based on the lowest frequency of operation. See Figure 5.14 ATTNOUT Attenuator Output. This pin is dc-coupled and matched to 50 Ω.A blocking capacitor is required. Select the value of the capacitor based on the lowest frequency of operation. See Figure 5.16 LE Serial/Parallel Interface Latch Enable Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (V IH or V IL ) and must not be left floating. See the Theory of Operation section for more information.17 CLK Serial Interface Clock Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (V IH or V IL ) and must not be left floating. See the Theory of Operation section for more information.18 SERNIN Serial interface Data Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (V IH or V IL ) and must not be left floating. See the Theory of Operation section for more information.EPADExposed Pad. The exposed pad must be connected to RF/dc ground.Data SheetHMC1119Rev. C | Page 7 of 15INTERFACE SCHEMATICSD0TO D512962-021Figure 3. D0 to D6 Interface12962-022Figure 4. GND Interface12962-023Figure 5. ATTIN and ATTOUT InterfaceV 12962-024Figure 6. P/S, LE, CLK, and SERNIN InterfaceHMC1119Data SheetRev. C | Page 8 of 15TYPICAL PERFORMANCE CHARACTERISTICSINSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE–4–3–2–1I N S E R T I O N L O S S (d B )FREQUENCY (GHz)12962-003Figure 7. Insertion Loss vs. Frequency at Various TemperaturesFREQUENCY (GHz)–50–40–30–20–100I N P U T R E T U R N L O S S (d B)12962-004Figure 8. Input Return Loss (Major States Only)–2.0–1.6–1.2–0.8–0.400.40.81.21.62.0043281216202428S T A T E E R R O R (d B )ATTENUATION STATE (dB)12962-007Figure 9. State Error vs. Attentuation State, 0.1 GHz to 0.5 GHzFREQUENCY (GHz)–35–30–25–20–15–10–50N O R M A L I Z E D A T T E N U A T I O N (d B )12962-005Figure 10. Normalized Attenuation (Major States Only)FREQUENCY (GHz)–60–50–40–30–20–10O U T P U T R E T U R N L O S S (d B )12962-006Figure 11. Output Return Loss (Major States Only)–1–0.8–0.6–0.4–0.200.20.40.60.81S T A T E E R R O R (d B )043281216202428ATTENUATION STATE (dB)12962-009Figure 12. State Error vs. Attentuation State, 1 GHz to 6 GHzData SheetHMC1119Rev. C | Page 9 of 15–2.0–1.5–1.0–0.500.51.01.52.0S T A T E E R R O R (d B )FREQUENCY (GHz)12962-008Figure 13. State Error vs. Frequency, Major States Only–60–40–20020406080R E L A T I V E P H A S E (d e g )FREQUENCY (GHz)12962-011Figure 14. Relative Phase vs. Frequency, Major States Only–1.0–0.8–0.6–0.4–0.200.20.40.60.81.0S T E P E R R O R (d B )FREQUENCY (GHz)12962-010Figure 15. Step Error vs. Frequency, Major States OnlyHMC1119Data SheetRev. C | Page 10 of 15INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT152025303540P 1d B(d B m )FREQUENCY (GHz)12962-012Figure 16. P1dB vs. Frequency at Various Temperatures, MinimumAttentuation State, 0.05 GHz to 1 GHz152025303540P 0.1d B(d B m )FREQUENCY (GHz)12962-013Figure 17. P0.1dB vs. Frequency at Various Temperatures, MinimumAttentuation State, 0.05 GHz to 1 GHzFREQUENCY (GHz)3040506070I P 3(d B m )0.200.40.60.8 1.012962-014Figure 18. IP3 vs. Frequency at Various Temperatures, MinimumAttentuation State, 0.1 GHz to 1 GHz 152025303540P 1d B (dB m )FREQUENCY (GHz)12962-015Figure 19. P1dB vs. Frequency at Various Temperatures, MinimumAttentuation State, 0.05 GHz to 6 GHz152025303540P 0.1d B (dB m )FREQUENCY (GHz)12962-016Figure 20. P0.1dB vs. Frequency at Various Temperatures, MinimumAttentuation State, 0.05 GHz to 6 GHzFREQUENCY (GHz)3040506070I P 3(d B m )12962-017Figure 21. IP3 vs. Frequency at Various Temperatures, MinimumAttentuation State, 0.1 GHz to 6 GHzTHEORY OF OPERATIONThe HMC1119 incorporates a 7-bit fixed attenuator array that offers an attenuation range of 0.25 dB to 31.75 dB, with 0.25 dB steps. An integrated driver provides both serial and parallel mode control of the attenuator array (see Figure 22).The HMC1119 can be in either serial or parallel mode control by setting the P/S pin to high or low, respectively (see Table 5). The 7-bit data, loaded in either serial or parallel mode, then latches with the control signal, LE, to determine the attenuator value. Table 5. Mode Selection Table 1P/S Pin State Control Mode Low Parallel HighSerial1The P/S pin must always be kept at a valid logic level (V IH or V IL ) and must not be left floating.SERIAL CONTROL INTERFACEThe HMC1119 utilizes a 3-wire serial to parallel (SPI)configuration, as shown in the serial mode timing diagram (see Figure 23): serial data input (SERNIN), clock (CLK), and latch enable (LE). The serial control interface activates when the P/S pin is set to high.In serial mode, the 7-bit SERNIN data is clocked MSB first on rising CLK edges into the shift register; then, LE must betoggled high to latch the new attenuation state into the device. The LE must be set low to clock a set of 7-bit data into the shift register because CLK is masked to prevent the attenuator value from changing if LE is kept high.In serial mode operation, both the serial control inputs (LE, CLK, SERNIN) and the parallel control inputs (D0 to D6) must always be kept at a valid logic level (V IH or V IL ) and must not be left floating. It is recommended to connect the parallel control inputs to ground and to use pull-down resistors on all serial control input lines if the device driving these input lines goes high impedance during hibernation.RF INPUT OUTPUTThe attenuator in the HMC1119 is bidirectional; the ATTNIN and ATTNOUT pins are interchangeable as the RF input and output ports. The attenuator is internally matched to 50 Ω at both input and output; therefore, no external matching components are required. The RF pins are dc-coupled; therefore, dc blocking capacitors are required on RF lines.SERNIND0D1D2D3D4D5D6CLK P/S LERFOUTPUT12962-018Figure 22. Attenuator Array Functional Block DiagramTable 6. Truth TableDigital Control Input 1Attenuation State (dB) D6 D5 D4 D3 D2 D1D0 Low Low Low Low Low Low Low 0 (reference) Low Low Low Low Low Low High 0.25 Low Low Low Low Low High Low 0.5 Low Low Low Low High Low Low 1.0 Low Low Low High Low Low Low 2.0 Low Low High Low Low Low Low 4.0 Low High Low Low Low Low Low 8.0 High Low Low Low Low Low Low 16.0 HighHighHigh High HighHigh High 31.751Any combination of the control voltage input states shown in Table 6 provides an attenuation equal to the sum of the bits selected.12962-19 P/SSERNINCLKLEFigure 23. Serial Control Timing DiagramPARALLEL CONTROL INTERFACEThe parallel control interface has seven digital control input lines(D6 to D0) to set the attenuation value. D6 is the most significantbit (MSB) that selects the 16 dB attenuator stage, and D0 is theleast significant bit (LSB) that selects the 0.25 dB attenuator stage(see Figure 22).In parallel mode operation, both the serial control inputs (LE, CLK,SERNIN) and the parallel control inputs (D0 to D6) must always bekept at a valid logic level (V IH or V IL) and must not be left floating. Itis recommended to connect the serial control inputs to ground andto use pull-down resistors on all parallel control input lines ifthe device driving these input lines goes high impedance duringhibernation.Setting P/S to low enables parallel mode. There are two modes ofparallel operation: direct parallel mode and latched parallel mode.Direct Parallel ModeFor direct parallel mode, the latch enable (LE) pin must be kepthigh. Change the attenuation state using the control voltage inputs(D0 to D6) directly. This mode is ideal for manual control of theattenuator and using hardware, switches, or a jumper.Latched Parallel ModeThe latch enable (LE) pin must be low when changing thecontrol voltage inputs (D0 to D6) to set the attenuation state.When the desired state is set, LE must be toggled high to transferthe 7-bit data to the bypass switches of the attenuator array, thentoggled low to latch the change into the device (see Figure 24).LED6TO D0P/S12962-2Figure 24. Latched Parallel Mode Timing DiagramPOWER-UP SEQUENCEThe ideal power-up sequence is as follows:1.Power up GND.2.Power up V DD.3.Power up the digital control inputs (the relative order ofthe digital control inputs is not important).4.Power up the RF input.For latched parallel mode operation, LE must be toggled. Therelative order of the digital inputs is not important as long as theinputs are powered up after GND and V DD.Power-Up StatesThe logic state of the device is at maximum attenuation when, atpower up, LE is set to low. The attenuator latches in the desiredpower-up state approximately 200 ms after power up.APPLICATIONS INFORMATIONEVALUATION PRINTED CIRCUIT BOARDThe schematic of the evaluation board, EV2HMC1119LP4M , is shown in Figure 25. The PCB is four-layer material with a copper thickness of 0.7 mils on each layer. Each copper layer is separated with a dielectric material. The top dielectric material is 10-mil RO4350 with a typical dielectric constant of 3.48. The middle and bottom dielectric materials are FR-4 material, used for mechanical strength and to meet the overall board thickness of approximately 62 mils, which allows SMA connectors to beAll RF and dc traces are routed on the top copper layer. The RF transmission lines are designed using coplanar waveguide model (CPWG) with a width of 18 mils, spacing of 17 mils, and dielectric thickness of 10 mils to maintain 50 Ω characteristic impedance. The inner and bottom layers are solid ground planes. For optimal electrical and thermal performance, an ample number of vias are populated around the transmission lines and under the package exposed pad. The evaluation board layout serves as a recommenda-tion for the optimal performance on both electrical and thermal aspects.12962-026Figure 25. EV2HMC1119LP4M Evaluation PCBTable 7. Bill of MaterialsItem Value 1 DescriptionManufacturer 2 J1, J2 PCB mount SMA connector J318-pin dc connectorTP1, TP2Through hole mount test point C1, C3 100 pF Capacitor, 0402 package C6 10 μF Capacitor, 0603 package C71000 pF Capacitor, 0402 package R1 to R11 0 Ω Resistor, 0402 package R12 to R25 100 kΩ Resistor, 0402 packageSW1, SW2 SPDT four-position DIP switchU1 HMC1119 digital attenuator Analog Devices, Inc.PCB 3600-01280-00-1 evaluation PCB EV2HMC1119LP4M 4 from Analog Devices1 Blank cells in the Value column indicate that there is no specific value recommendation for the listed component.2Blank cells in the Manufacturer column indicate that there is no specific manufacturer recommendation for the listed component. 3Circuit board material is Arlon 25FR. 4Reference this number when ordering the full evaluation PCB. See the Ordering Guide section.12962-027Figure 26. Applications CircuitPACKAGING AND ORDERING INFORMATIONOUTLINE DIMENSIONS0.50BSC0.500.400.30BOTTOM VIEWTOP VIEWSIDE VIEW4.104.00 SQ 3.900.950.850.750.05 MAX 0.02 NOM0.20 REFCOPLANARITY0.08PIN 1INDICATORFOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.12-08-2017-C0.300.250.180.20 MIN2.852.70 SQ 2.55EXPOSED PAD00SEATING PLANEDETAIL A (JEDEC 95)Figure 27. 24-Lead Lead Frame Chip Scale Package [LFCSP]4 mm × 4 mm Body and 0.85 mm Package Height(HCP-24-3)Dimensions shown in millimetersORDERING GUIDEModel 1Temperature Range MSL Rating 2 Package DescriptionPackage Option HMC1119LP4ME −40°C to +85°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] HCP-24-3 HMC1119LP4METR −40°C to +85°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] HCP-24-3 EV2HMC1119LP4MEvaluation Board1 All models are RoHS compliant.2See the Absolute Maximum Ratings section.©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12962-0-4/18(C)。

NUW3390系列超级白色预催化漆 Zenith透明防水剂说明书

The data on this sheet represent typical values. Since application variables are a major factor in product performance, this information should serve only as a general guide. Axalta assumes no obligation or liability for use of this information . UNLESS AXALTA AGREES OTHERWISE IN WRITING, AXALTA MAKES NO WARRANTIES, EXPRESS ORIMPLIED, AND DISCLAIMS ALL IMPLIED WARRANTIES INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR USE OR FREEDOM FROM PATENT INFRINGEMENT. AXALTA WILL NOT BE LIABLE FOR ANY SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES. Your only remedy for any defect in thisproduct is the replacement of the defective product, or a refund of its purchase price, at our option. The information in this sheet, as well as the products referenced herein, shall beGENERAL INFORMATIONAxalta ’s SUPERLAC PLUS™ Pre -catalyzed White Lacquers are a line of highly durable pre-catalyzed lacquers that offer excellent build and durability approaching that of two-component acid cured coatings in a HAPs Free formulation. The high build, UV protection, chemical and mar resistance that this product provides makes in an excellent choice for cabinet and furniture applications. This product can be tinted to achieve unlimited colour options.1. PRODUCTS• NUW3390-90C NUW3390-35C• NUW3390-25C NUW3390-10C2. MIXING RATIO• All products should be stirred well before use and, forbest results, continuously agitated while in use.3. SHELF LIFE @ 77°F (25°C)• 6 months from manufacture date4. CLEAN UP• All products should be stirred well before use and, for bestresults, continuously agitated while in use.5. ADDITIVES• In the event of blushing or blistering, add Axalta 390-9303-00 Lacquer Retarder to extend dry time. See Additional Notes portion of this document for details.6. SURFACE PREPARATION• Surface must be clean and dust free with a moisturecontent of 6-8% prior to finishing. Remove all dust, dirt, wax and wood marks. Proper sanding and preparation of the wood is critical to achieving consistent results.• On new wood, finish sand surface with 150-180 grit sandpaper• On previously finished wood, remove all old paint or varnish and follow new wood procedure.7. COMPANION PRODUCTS• 383-1902-00 & 383-9905-00 SUPERLAC ™ Basecoats8. TECH NOTES• If reduction is necessary, use Axalta 390-7001-00 LacquerThinner. See Additional Notes portion of this document for details.9. SUBSTRATES• Commonly used furniture and cabinetry woods • MDF/HDFNOTE: Not to be used on exterior applications10. APPLICATION• See application notes for additional details.11. FLASH / DRY TIMESAIR DRY @ 77°F (25°C)12. FORCE DRYFlash 10 Minutes Bake 5 Minutes @ 125°F Cool Down 10 Minutes ambient StackAfter cool down13. GUN SET UPGravity Feed 1.6 mm - 1.8 mm Siphon Feed 1.8 mm – 2.0 mm Airless10 – 15 thousandths Air-Assisted Airless11 – 15 thousandthsAIR PRESSURESGravity Feed 30-35 psi (2.0-2.4 bar) Siphon Feed 35-40 psi (2.4-2.8 bar) Air-Assisted Airless10-20 psi (0.7-1.4 bar)See spray gun manufacturer data for more information14. PHYSICAL DATAViscosity24±2” #2 Zahn at 25˚C(~77˚F)Weight Solids % 41±2% Volume Solids % 27±2%Actual VOC4.34lbs/gal of Product VOC Ratio (lb.voc/lb.solids) 1.17lb VOC/lb solidRegulatory VOC(less water and exempt solvents)576g/l Weight Per Gallon 8.68-8.875lbs/gal Flash Point-4°C (~25°F) Tag Open Cup(TOC) Theoretical Coverage 454 ft/gal @ 1 mil dry VHAP (lb.HAP/lb.solids) 0.03lb VHAP/lb solidCoating CategoryWhiteDry to touch20 - 25 Minutes Flash between coats 35 - 45 Minutes To Stack12 - 24 HoursThe data on this sheet represent typical values. Since application variables are a major factor in product performance, this information should serve only as a general guide. Axalta assumes no obligation or liability for use of this information . UNLESS AXALTA AGREES OTHERWISE IN WRITING, AXALTA MAKES NO WARRANTIES, EXPRESS ORIMPLIED, AND DISCLAIMS ALL IMPLIED WARRANTIES INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR USE OR FREEDOM FROM PATENT INFRINGEMENT. AXALTA WILL NOT BE LIABLE FOR ANY SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES. Your only remedy for any defect in thisproduct is the replacement of the defective product, or a refund of its purchase price, at our option. The information in this sheet, as well as the products referenced herein, shall beApplication Notes:All products should be stirred well before use and, for best results, continuously agitated while in use. Do not mix with other finishing systems or deviate from these finishing recommendations. Axalta will not be held liable for finish failures resulting from the mixing of products or deviations from finishing recommendations. Sandingshould be completed immediately prior to the application of any additional coats.1) Seal: NUW3390 Series lacquers are self-sealing. If a basecoat is desired, use 383-1902-00 or other approved basecoat. Refer to Technical Data Sheet for detailed use instructions. Sand with 240–320 grit stearated, silicon carbide sandpaper.2) Finish: Choose the appropriate sheen from the series, and agitate well before applying. Verify the surface is clean and dust free, and apply an even coat at 3–4 wet mils using conventional, airless, air-assisted or HVLP spray equipment.If additional coats are required, wait a minimum of 30 minutes between applications. Sand with 280–320 grit stearated, silicon carbide sandpaper before recoating. If reduction is necessary, use Axalta 390-7001-00 Lacquer Thinner. See Additional Notes portion of thisdocument for additional details. In the event of blushing or blistering, add Axalta 390-9303-00 Lacquer Retarder to extend dry time. See Additional Notes portion of this document for additional details.IMPORTANT NOTE: System’s total dry film build should not exceed 4 mils . A higher build may result in a film breakdown or reduction in performance. Clean Up:Use lacquer thinner to clean equipment. Refer to yourlocal regulations for compliance requirements for cleaning thinners, or use recommended Axalta Lacquer Thinner. Dispose of dirty solvent and cleaning rags in a safe and compliant manner. Solvent or lacquer soaked rags should be stored in water-filled, closed containers prior to disposal.Precautions:These products are recommended for professionalapplication and are designed for interior use only. Always pre-test the system on your substrate and under your line conditions to verify suitability to the application and toavoid potential need for costly refinishing. Axalta Industrial Wood Coatings are designed to protect and enhance the natural beauty of wood, but cannot eliminate natural discoloration or deterioration of wood as it ages.Additional notes:Do not mix with other finishing systems or deviate from these finishing recommendations. Axalta will not be heldliable for finish failures resulting from the mixing of products or deviations from finishing recommendations.Catalyzation: n/a Pot-Life: n/a Reduction: Max. 20% by volume 390-7001* Retarder: Max. 5% by volume 390-9303*As allowable within regulatory compliance requirementsStorage:Store in a cool, dry place. DO NOT FREEZE! Product should be stored in temperatures between 50°-110°F. Close all containers after use. Do not store near heat or sparks.Spills should be cleaned up with non-sparking tools. See the product SDS for complete safety information.Warning:Always pre-test the system on your substrate and underyour line conditions to verify suitability to the application and avoid potential need for costly refinishing. All dry times listed are as tested under ideal indoor environmental conditions of 78°F (26°C) with relative humidity notexceeding 50%. These products are recommended for use under temperature conditions of 60-100°F (16-38°C) and when relative humidity is below 50% during application and drying time. Low temperatures, poor air circulation or high humidity will extend dry times. Axalta strongly recommends against use of these products iftemperatures of air, material, or surface to be coated are below 60°F (16°C) or below the dew point.Abnormal conditions of temperature or humidity may adversely affect product performance. Please contact your authorized Axalta Industrial Wood Coatings distributor for additional product use recommendations and finishing guidance.。

SENTRON 3WL1110-2CB33-1AA2 三极固定式电路保护器说明书

General technical data Number of poles Size of the circuit-breaker Electrical endurance (switching cycles) / typical Usage category circuit-breaker / Design Mechanical service life (switching cycles) / typical
Short-time current resistance (Icw)
3WL1110-2CB33-1AA2
FIXED-MOUNTED CIRCUIT BREAKER 3-POLE, SIZE I, IEC IN=1000A TO 690V, AC50/60HZ ICU=55KA AT 500V FRNT.CONN. TOP/BOT. SINGLE-HOLE
SENTRON ACB Pushbutton Manual operating mechanism with mechanical closing No ETU25B
3 1 20 000 B 3WL1110 20 000
1 000 1 000
IP20 LSI
33.3
100
1 000
20 000
20 000
kA
● at 500 V / rated value
kA
● at 690 V / rated value
kA
55 42 29.5 24
50 60
690
1 000 1 000 1 000 1 000 1 000 1 000
Plant / motor protection
Yes No No Yes

RT9013-33GB中文资料

1DS9013-05 August 2007Pin ConfigurationsApplicationsCDMA/GSM Cellular Handsets Portable Information AppliancesLaptop, Palmtops, Notebook Computers Hand-Held InstrumentsMini PCI & PCI-Express Cards PCMCIA & New Cards500mA, Low Dropout, Low Noise Ultra-Fast Without Bypass Capacitor CMOS LDO RegulatorOrdering InformationMarking InformationFor marking information, contact our sales representative directly or through a Richtek distributor located in your area, otherwise visit our website for detail.General DescriptionThe RT9013 is a high-performance, 500mA LDO regulator,offering extremely high PSRR and ultra-low dropout. Ideal for portable RF and wireless applications with demanding performance and space requirements.The RT9013 quiescent current as low as 25μA, further prolonging the battery life. The RT9013 also works with low-ESR ceramic capacitors, reducing the amount of board space necessary for power applications, critical in hand-held wireless devices.The RT9013 consumes typical 0.7μA in shutdown mode and has fast turn-on time less than 40μs. The other features include ultra-low dropout voltage, high output accuracy,current limiting protection, and high ripple rejection ratio.Available in the SOT-23-5, SC-70-5 and WDFN-6L 2x2package.(TOP VIEW)WDFN-6L 2x2FeaturesWide Operating Voltage Ranges : 2.2V to 5.5V Low Dropout : 250mV at 500mA Ultra-Low-Noise for RF ApplicationUltra-Fast Response in Line/Load Transient Current Limiting Protection Thermal Shutdown ProtectionHigh Power Supply Rejection RatioOutput Only 1μF Capacitor Required for Stability TTL-Logic-Controlled Shutdown InputRoHS Compliant and 100% Lead (Pb)-FreeSOT-23-5 / SC-70-5RT901312 : 1.2V 13 : 1.3V 15 : 1.5V 16 : 1.6V :32 : 3.2V 33 : 3.3V 1B : 1.25V 1H : 1.85V 2H : 2.85VNote :Richtek Pb-free and Green products are :`RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.`Suitable for use in SnPb or Pb-free soldering processes.`100% matte tin (Sn) plating.EN GND NC NC VOUTVINGND VIN EN2DS9013-05 August 2007 Typical Application CircuitFunctional Pin DescriptionFunction Block DiagramV OUTENVINAbsolute Maximum Ratings (Note 1)Supply Input Voltage------------------------------------------------------------------------------------------------------6VEN Input Voltage-----------------------------------------------------------------------------------------------------------6VPower Dissipation, P D @ T A= 25°CSOT-23-5--------------------------------------------------------------------------------------------------------------------0.4WSC-70-5----------------------------------------------------------------------------------------------------------------------0.3WWDFN-6L 2x2--------------------------------------------------------------------------------------------------------------0.606WPackage Thermal Resistance (Note 4)SOT-23-5, θJA---------------------------------------------------------------------------------------------------------------250°C/WSC-70-5, θJA----------------------------------------------------------------------------------------------------------------333°C/W WDFN-6L 2x2, θJA---------------------------------------------------------------------------------------------------------165°C/W WDFN-6L 2x2, θJC---------------------------------------------------------------------------------------------------------20°C/WLead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------------260°CJunction T emperature-----------------------------------------------------------------------------------------------------125°CStorage T emperature Range--------------------------------------------------------------------------------------------−65°C to 150°C ESD Susceptibility (Note 2)HBM--------------------------------------------------------------------------------------------------------------------------2kVMM----------------------------------------------------------------------------------------------------------------------------200V Recommended Operating Conditions (Note 3)Supply Input Voltage------------------------------------------------------------------------------------------------------2.2V to 5.5VJunction T emperature Range--------------------------------------------------------------------------------------------−40°C to 125°C Ambient T emperature Range--------------------------------------------------------------------------------------------−40°C to 85°C Electrical Characteristics(V= V + 0.5V, V= V, C= C= 1μF (Ceramic), T= 25°C unless otherwise specified)To be continuedDS9013-05 August 34DS9013-05 August 2007 Note 1. Stresses listed as the above “Absolute Maximum Ratings ” may cause permanent damage to the device. These are forstress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.Note 2. Devices are ESD sensitive. Handling precaution recommended.Note 3. The device is not guaranteed to function outside its operating conditions.Note 4. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3thermal measurement standard. The case position of θJC is on the exposed pad for the WDFN-6L 2x2 packages.Note 5. Quiescent, or ground current, is the difference between input and output currents. It is defined by I Q = I IN - I OUT under noload condition (I OUT = 0mA). The total current drawn from the supply is the sum of the load current plus the ground pin current.Note 6. The dropout voltage is defined as V IN -V OUT , which is measured when V OUT is V OUT(NORMAL) - 100mV.Note 7. Regulation is measured at constant junction temperature by using a 2ms current pulse. Devices are tested for loadregulation in the load range from 10mA to 500mA.5DS9013-05 August 2007Typical Operating CharacteristicsOutput Voltage vs. Temperature1.401.421.441.461.481.501.521.541.561.581.60-50-25255075100125Temperature O u t p u t V o l t a g e (V )(°C)(C IN = C OUT = 1μ/X7R, unless otherwise specified)Dropout Voltage vs. Load Current050100150200250300350050100150200250300350400450500Load Current (mA)D r o p o u t V o l t a ge (m V )V IN = 2.5V, I LOAD = 75mA Start UpTime (5μs/Div)E N P i n V o l t a g e (V )O u t p u t V o l t a g e (V )4201.00.50RT9013-15PQWV IN = 2.5V, I LOAD = 50mA EN Pin Shutdown ResponseE N P i n V o l t a g e (V )Time (100μs/Div)O u t p u t V o l t a g e (V )420210RT9013-15PQW Quiescent Current vs. Temperature1012141618202224262830-50-250255075100125Temperature Q u i e s c e n t C u r r e n t (u A )(°C)Dropout Voltage vs. Load Current50100150200250300350050100150200250300350400450500Load Current (mA)D r o p o u t V o l t a g e (m V )6DS9013-05 August 2007 V IN = 2.5V, I LOAD= 10mA to 100mAL o a d C u r r e n t (m A )Time (100μs/Div)O u t p u t V o l t a g e D e v i a t i o n (m V )100500500-50RT9013-15PQWV IN = 2.5V, I LOAD = 10mA to 300mAL o a d C u r r e n t (m A )Time (100μs/Div)O u t p u t V o l t a g e D e v i a t i o n (m V )4002000500-50RT9013-15PQWV IN = 2.6V to 3.6V, I LOAD = 10mAI n p u t V o l t ag e D e v i a t i o n (V )Time (100μs/Div)O u t p u t V o l t a g e D e v i a t i o n (m V )3.62.6200-20RT9013-15PQWI n p u t V o l t a g e De v i a t i o n (V )Time (100μs/Div)O u t p u t V o l t a g e D e v i at i o n (m V )3.62.6200-20V IN = 2.6V to 3.6V, I LOAD = 100mART9013-15PQWTime (10ms/Div)V IN = 3.0V (By Battery), No Load NoiseTime (10ms/Div)N o i s e (μV /D i v )3002001000-100-200-300RT9013-15PQW7DS9013-05 August 2007PSRR-70-60-50-40-30-20-1001020101001000100001000001000000Frequency (Hz)P S R R (d B )Time (10ms/Div)8DS9013-05 August 2007 Applications InformationLike any low-dropout regulator, the external capacitors used with the RT9013 must be carefully selected for regulator stability and performance. Using a capacitor whose value is > 1μF on the RT9013 input and the amount of capacitance can be increased without limit. The input capacitor must be located a distance of not more than 0.5 inch from the input pin of the IC and returned to a clean analog ground.Any good quality ceramic can be used for this capacitor.The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response.The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDOs application. The RT9013 is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least 1μF with ESR is > 20m Ω on the RT9013 output ensures stability. The RT9013 still works well with output capacitor of other types due to the wide stable ESR range. Figure 1. shows the curves of allowable ESR range as a function of load current for various output capacitor values. Output capacitor of larger capacitance can reduce noise and improve load transient response,stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the RT9013and returned to a clean analog ground.Figure 1EnableThe RT9013 goes into sleep mode when the EN pin is in a logic low condition. During this condit ion, the RT9013 has an EN pin to turn on or turn off regulator, When the EN pin is logic hight, the regulator will be turned on. The supply current to 0.7μA typical. The EN pin may be directly tied to V IN to keep the part on. The Enable input is CMOS logic and cannot be left floating.PSRRThe power supply rejection ratio (PSRR) is defined as the gain from the input to output divided by the gain from the supply to the output. The PSRR is found to be⎟⎠⎞⎜⎝⎛×=ΔSupply Error ΔGain log 20 PSRR Note that when heavy load measuring, Δsupply will cause Δtemperature. And Δtemperature will cause Δoutput voltage. So the heavy load PSRR measuring is include temperature effect.Current limitThe RT9013 contains an independent current limiter, which monitors and controls the pass transistor's gate voltage,limiting the output current to 0.6A (typ.). The output can be shorted to ground indefinitely without damaging the part.Thermal ConsiderationsThermal protection limits power dissipation in RT9013.When the operation junction temperature exceeds 170°C,the OTP circuit starts the thermal shutdown function and turns the pass element off. The pass element turn on again after the junction temperature cools by 30°C.For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The power dissipation definition in device is :P D = (V IN − V OUT ) x I OUT + V IN x I QThe maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula :P D(MAX) = ( T J(MAX) − T A ) /θJARegion of Stable C OUT ESR vs. Load Current0.0010.010.1110100100200300400500Load Current (mA)R e g i o n o f S t a b l e C O U T E S R (Ω)9DS9013-05 August 2007Figure 2. Derating Curves for RT9013 PackagesWhere T J(MAX) is the maximum operation junction temperature, T A is the ambient temperature and the θJA is the junction to ambient thermal resistance.For recommended operating conditions specification of RT9013, where T J(MAX) is the maximum junction temperature of the die (125°C) and T A is the operated ambient temperature. The junction to ambient thermal resistance θJA (θJA is layout dependent) for WDFN-6L 2x2package is 165°C/W, SOT-23-5 package is 250°C/W and SC-70-5 package is 333°C/W on the standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at T A = 25°C can be calculated by following formula :P D(MAX) = (125°C − 25°C) / 165 = 0.606 W for WDFN-6L 2x2 packagesP D(MAX) = (125°C − 25°C) / 250 = 0.400 W for SOT-23-5packagesP D(MAX) = (125°C − 25°C) / 333 = 0.300 W for SC-70-5packagesThe maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA . For RT9013 packages, the Figure 2 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed.00.10.20.30.40.50.60.7012.52537.55062.57587.5100113125Ambient Temperature P o w e r D is s i p a t i o n (W )(°C)10DS9013-05 August 2007Outline DimensionA1HLSOT-23-5 Surface Mount PackageRT9013Preliminary11DS9013-05 August 2007A1HLSC -70-5 Surface Mount Package12DS9013-05 August 2007Richtek Technology CorporationHeadquarter5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C.Tel: (8863)5526789 Fax: (8863)5526611Richtek Technology CorporationTaipei Office (Marketing)8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C.Tel: (8862)89191466 Fax: (8862)89191465Email: marketing@W-Type 6L DFN 2x2 Package。

艾默生UL33UPS用户手册

iTrust UL33 系列 UPS 系统20kVA/30kVA/40kVA/60kVA用户手册艾默生网络能源有限公司iTrust UL33 系列 UPS 系统用户手册资料版本BOM 编码艾默生网络能源有限企业为客户供给全方向的技术支持，用户可与就近的艾默生做事处或用户服务中心联系，也可直接与企业总部联系。

内容若有变动，恕不另行通知。

Copyright by Emerson Network Power Co., Ltd.All rights reserved.The information in this document is subject to change without notice. No part of this document may in any form or by any means (electronic, mechanical, micro-copying, photocopying, recording or otherwise) be reproduced, stored in a retrieval system or transmitted without prior written permission from Avansys Power Co., Ltd..第一版说明内容介绍本手册主要介绍iTrust UL33 系列 UPS系统及其构成部分的特色、功能、技术参数、机械参数等，详尽说了然外面连结端口的尺寸和电气性能。

施耐德 C10N3TM100 断路器 ComPacT NSX100N 数据表

Product data sheetCharacteristicsC10N3TM100断路器 ComPacT NSX100N, 50 kA (415 VAC),TMD 脱扣单元 100 A, 3P3DT h e i n f o r m a t i o n p r o v i d e d i n t h i s d o c u m e n t a t i o n c o n t a i n s g e n e r a l d e s c r i p t i o n s a n d /o r t e c h n i c a l c h a r a c t e r i s t i c s o f t h e p e r f o r m a n c e o f t h e p r o d u c t s c o n t a i n e d h e r e i n .T h i s d o c u m e n t a t i o n i s n o t i n t e n d e d a s a s u b s t i t u t e f o r a n d i s n o t t o b e u s e d f o r d e t e r m i n i n g s u i t a b i l i t y o r r e l i a b i l i t y o f t h e s e p r o d u c t s f o r s p e c i f i c u s e r a p p l i c a t i o n s .I t i s t h e d u t y o f a n y s u c h u s e r o r i n t e g r a t o r t o p e r f o r m t h e a p p r o p r i a t e a n d c o m p l e t e r i s k a n a l y s i s , e v a l u a t i o n a n d t e s t i n g o f t h e p r o d u c t s w i t h r e s p e c t t o t h e r e l e v a n t s p e c i f i c a p p l i c a t i o n o r u s e t h e r e o f .N e i t h e r S c h n e i d e r E l e c t r i c I n d u s t r i e s S A S n o r a n y o f i t s a f f i l i a t e s o r s u b s i d i a r i e s s h a l l b e r e s p o n s i b l e o r l i a b l e f o r m i s u s e o f t h e i n f o r m a t i o n c o n t a i n e d h e r e i n .主要信息产品系列ComPacT new generation产品名称ComPacT NSX new generation产品短名NSX100N产品类型断路器产品应用配电保护极数3P保护极说明3D额定电流 [In]100 A 在…上 40 °C额定工作电压 [Ue]690 V AC 50/60 Hz电网类型AC电网频率50/60 Hz隔离功能适用符合 TM-D使用类别AC类分断能力90 KA Icu 在…上 220/240 V AC 50/60 Hz 符合 IEC 60947-250 KA Icu 在…上 380/415 V AC 50/60 Hz 符合 IEC 60947-250 KA Icu 在…上 440 V AC 50/60 Hz 符合 IEC 60947-236 KA Icu 在…上 500 V AC 50/60 Hz 符合 IEC 60947-235 KA Icu 在…上 525 V AC 50/60 Hz 符合 IEC 60947-210 KA Icu 在…上 660/690 V AC 50/60 Hz 符合 IEC 60947-2分断能力N 50 kA 415 V AC脱扣器名称TM-D脱扣器类型热磁式脱扣器保护功能LI控制类型手柄安装类型固定式补充信息额定绝缘电压 [Ui]800 V AC 50/60 Hz额定冲击耐受电压 [Uimp]8 KV使用分断能力 [Ics]90 KA 在…上 220/240 V AC 50/60 Hz 符合 IEC 60947-250 KA 在…上 380/415 V AC 50/60 Hz 符合 IEC 60947-250 KA 在…上 440 V AC 50/60 Hz 符合 IEC 60947-236 KA 在…上 500 V AC 50/60 Hz 符合 IEC 60947-235 KA 在…上 525 V AC 50/60 Hz 符合 IEC 60947-210 KA 在…上 660/690 V AC 50/60 Hz 符合 IEC 60947-2机械寿命50000 次电气寿命50000 次在…上 440 V In/230000 次在…上 440 V In20000 次在…上 690 V In/210000 次在…上 690 V In每极功耗8.8 W安装方式底板安装安装位置水平和垂直方向Flat on the back连接方式-上端前连接连接方式-下端前连接极间距35 Mm保护类型L : for 过载保护 (热保护)I : for 短路保护 (磁保护)脱扣器额定值100 A 在…上 40 °C长延时电流整定类型可调长延时电流整定值 [Ir]0.7...1 x In长延时时间整定类型固定式[tr] 长延时时间整定范围120…400 S 在…上 1.5 x In15 S 在…上 6 x Ir瞬时保护电流整定类型固定式瞬时保护整定值 [Ii]800 A漏电流保护无漏电保护槽位数 5 槽宽度105 Mm高度161 Mm深度86 Mm净重 2.05 Kg环境符合标准TM-D过电压类别Class II电击保护级别Class II污染等级 3 符合 IEC 60664-1IP 保护等级IP40 conforming to IEC 60529 IK 保护等级IK07 conforming to IEC 62262运行温度-25…70 °C贮存环境温度-50…85 °C相对湿度0…95 %工作海拔0...2000 m 不降容2000 m...5000 m 有降容包装单位Unit Type of Package 1PCENumber of Units in Package 11Package 1 Height14.0 CmPackage 1 Width11.0 CmPackage 1 Length19.5 CmPackage 1 Weight 1.786 KgUnit Type of Package 2S03Number of Units in Package 27Package 2 Height30.0 CmPackage 2 Width30.0 CmPackage 2 Length40.0 CmPackage 2 Weight12.876 Kg可持续性产品类型Green Premium 产品China Green Designed Product是REACh法规REACh 声明欧盟ROHS指令符合豁免条件无汞是中国 ROHS 管理办法中国 ROHS 声明RoHS 豁免信息是环境披露产品环境文件流通资料产品使用寿命终期信息无 PVC是合同保修保修单18 个月Product Life Status :Commercialised。

ACPL-331J CN的中文资料

ACPL-331J 1.5A电流输出的IGBT门极驱动光耦集成的（Vce）饱和度检测，欠压锁定，故障状态反馈和有源米勒钳位综述:ACPL - 331J是一种先进的1.5 A的输出电流，方便易用的智能化的门极驱动器使得IGBT的Vce的故障保护更加紧凑，价格合理，且易于实现功能，如集成的Vce检测，欠压锁定（UVLO），IGBT的“软”关断，隔离的集电极开路故障反馈和有源米勒钳位提供最大的设计灵活性和保护电路。

ACPL - 331J包含了一个GaAsP的LED。

通过该LED完成光电信号的耦合。

ACPL-331J非常适合用于驱动电机控制领域的功率IGBT和MOSFET。

这些光耦的电压、电流供给使其非常适用用于直接驱动1200V 100A以下的IGBT。

对于更高功率等级的IGBT，ACPL-331J通常被用来驱动由分离器件构成的IGBT门极驱动器。

ACPL-331J具备一个峰值为891V的绝缘电压。

结构框图：产品特点：z滞后的欠压封锁功能z饱和度侦测z米勒钳位z隔离的开路集电极故障反馈z IGBT软关断z IGBT下个开通周期的故障复位z提供SO - 16封装z安规认证详细说明：z 1.5A的最大输出峰值电流z 1.0A的最小输出峰值电流z温度范围内最大250nS的传输延时z100nS最大脉冲宽度失真z在V CM = 1500 V时，最小15 kV/µs的共模抑制能力z最大供电电流I CC(max) < 5 mAz温度范围内工作电压可达15V-30Vz1A的米勒钳位。

该脚不用时必须同VEE短接z宽的工作温度范围：–40°C to 100°C应用：z IGBT和功率MOSFET的驱动z交流和直流无刷电机驱动z变频器和UPS引脚功能介绍订货信息ACPL-331J 经过3750 Vrms 1分钟测试，符合UL1577标准。

备注表面符合IEC / EN产品编号符合ROHS 标准封装方式安装卷带装 DIN EN 60747-5-2 数量-000E SO-16 X X 45/管ACPL-331J -500E X X X 850/卷订购时，从产品编号列表中选择产品编号，并结合其他所需的选项形成定单输入。

LM337中文资料_数据手册_参数

LM337中⽂资料_数据⼿册_参数-V IN Copyright ? 2016, Texas Instruments Incorporated TO-92SOICPin 1. Output2.Adjustment3. Input3121ProductFolder Sample &Buy TechnicalDocuments Tools &Software Support &CommunityLM337LSNVS780E –MAY 1998–REVISED DECEMBER 2016LM337L 3-Terminal Adjustable Regulator1FeaturesAdjustable Output Down to 1.2V ?Ensured 100-mA Output Current ?Line Regulation Typically 0.01%/V ?Load Regulation Typically 0.1%?Current Limit Constant With Temperature ?Eliminates the Need to Stock Many Voltages ?Standard 3-Pin Transistor Package ?80-dB Ripple Rejection ?Output is Short Circuit Protected 2Applications ?Industrial Power Supplies ?Factory Automation Systems ?Building Automation Systems ?PLC Systems ?Instrumentation ? IGBT Drive Negative Gate Supplies ?Networking ?Set-Top Boxes 3Description The LM337L is an adjustable 3-pin negative voltage regulator capable of supplying 100mA over a –1.2-V to –37-V output range.The LM337L is easy to use and requires only two external resistors to set the output voltage.Both line and load regulation are better than standard fixed regulators.The LM337L is packaged in a standard,easy-to-use TO-92transistor package.In addition to higher performance than fixedregulators,the LM337L offers full overload protection.Included on the chip are current limit,thermaloverload protection,and safe area protection.Alloverload protection circuitry remains fully functionaleven if the adjustment pin is disconnected.Normally,only a single 1-µF solid tantalum output capacitor is required unless the device is situated more than 6inches from the input filter capacitors,in which case an input bypass is required.A larger output capacitor can be added to improve transient response.The adjustment pin can be bypassed to achieve very high ripple rejection ratios,which are difficult to achieve with standard 3-pin regulators.Besides replacing fixed regulators,the LM337L is useful in a wide variety of other applications.Because the regulator is floating and monitors only the input-to-output differentialvoltage,supplies of severalhundred volts can be regulated as long as themaximum input-to-output differential is not exceeded.The LM337L makes a simple adjustable switchingregulator,a programmable output regulator,or byconnecting a fixed resistor between the adjustmentand output,the LM337L can be used as a precisioncurrent regulator.Supplies with electronic shutdowncan be achieved by clamping the adjustment pin toground,which programs the output to 1.2V,wheremost loads draw little current.The LM337L is available in a standard TO-92transistor package and a standard SO-8surfacemount package.The LM337L is rated for operationover a –25°C to 125°C range.For applications requiring output current in excess of0.5A and 1.5A,The LM137series may be suitable.For the positive complement,the LM117and LM317Lseries are options.Device Information (1)PART NUMBERPACKAGE BODY SIZE (NOM)LM337L SOIC (8)3.91mm ×4.90mm TO-92(3) 4.30mm ×4.30mm (1)For all available packages,see the orderable addendum at the end of the data sheet.1.2-V to 25-V Adjustable Regulator LM337L Available PackagesLM337LSNVS780E–MAY1998–REVISED /doc/c345595427fff705cc1755270722192e453658bd.htmlTable of Contents1Features (1)2Applications (1)3Description (1)4Revision History (2)5Pin Configuration and Functions (3)6Specifications (3)6.1Absolute Maximum Ratings (3)6.2ESD Ratings (3)6.3Recommended Operating Conditions (3)6.4Thermal Information (4)6.5Electrical Characteristics (4)6.6Typical Characteristics (5)7Detailed Description (6)7.1Overview (6)7.2Functional Block Diagram (6)7.3Feature Description (6)7.4Device Functional Modes (6)8Application and Implementation (8)8.1Application Information (8)8.2Typical Applications (8)9Power Supply Recommendations (10)10Layout (10)10.1Layout Guidelines (10)10.2Layout Example (10)11Device and Documentation Support (11)11.1Documentation Support (11)11.2Receiving Notification of Documentation Updates1111.3Community Resources (11)11.4Trademarks (11)11.5Electrostatic Discharge Caution (11)11.6Glossary (11)12Mechanical,Packaging,and OrderableInformation (11)4Revision HistoryNOTE:Page numbers for previous revisions may differ from page numbers in the current version.Changes from Revision D(May2013)to Revision E Page ?Added Applications section,Device Information table,Pin Configuration and Functions section,ESD Ratings table, Recommended Operating Conditions table,Typical Characteristics section,Detailed Description section,Application and Implementation section,Power Supply Recommendations section,Layout section,Device and Documentation Support section,and Mechanical,Packaging,and Orderable Information section (1)Deleted DSBGA Package references throughout the data sheet (1)Deleted soldering information rows from Absolute Maximum Ratings table (3)Added Thermal Information table (4)Changed RθJA values for D(SOIC)package From:180To:111.3and for LP(TO-92)package From:160To:156.9 (4)Changes from Revision C(May2013)to Revision D Page ?Changed layout of National Semiconductor Data Sheet to TI format (1)LM337L/doc/c345595427fff705cc1755270722192e453658bd.html SNVS780E –MAY 1998–REVISED DECEMBER 20165Pin Configuration and FunctionsD Package8-Pin SOICTop View LP Package 3-Pin TO-92Bottom ViewPin FunctionsPINI/O DESCRIPTIONNAMETO-92SOIC ADJ14—Adjust pin NC—5,8—No connection VIN32,3,6,7Input Input voltage pin for the regulator VOUT 21Output Output voltage pin for the regulator (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings only,which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions .Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)If Military/Aerospace specified devices are required,please contact the Texas Instruments Sales Office/Distributors for availability andspecifications.6Specifications6.1Absolute Maximum RatingsSee (1)(2)MINMAX UNIT Input-output voltage differential40V Power dissipationInternally Limited Storage temperature,T stg–55150°C (1)JEDEC document JEP155states that 500-V HBM allows safe manufacturing with a standard ESD control process.Pins listed as ±1500V may actually have higher performance.(2)Human-body model,1.5k ?in series with 100pF.6.2ESD RatingsVALUEUNIT V (ESD)Electrostatic discharge Human-body model (HBM),per ANSI/ESDA/JEDEC JS-001(1)(2)±1500V 6.3Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)MINMAX UNIT Operating junction temperature –25125°CLM337LSNVS780E –MAY 1998–REVISED DECEMBER /doc/c345595427fff705cc1755270722192e453658bd.html(1)For more information about traditional and new thermal metrics,see the Semiconductor and IC Package Thermal Metrics applicationreport.6.4Thermal InformationTHERMAL METRIC(1)LM337LUNIT D (SOIC)LP (TO-92)8PINS 3PINS R θJAJunction-to-ambient thermal resistance 111.3156.9°C/W R θJC(top)Junction-to-case (top)thermal resistance 56.180.2°C/W R θJBJunction-to-board thermal resistance 51.9—°C/W ψJTJunction-to-top characterization parameter 10.624.7°C/W ψJBJunction-to-board characterization parameter 51.3136.2°C/W (1)Unless otherwise specified,these specifications apply –25°C ≤T J ≤125°C for the LM337L;|V IN –V OUT |=5V and I OUT =40mA.Although power dissipation is internally limited,these specifications are applicable for power dissipations up to 625mW.I MAX is 100mA.(2)Regulation is measured at constant junction temperature,using pulse testing with a low duty cycle.Changes in output voltage due toheating effects are covered under the specification for thermal regulation.6.5Electrical Characteristics (1)PARAMETERTEST CONDITIONS MIN TYP MAX UNIT Line regulation (2)T A =25°C,3V ≤|V IN –V OUT |≤40V 0.010.04%/V Load regulation (2)T A =25°C,5mA ≤I OUT ≤I MAX 0.1%0.5%Thermal regulationT A =25°C,10-ms Pulse 0.040.2%/W Adjustment pin current50100µA Adjustment pin current change5mA ≤I L ≤100mA,3V ≤|V IN –V OUT |≤40V 0.25µA Reference voltage3V ≤|V IN –V OUT |≤40V,10mA ≤I OUT ≤100mA,P ≤625mW 1.2 1.25 1.3V Line regulation (2)3V ≤|V IN –V OUT |≤40V 0.020.07%/V Load regulation (2)5mA ≤I OUT ≤100mA 0.3% 1.5%Temperature stabilityT MIN ≤T j ≤T MAX 0.65%Minimum load current|V IN –V OUT |≤40V 3.55mA 3V ≤|V IN –V OUT |≤15V 2.2 3.5mA Current limit3V ≤|V IN –V OUT |≤13V 100200320mA |V IN –V OUT |=40V 2550120mA RMS output noise,%of V OUTT A =25°C,10Hz ≤f ≤10kHz 0.003%Ripple rejection ratioV OUT =–10V,F =120Hz,C ADJ =065dB C ADJ =10µF 6680dB Long-term stabilityT A =125°C 0.3%1%LM337L /doc/c345595427fff705cc1755270722192e453658bd.html SNVS780E–MAY1998–REVISED DECEMBER20166.6Typical CharacteristicsFigure3.Line Transient Response Figure4.Load Transient ResponseINPUTOUTPUTADJUSTCopyright ? 2016,Texas Instruments IncorporatedLM337LSNVS780E –MAY 1998–REVISED DECEMBER /doc/c345595427fff705cc1755270722192e453658bd.html7Detailed Description7.1OverviewThe LM337L devices are adjustable 3-terminal negative-voltage regulators capable of supplying 100mA over anoutput voltage range of –1.2V to –37V.They are exceptionally easy to use,requiring only two external resistorsto set the output voltage and one output capacitor for frequency compensation.In addition,LM337L offers fulloverload protection.Included on the chip are current limit,thermal overload protection and safe area protection.All overload protection circuitry remains fully functional even if the adjustment terminal is disconnected.TheLMx37devices serve a wide variety of applications,including local on-card regulation,programmable output-voltage regulation,and precision current regulation.7.2Functional Block Diagram7.3Feature Description7.3.1Output Voltage AdjustmentThe Adjustment (ADJ)pin serves as a voltage adjustment reference for the output.The ADJ pin can be attachedto a resistor divider circuit to adjust the output voltage level.The reference voltage VADJ will typically be 1.25Vhigher than VO.7.4Device Functional Modes7.4.1Protection DiodesWhen external capacitors are used with any IC regulator,it is sometimes necessary to add protection diodes toprevent the capacitors from discharging through low current points into the regulator.Most 10-µF capacitors havelow enough internal series resistance to deliver 20-A spikes when shorted.Although the surge is short,there isenough energy to damage parts of the IC.When an output capacitor is connected to a negative output regulatorand the input is shorted,the output capacitor pulls current out of the output of the regulator.The current dependson the value of the capacitor,the output voltage of the regulator,and the rate at which VIN is shorted to ground.The bypass capacitor on the adjustment terminal can discharge through a low current junction.Discharge occurswhen either the input,or the output,is shorted.Figure 15shows the placement of the protection diodes.LM337L /doc/c345595427fff705cc1755270722192e453658bd.html SNVS780E–MAY1998–REVISED DECEMBER2016 Device Functional Modes(continued)When CL is larger than20µF,D1protects the LM337L in case the input supply is shorted.When C2is larger than10µF and?VOUT is larger than?25V,D2protects the LM337L in case the output is shorted.Figure5.Regulator With Protection DiodesOUT R2V 1.25V 1240§· ¨?:?1-V IN Copyright ? 2016, Texas Instruments IncorporatedLM337LSNVS780E –MAY 1998–REVISED DECEMBER /doc/c345595427fff705cc1755270722192e453658bd.html8Application and ImplementationNOTEInformation in the following applications sections is not part of the TI componentspecification,and TI does not warrant its accuracy or completeness.TI’s customers areresponsible for determining suitability of components for their purposes.Customers shouldvalidate and test their design implementation to confirm system functionality.8.1Application InformationThe LM337L is a negative output linear regulator with high accuracy and a wide temperature range.An outputcapacitor can be added to further improve transient response,and the ADJ pin can be bypassed to achieve veryhigh ripple-rejection ratios.The device's functionality can be utilized in many different applications that requirenegative voltage supplies,such as bipolar amplifiers,operational amplifiers,and constant current regulators.8.2Typical Applications8.2.1 1.2-V to 25-V Adjustable RegulatorFull output current not available at high input-output voltagesC1=1-µF solid tantalum or 10-µF aluminum electrolytic required for stability*C2=1-µF solid tantalum is required only if regulator is more than 4″from power supply filter capacitorFigure 6. 1.2-V to 25-V Adjustable Regulator Diagram8.2.1.1Design RequirementsThe device component count is very minimal,employing two resistors as part of a voltage divider circuit and anoutput capacitor for load regulation.An input capacitor is needed if the device is more than 4in.from the filtercapacitors.8.2.1.2Detailed Design ProcedureThe output voltage is set based on the selection of the two resistors (R1and R2)as shown in Equation 1.(1)-22 VCopyright ? 2016, Texas Instruments Incorporated LM337L/doc/c345595427fff705cc1755270722192e453658bd.html SNVS780E–MAY1998–REVISED DECEMBER2016 Typical Applications(continued)8.2.1.3Application CurveFigure7.Dropout Voltage across Load Current at25°C(?Vout<100mV8.2.2Regulator With Trimmable Output VoltageFigure8.Regulator with Trimmable Output Voltage Diagram8.2.2.1Design RequirementsThis design uses five resistors with two being used for a voltage divider circuit and the other three used for trimming the output voltage.The benefit is lower cost as compared to using a trim pot.An output capacitor is needed to improve load regulation.8.2.2.2Detailed Design ProcedureThis design will trim the output voltage to within1%of–22V.The parallel combination of R1,R3,R4and R5 serve as the bottom resistance and R2as the top resistance in the voltage divider that sets the output voltage. Trim Procedure:If V OUT is–23.08V or larger,do not use R3,otherwise leave it in.Then if V OUT is–22.47V or bigger,do not use R4,otherwise leave it in.Then if V OUT is–22.16V or bigger,do not use R5,otherwise leave it in.This will trim the output to well within1%of–22V DC,without any of the expense or trouble of a trim pot(see LB-46).This technique can be used at any output voltage level.LM337LSNVS780E–MAY1998–REVISED /doc/c345595427fff705cc1755270722192e453658bd.html 9Power Supply RecommendationsThe input supply to the LM337L must be kept at a voltage level such that its maximum input to output differential voltage rating is not exceeded.The minimum dropout voltage must also be met with extra headroom when possible to keep the LM337L in regulation.TI recommends an input capacitor,especially when the input pin is placed more than4in.away from the power-supply filter capacitor.10Layout10.1Layout GuidelinesSome layout guidelines must be followed to ensure proper regulation of the output voltage with minimum noise. Traces carrying the load current must be wide to reduce the amount of parasitic trace inductance and the feedback loop from VOUT to ADJ must be kept as short as possible.To improve PSRR,a bypass capacitor can be placed at the ADJ pin and must be placed as close as possible to the IC.In cases when VIN shorts to ground, an external diode must be placed from VIN to VOUT to divert the surge current into the output capacitor and protect the IC.Similarly,in cases when a large bypass capacitor is placed at the ADJ pin and VOUT shorts to ground,an external diode must be placed from VOUT to ADJ to provide a path for the bypass capacitor to discharge.These diodes must be placed close to the corresponding IC pins to increase their effectiveness.10.2Layout ExampleFigure9.LM337L Layout ExampleLM337L /doc/c345595427fff705cc1755270722192e453658bd.html SNVS780E–MAY1998–REVISED DECEMBER201611Device and Documentation Support11.1Documentation Support11.1.1Related DocumentationFor related documentation see the following:LM317L-N3-Terminal Adjustable Regulator(SNOSBW2)LM117,LM317-N Wide Temperature Three-Pin Adjustable Regulator(SNVS774)LM317L-N3-Terminal Adjustable Regulator(SNVS775)11.2Receiving Notification of Documentation UpdatesTo receive notification of documentation updates,navigate to the device product folder on /doc/c345595427fff705cc1755270722192e453658bd.html .In the upper right corner,click on Alert me to register and receive a weekly digest of any product information that has changed.For change details,review the revision history included in any revised document.11.3Community ResourcesThe following links connect to TI community resources.Linked contents are provided"AS IS"by the respective contributors.They do not constitute TI specifications and do not necessarily reflect TI's views;see TI's Terms of Use.TI E2E?Online Community TI's Engineer-to-Engineer(E2E)Community.Created to foster collaboration among engineers.At/doc/c345595427fff705cc1755270722192e453658bd.html ,you can ask questions,share knowledge,explore ideas and helpsolve problems with fellow engineers.Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.11.4TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.11.5Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6GlossarySLYZ022—TI Glossary.This glossary lists and explains terms,acronyms,and definitions.12Mechanical,Packaging,and Orderable InformationThe following pages include mechanical,packaging,and orderable information.This information is the most current data available for the designated devices.This data is subject to change without notice and revision of this document.For browser-based versions of this data sheet,refer to the left-hand navigation.PACKAGING INFORMATION(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check/doc/c345595427fff705cc1755270722192e453658bd.html /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.Addendum-Page 1(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.Addendum-Page 2TAPE AND REEL INFORMATION*All dimensions are nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant LM337LMX SOIC D 82500330.012.4 6.5 5.4 2.08.012.0Q1LM337LMX/NOPB SOIC D 82500330.012.4 6.5 5.4 2.08.012.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) LM337LMX SOIC D8*******.0367.035.0 LM337LMX/NOPB SOIC D8*******.0367.035.0PACKAGE OUTLINETO-92 - 5.34 mm max height LP0003A TO-92NOTES:1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. Lead dimensions are not controlled within this area.4. Reference JEDEC TO-226, variation AA.5. Shipping method:a. Straight lead option available in bulk pack only.b. Formed lead option available in tape and reel or ammo pack.c. Specific products can be offered in limited combinations of shipping medium and lead options.d. Consult product folder for more information on available options.EXAMPLE BOARD LAYOUTTO-92 - 5.34 mm max heightLP0003A TO-92。

SL33资料

SL32 THRU SL34LOW VF SURFACE MOUNT SCHOTTKY BARRIER RECTIFIERVOLTAGE - 20 to 40 Volts CURRENT - 3.0 AmperesFEATURESl Plastic package has Underwriters Laboratory Flammability Classification 94V-O l For surface mounted applications l Low profile package l Built-in strain relief l Metal to silicon rectifier majority carrier conductionl Low power loss, High efficiency l High current capability, low V Fl High surge capacityl For use in low voltage high frequency inverters, free wheeling, and polarity protection applications l High temperature soldering guaranteed: 260¢J /10 seconds at terminals MECHANICAL DA TACase: JEDEC DO-214AB molded plasticTerminals: Solder plated, solderable per MIL-STD-750, Method 2026Polarity: Color band denotes cathodeStandard packaging: 16mm tape (EIA-481)Weight: 0.007 ounce, 0.21 gramMAXIMUM RA TINGS AND ELECTRICAL CHARACTERISTICSRatings at 25¢J ambient temperature unless otherwise specified.Resistive or inductive load.SYMBOLS SL32SL33SL34UNITS Maximum Recurrent Peak Reverse Voltage V RRM 203040Volts Maximum RMS Voltage V RMS 142128Volts Maximum DC Blocking Voltage V DC 203040VoltsMaximum Average Forward Rectified Current at T L (See Figure 1)I (AV) 3.0Amps Peak Forward Surge Current 8.3ms single half sine-wave superimposed on rated load(JEDEC method)I FSM100.0Amps Maximum Instantaneous Forward Voltage at 3.0A (Note 1)V F 0.380.380.40Volts Maximum DC Reverse Current T A =25¢J (Note 1)At Rated DC Blocking Voltage T A =100¢J I R 0.520.0mA Maximum Thermal Resistance (Note 2)R £K JLR £K JA1755¢J /W Operating Junction Temperature Range T J -50 to +125¢J Storage Temperature Range T STG -50 to +150¢JNOTES:1. Pulse Test with PW=300£g s, 1% Duty Cycle.2. Mounted on P.C.Board with 14mm 2(.013mm thick) copper pad areas.S MC/DO-214ABRATING AND CHARACTERISTIC CURVES SL32 THRU SL34LEAD TEMPERATURE,¢JTYPICAL INSTANTANEOUS FORWARD CHARACTERISTICSFig. 1-FORWARD CURRENT DERATING CURVE Fig. 2-TYPICAL INSTANTANEOUS FORWARDCHARACTERISTICSREVERSE VOLTAGE. VOLTSFig. 4-TYPICAL JUNCTION CAPACITANCEPERCENT OF RATED PEAK REVERSE VOLTAGEFig. 3-TYPICAL REVERSE CHARACTERISTICSNUMBER OF CYCLES AT 60HzFig. 5-MAXIMUM NON-REPETITIVE PEAK FORWARDSURGE CURRENT。

格之格品牌硒鼓碳粉分类

B A B
120 100 100
B B B 无
3 NT-TL013 4 NT-TL013L LEXMARK 系列 BROTHER 系列 1 NT-TB012 2 NT-TB012L 松下 1 NT-T90/92/94
LENOVO 2312P/2412P/8212N/6012MFP/6112MFC/6212MFC/LJ2500 LENOVO J2312/2500/6212/6112 联想 LJ2000/LJ2050N/M7020/M7030/M7120/M7130N/M3020/M3120 BROTHER MFC-8420/8820D/8820DN/8220/8440/ 8840D/8840DN / BROTHER MFCPANSONIC KX-FL313/318/MB263/MB263/MB271/ MB763/MB772/MB773/MB781/MB783/MB261/MB771 /MB228/MB238/MB258/MB778 制表:
碳粉分类
序号 HP系列系列 1 2 3 4 5 6 7 8 9 10 11 16 24 25 26 27 28 29 30 31 36 37 38 39 40 41 42 43 44 45 46 碳粉型号 NT-T2612 NT-T2612B NT-T2612H NT-T2612L NT-T2612D NT-T7115 NT-T7115B NT-T7115H NT-T3906 NT-T3906B NT-T3906H NT-T4129 NT-T9700 NT-T9701 NT-T9702 NT-T9703 NT-T4191 NT-T4192 NT-T4193 NT-T4194 NT-T6000J NT-T6001J NT-T6002J NT-T6003J NT-T0388 NT-T0436 NT-T0388L/436L NT-T0540BK NT-T0541C NT-T0542Y NT-T0543M 灌粉量(g) A B B A A A A B A A B A A A A A A A B B B B A A A A A A A A A A A C 自产外购适用机型