AD1556ASZ;AD1555APZRL;AD1555APRL;AD1555APZ;AD1555BPZRL;中文规格书,Datasheet资料
PWM降压型DC-DC转换器MAX1556-MAX1556A-MAX1557简介
PWM降压型DC-DC转换器
MAX1556/MAX1556A/MAX1557简介
MAX1556/MAX1556A/MAX1557 是低工作电流(16micro;A)、固定频率的降压型调节器。
这些转换器具有高工作频率、低静态电流、低压差等特性，低
静态电流(27µA)使其非常适合用于1 节锂离子电池或3 节碱性/NiMH 电池供电的便携式装置。
MAX1556 最高可提供1.2A 电流，通过引脚可以选择
1.8V、
2.5V 与
3.3V 输出，或可调输出。
MAX1557 最高可提供600mA 电流，通过引脚可以选择1V、1.3V 与1.5V 输出，或可调输出。
MAX1556/MAX1556A/MAX1557 包含一个低导通电阻的内部MOSFET 开关和一个同步整流器，以最少的外部元件数提供高效、低压差指标。
采用专
有的拓扑结构，在高固定频率工作模式下，保证轻载和满载时都能保持优异的
性能。
1MHz PWM 开关频率使外部元件尺寸最小。
这两种器件都具有可调节的软启动，可以减小电池的瞬态负载变化。
MAX1556/MAX1556A/MAX1557 提供细小的10 引脚TDFN (3mm x 3mm)封装。
引脚配置：
关键特性：
●最高97%的效率
●1mA负载电流下95%的效率
●16µA低静态电流
●1MHz PWM 开关
●3.3µH小尺寸电感。
AD转换芯片介绍
高位高速AD、DA模数转换器（A/D）l 8位分辨率l TLV0831 8 位 49kSPS ADC 串行输出，差动输入，可配置为 SE 输入，单通道l TLC5510 8 位 20MSPS ADC，单通道、内部 S、低功耗l TLC549 8 位、40kSPS ADC，串行输出、低功耗、与 TLC540/545/1540 兼容、单通道l TLC545 8 位、76kSPS ADC，串行输出、片上 20 通道模拟 Mux，19 通道l TLC0831 8 位，31kSPS ADC 串行输出，微处理器外设/独立运算，单通道l TLC0820 8 位，392kSPS ADC 并行输出，微处理器外设，片上跟踪与保持，单通道l ADS931 8 位 30MSPS ADC，具有单端/差动输入和外部基准以及低功耗、电源关闭功能l ADS930 8 位 30MSPS ADC，单端/差动输入具有内部基准以及低功耗、电源关闭功能l ADS830 8 位 60MSPS ADC，具有单端/差动输入、内部基准和可编程输入范围l 10位分辨率l TLV1572 10 位 1.25 MSPS ADC 单通道 DSP/(Q)SPI IF S 极低功耗自动断电功能l TLV1571 1 通道 10 位 1.25MSPS ADC，具有 8 通道输出、DSP/SPI、硬件可配置、低功耗l TLV1549 10 位 38kSPS ADC 串行输出、固有采样功能、终端与 TLC154、TLC1549x 兼容l TLV1548 10 位 85kSPS ADC 系列输出，可编程供电/断电/转换速率，TMS320 DSP/SPI/QPSI Compat.，8 通道l TLV1544 10 位 85kSPS ADC 串行输出，可编程供电/断电/转换速率，TMS320 DSP/SPI/QPSI 兼容，4 通道l TLV1543 10 位 200 kSPS ADC 串行输出，内置自检测模式，内部 S，引脚兼容。
微雪电子 High-Precision AD DA Board 用户手册说明书
High-Precision AD/DA Board用户手册Raspberry Pi的GPIO接口没有AD/DA功能，而High-Precision AD/DA Board可以有效满足Raspberry Pi的高精度AD/DA转换的需求。
该模块支持Raspberry Pi A+/B+/2代B，具有以下特点：●板载ADS1256芯片，8通道24位高精度ADC（4通道差分输入），30ksps采样速率●板载DAC8532芯片，2通道16位高精度DAC●板载排针封装输入接口，可接入模拟信号，兼容微雪传感器接口标准，方便接入各种模拟传感器模块●板载接线端子封装输入输出接口，可接入模拟信号及数字信号，方便在各种场合使用●自带AD/DA检测电路，方便观察实验现象12板载资源[ 扩展接口]1.Raspberry Pi GPIO接口方便接入树莓派2.AD/DA输入输出接口（接线端子）方便在各种场合使用3.AD输入接口（排针）方便接入各种传感器模块（兼容微雪传感器接口标准）[ 器件介绍]4.7.68M晶振5.LM285-2.5提供ADC芯片工作基准电压6.光敏电阻7.LED输出指示灯8.10K电位器9.DAC853216位高精度DAC，2通道输出10.PWR LED电源指示灯11.ADS125624位高精度ADC，8通道（4通道差分输入）[ 跳线设置]12.ADC测试跳线13.DAC测试跳线14.电源配置跳线15.ADC参考地设置AD单端输入时，AINCOM为参考端，可接地或外部参考电平符号说明1)AD/DA输入输出接口（接线端子）（标号2）AD0-AD7：AD输入端AGND：模拟地GND：数字地VCC：工作电压（可通过电源配置跳线控制电压输出3.3V或者5V）DA0-DA1：DA输出端2)AD：AD输入接口（标号3）AD0-AD7：ADS1256模拟输入接口D0-D3：ADS1256的GPIO管脚（参考ADS1256数据手册）P22-P25：树莓派GPIO管脚AGND：模拟地3)LDR：光敏电阻（标号6）通过连接AD1和LDR之间的跳线，MCU可从AD1采集到该光敏电阻的输出电压。
常用的AD芯片
经常使用的A/D芯片之答禄夫天创作1. AD公司AD/DA器件AD公司生产的各种模数转换器(ADC)和数模转换器(DAC)(统称数据转换器)一直坚持市场领导地位，包含高速、高精度数据转换器和目前流行的微转换器系统（MicroConvertersTM )。
1.1 带信号调理、1mW功耗、双通道16位AD转换器：AD7705AD7705是AD公司出品的适用于低频丈量仪器的AD转换器。
它能将从传感器接收到的很弱的输入信号直接转换成串行数字信号输出，而无需外部仪表放大器。
采取Σ-Δ的ADC，实现16位无误码的良好性能，片内可编程放大器可设置输入信号增益。
通过片内控制寄存器调整内部数字滤波器的关闭时间和更新速率，可设置数字滤波器的第一个凹口。
在+3V电源和1MHz主时钟时， AD7705功耗仅是1mW。
AD7705是基于微控制器（MCU）、数字信号处理器（DSP）系统的理想电路，能够进一步节省成本、缩小体积、减小系统的复杂性。
应用于微处理器（MCU）、数字信号处理（DSP）系统，手持式仪器，分布式数据收集系统。
1.2 3V/5V CMOS信号调节AD转换器：AD7714AD7714是一个完整的用于低频丈量应用场合的模拟前端，用于直接从传感器接收小信号并输出串行数字量。
它使用Σ-Δ转换技术实现高达24位精度的代码而不会丢失。
输入信号加至位于模拟调制器前端的专用可编程增益放大器。
调制器的输出经片内数字滤波器进行处理。
数字滤波器的第一次陷波通过片内控制寄存器来编程，此寄存器可以调节滤波的截止时间和建立时间。
AD7714有3个差分模拟输入（也可以是5个伪差分模拟输入）和一个差分基准输入。
单电源工作（+3V或+5V）。
因此，AD7714能够为含有多达5个通道的系统进行所有的信号调节和转换。
AD7714很适合于灵敏的基于微控制器或DSP的系统，它的串行接口可进行3线操纵，通过串行端口可用软件设置增益、信号极性和通道选择。
AD-155A中文资料
10min./1cycle, PERIOD FOR 60min. EACH AXES I/P - FG:1.5KVAC O/P - FG:0.5KVAC
- FG, O/P
- FG:500VDC / 100M Ohms ~ 90% RH
- 10 ºC ~ +60 ºC(REFER TO OUTPUT DERATING CURVE), 20% - 20 ºC ~ +85 ºC, 10% 199 * 110 * 50mm 1Kg UL1950, TUV EN60950 APPROVED CISPR22(EN55022)CLASS B,EN61000 ~ 95% RH CASE:906
RESET:AUTO RECOVERY CH1:115% ~ 135% TYPE:SHUTDOWN 10V ¡Ó 0.8V ºC (0 ~ 50 ºC) 1s, 90ms, 20ms / 230VAC 19.5V( +1.5V, - 1V ) 39V ¡Ó 2V
2s, 90ms, 16ms/115VAC PF>0.92 10 ~ 500Hz, 2G I/P - O/P:3KVAC I/P - O/P, I/P
- 4 - 2,3,4,5,6,8,11;ENV50204,EN61000
- 3 - 2, - 3
1.ALL PARAMETERS ARE SPECIFIED AT 230VAC INPUT, RATED LOAD, 25 ºC 70% RH. AMBIENT. 2.TOLERANCE¡G INCLUDE SET UP TOLERANCE, LINE REGULATION, LOAD REGULATION. 3.RIPPLE & NOISE ARE MEASURED AT 20MHz BY USING A 12" TWISTED PAIR TERMINATED WITH A 0.1uF & 47uF CAPACITOR. 4.LINE REGULATION IS MEASURED FROM LOW LINE TO HIGH LINE AT RATED LOAD. 5.LOAD REGULATION IS MEASURED FROM 20% TO 100% RATED LOAD, AND OTHER OUTPUT AT 60% RATED LOAD. 6.EACH OUTPUT PROVIDE UP TO MAXIMUM CURRENT, BUT TOTAL LOAD CAN NOT EXCEED MAX. OUTPUT POWER.
ADI（Analog Devices）CN-0348电路参考设计手册说明书
电路笔记CN-0348Circuits from the Lab™ reference circuits are engineered and tested for quick and easy s ystem integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit /CN0348.连接/参考器件AD5541A 串行输入、电压输出、无缓冲型16位DAC ADA4500-2 轨到轨输入/输出、零输入交越失真放大器ADR4550超低噪声、高精度5 V 基准电压源16位单电源缓冲电压输出数模转换，积分和微分非线性误差小于±1 LSBRev. 0C i r cu i t s fr o m t h e Lab ™ ci r cu i t s fr o m An al o gD evi ces h ave b een d esi g n ed an d b u i l t b y An al o g D evi ces en g i n eer s. St an d ar d en g i n eer i n g p r act i ces h ave b een emp l o yed i n t h e d esi g n an d co n st r u ct i o n o f each ci r cu i t , an d t h ei r fu n ct i o n an d p er fo r man ce h ave b een t est ed an d ver i ed i n a l ab en vi r o n men t at r o o m t emp er at u r e. H o wever , yo u ar e so l el y r esp o n si b l e fo r t est i n g t h e ci r cu i t an d d et er mi n i n g i t s su i t ab i l i t y an d ap p l i cab i l i t y fo r yo u r u se an d ap p l i cat i o n . Acco r d i n g l y, i n n o even t sh al l An al o g D evi ces b e l i ab l e fo r d i r ect , i n d i r ect , sp eci al , i n ci d en t al , co n seq u en t i al o r p u n i t i ve d amag es d u e t o an y cau se wh at so ever co n n ect ed t o t h e u se o f an y C i r cu i t s fr o m t h e Lab ci r cu i t s. (C o n t i n u ed o n l ast p ag e)One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www Fax: 781.461.3113 ©2014 Analog Devices, Inc. All rights reserved.ADR4550CS DIN SCLK LDAC3.3VV LOGIC V DDV OUTREF AGNDDGNDSERIAL INTERFACEAD5541AADA4500-26V5V11994-001V INGNDV OUT0.1µF0.1µF1µFVOUT图1. ±1 LSB 线性16位缓冲电压输出DAC(原理示意图，未显示去耦和所有连接)评估和设计支持电路评估板CN-0348电路评估板(EVAL-CN0348-SDPZ)系统演示平台(EVAL-SDP-CB1Z)设计和集成文件原理图、布局文件、物料清单电路功能与优势图1所示电路是一款完整的单电源16位缓冲电压输出DAC ，它利用一个CMOS DAC 和一个无交越失真的创新放大器将积分和微分非线性误差保持在±1 LSB 。
AD9260ASZ;AD9260ASZRL;中文规格书,Datasheet资料
High Speed Oversampling CMOS ADC with16-Bit Resolution at a 2.5 MHz Output Word RateAD9260 Rev. CInformation furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESMonolithic 16-bit, oversampled A/D converter8× oversampling mode, 20 MSPS clock2.5 MHz output word rate1.01 MHz signal passband with 0.004 dB rippleSignal-to-noise ratio: 88.5 dBTotal harmonic distortion: –96 dBSpurious-free dynamic range: 100 dBInput referred noise: 0.6 LSBSelectable oversampling ratio: 1×, 2×, 4×, 8×Selectable power dissipation: 150 mW to 585 mW85 dB stop-band attenuation0.004 dB pass-band rippleLinear phaseSingle 5 V analog supply, 5 V/3 V digital supply Synchronize capability for parallel ADC interfaceTwos complement output data44-lead MQFPPRODUCT DESCRIPTIONThe AD9260 is a 16-bit, high-speed oversampled analog-to-digital converter (ADC) that offers exceptional dynamic range over a wide bandwidth. The AD9260 is manufactured on an advanced CMOS process. High dynamic range is achieved with an oversampling ratio of 8× through the use of a proprietary technique that combines the advantages of sigma-delta and pipeline converter technologies. The AD9260 is a switched-capacitor ADC with a nominal full-scale input range of 4 V. It offers a differential input with 60 dB of common-mode rejec-tion of common-mode signals. The signal range of each differ-ential input is ±1 V centered on a 2.0 V common-mode level. The on-chip decimation filter is configured for maximum performance and flexibility. A series of three half-band FIR filter stages provide 8× decimation filtering with 85 dB of stop-band attenuation and 0.004 dB of pass-band ripple. An onboard digital multiplexer allows the user to access data from the various stages of the decimation filter. The on-chip programmable reference and reference buffer amplifier are configured for maximum accuracy and flexibility. An external reference can also be chosen to suit the user’s specific dc accuracy and drift requirements.The AD9260 operates on a single +5 V supply, typically consuming 585 mW of power. A power scaling circuit is provided allowing the AD9260 to operate at power consump-FUNCTIONAL BLOCK DIAGRAMD SOTRBIT1–BIT16DAVREAD581-C-1Figure 1.tion levels as low as 150 mW at reduced clock and data rates. The AD9260 is available in a 44-lead MQFP package and is specified to operate over the industrial temperature range. PRODUCT HIGHLIGHTSThe AD9260 is fabricated on a very cost effective CMOS process. High speed, precision, mixed-signal analog circuits are combined with high density digital filter circuits. The AD9260 offers a complete single-chip 16-bit sampling ADC with a 2.5 MHz output data rate in a 44-lead MQFP.Selectable Internal Decimation Filtering—The AD9260 provides a high performance decimation filter with 0.004 dB pass-band ripple and 85 dB of stop-band attenuation. The filter is configurable with options for 1×, 2×, 4×, and 8× decimation. Power Scaling—The AD9260 consumes a low 585 mW of power at 16-bit resolution and 2.5 MHz output data rate. Its power can be scaled down to as low as 150 mW at reduced clock rates.Single Supply—Both the analog and digital portions of the AD9260 can operate off of a single +5 V supply, simplifying system power supply design. The digital logic will also accommodate a single +3 V supply for reduced power.AD9260Rev. C | Page 2 of 44TABLE OF CONTENTSSpecifications.....................................................................................3 Clock Input Frequency Range....................................................3 DC Specifications.........................................................................3 AC Specifications..........................................................................4 Digital Filter Characteristics.......................................................6 Digital Filter Characteristics.......................................................7 Digital Specifications...................................................................9 Switching Specifications............................................................10 Absolute Maximum Ratings..........................................................11 Thermal Characteristics............................................................11 ESD Caution................................................................................11 Terminology....................................................................................12 Pin Configuration and Function Descriptions...........................13 Typical Performance Characteristics...........................................14 Typical AC Characterization Curvesvs. Decimation Mode.................................................................15 Typical AC Characterization Curves for 8× Mode................16 Typical AC Characterization Curves for 4× Mode................17 Typical AC Characterization Curves for 2× Mode................18 Typical AC Characterization Curves for 1× Mode................19 Typical AC Characterization Curves.......................................20 Additional AC Characterization Curves.................................21 Theory of Operation......................................................................23 Analog Input and Reference Overview.......................................24 Input Span...................................................................................24 Input Compliance Range...........................................................24 Analog Input Operation............................................................24 Driving the Input........................................................................25 Reference Operation......................................................................28 Digital Inputs and Outputs...........................................................30 Digital Outputs...........................................................................30 Mode Operation.........................................................................31 Bias Pin Operation.....................................................................32 Power Dissipation Considerations...............................................33 Digital Output Driver Considerations (DRVDD).................33 Grounding and Decoupling......................................................34 Evaluation Board General Description.......................................36 Features and User Controls.......................................................36 Shipment Configuration............................................................37 Quick Setup.................................................................................37 Application Information...........................................................38 Outline Dimensions.......................................................................43 Ordering Guide.. (43)REVISION HISTORY7/04—Changed from Rev. B to Rev. CChanged “trimpot” to “variable resistor” .....................Universal Updated Format................................................................Universal Updated Outline Dimensions......................................................43 Changes to Ordering Guide (43)5/00—Changed from Rev. A to Rev. B.1/98—Changed from Rev. 0 to Rev. A.AD9260Rev. C | Page 3 of 44SPECIFICATIONSCLOCK INPUT FREQUENCY RANGETable 1.Parameter—Decimation Factor (N)AD9260 (8) AD9260 (4) AD9260 (2) AD9260 (1) Unit CLOCK INPUT (Modulator Sample Rate, f CLOCK ) 1 1 1 1 kHz min20 20 20 20 M H z max OUTPUT WORD RATE (FS = f CLOCK /N) 0.125 0.250 0.500 1 kHz min2.5 5 10 20 MHz maxDC SPECIFICATIONSAVDD = +5 V , DVDD = +3 V , DRVDD = +3 V , f CLOCK = 20 MSPS, V REF = +2.5 V , Input CML = 2.0 V T MIN to T MAX unless otherwise noted,R BIAS = 2 kΩ. Table 2.Parameter—Decimation Factor (N) AD9260 (8) AD9260 (4) AD9260 (2) AD9260 (1) Unit RESOLUTION 16 16 16 12 Bits min INPUT REFERRED NOISE (TYP) 1.0 V Reference 1.40 2.4 6.0 1.3 LSB rms typ 2.5 V Reference 1 0.68 (90.6) 1.2 (86) 3.7 (76) 1.0 (63.2) LSB rms typ (dB typ) ACCURACY Integral Nonlinearity (INL) ± 0.75 ± 0.75 ± 0.75 ± 0.3 LSB typ Differential Nonlinearity (DNL) ± 0.50 ± 0.50 ± 0.50 ± 0.25 LSB typ No Missing Codes 16 16 16 12 Bits Guaranteed Offset Error 0.9 (0.5) (0.5) (0.5) (0.5) % FSR max (typ @ +25°C) Gain Error 2 2.75 (0.66) (0.66) (0.66) (0.66) % FSR max (typ @ +25°C)Gain Error 31.35 (0.7) (0.7) (0.7) (0.7) % FSR max (typ @ +25°C) TEMPERATURE DRIFT Offset Error2.5 2.5 2.5 2.5 ppm/°C typGain Error 222 22 22 22 ppm/°C typ Gain Error 3 7.0 7.0 7.0 7.0 ppm/°C typ POWER SUPPLY REJECTION AVDD, DVDD, DRVDD (+5 V ±0.25 V) 0.06 0.06 0.06 0.06 % FSR max ANALOG INPUT Input Span V REF = 1.0 V 1.6 1.6 1.6 1.6 V p p Diff. max V REF = 2.5 V 4.0 4.0 4.0 4.0 V p p Diff. max Input (VINA or VINB) Range +0.5 +0.5 +0.5 +0.5 V min +AVDD –0.5 +AVDD –0.5 +AVDD –0.5 +AVDD –0.5 V max Input Capacitance 10.2 10.2 10.2 10.2 pF typ INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) 1 1 1 1 V typ Output Voltage Error (1 V Mode) ± 14 ± 14 ± 14 ± 14 mV max Output Voltage (2.5 V Mode) 2.5 2.5 2.5 2.5 V typ Output Voltage Error (2.5 V Mode) ± 35 ± 35 ± 35 ± 35 mV max Load Regulation 4 1 V REF 0.5 0.5 0.5 0.5 mV max 2.5 V REF 2.0 2.0 2.0 2.0 mV max REFERENCE INPUT RESISTANCE 8 8 8 8 kΩ POWER SUPPLIES Supply Voltages AVDD +5 +5 +5 +5 V (± 5%)AD9260Rev. C | Page 4 of 44Parameter—Decimation Factor (N)AD9260 (8) AD9260 (4) AD9260 (2) AD9260 (1) Unit DVDD and DRVDD +5.5 +5.5 +5.5 +5.5 V max+2.7 +2.7 +2.7 +2.7 V min Supply Current IAVDD 115 115 115 115 mA typ134 mA max IDVDD 12.5 10.3 6.5 2.4 mA typ3.5 mA max IDRVDD0.450 0.850 1.7 2.6 mA typ POWER CONSUMPTION 613 608 600 585 mW typ 630 mW max1 VINA and VINB connect to DUT CML.2Including Internal 2.5 V reference. 3Excluding Internal 2.5 V reference. 4Load regulation with 1 mA load current (in addition to that required by AD9260).AC SPECIFICATIONSAVDD = +5 V , DVDD = +3 V , DRVDD = +3 V , f CLOCK = 20 MSPS, V REF = +2.5 V , Input CML = 2.0 V T MIN to T MAX unless otherwise noted, R BIAS = 2 kΩ. Table 3.Parameter—Decimation Factor (N) AD9260(8) AD9260(4) AD9260(2) AD9260(1) UnitDYNAMIC PERFORMANCE INPUT TEST FREQUENCY: 100 kHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS 88.5 82 74 63 dB typ Input Amplitude = –6.0 dBFS 82.5 78 68 58 dB typ SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS 87.5 82 74 63 dB typ Input Amplitude = –6.0 dBFS 82 77.5 69 58 dB typ Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS –96 –96 –97 –98 dB typ Input Amplitude = –6.0 dBFS–93 –98 –96 –98 dB typ Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS 100 98 98 88 dB typ Input Amplitude = –6.0 dBFS 94 100 94 84 dB typ INPUT TEST FREQUENCY: 500 kHz Signal to Noise Ratio (SNR) Input Amplitude = –0.5 dBFS 86.5 82 74 63 dB typ80.5 dB min Input Amplitude = –6.0 dBFS 82.5 77 68 58 dB typ SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS 86.0 81 74 63 dB typ80.0 dB min Input Amplitude = –6.0 dBFS 82.0 77 68 58 dB typ Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS –97.0 –92 –89 –86 dB typ–90.0 dB max Input Amplitude = –6.0 dBFS–95.5 –96 –89 –86 dB typ Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS 99.0 92 91 88 dB typ90.0 dB maxAD9260Rev. C | Page 5 of 44Parameter—Decimation Factor (N)AD9260(8) AD9260(4) AD9260(2) AD9260(1) Unit Input Amplitude = –6.0 dBFS98 100 91 82 dB typ INPUT TEST FREQUENCY: 1.0 MHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS 85 82 74 63 dB typ Input Amplitude = –6.0 dBFS 80 76 68 58 dB typ SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS 84.5 81 74 63 dB typ Input Amplitude = –6.0 dBFS 80 76 69 58 dB typ Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS –102 –96 –82 –79 dB typ Input Amplitude = –6.0 dBFS–96 –94 –84 –77 dB typ Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS 105 98 83 80 dB typ Input Amplitude = –6.0 dBFS98 96 87 80 dB typ INPUT TEST FREQUENCY: 2.0 MHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS 82 74 63 dB typ Input Amplitude = –6.0 dBFS 76 68 58 dB typ SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS 81 73 62 dB typ Input Amplitude = –6.0 dBFS 76 69 58 dB typ Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS –101 –80 –75 dB typ Input Amplitude = –6.0 dBFS–95 –80 –76 dB typ Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS 104 80 78 dB typ Input Amplitude = –6.0 dBFS100 83 79 dB typ INPUT TEST FREQUENCY: 5.0 MHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS 59 dB typ Input Amplitude = –6.0 dBFS 57 dB typ SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS 58 dB typ Input Amplitude = –6.0 dBFS57 dB typTotal H armonic Distortion (T H D)Input Amplitude = –0.5 dBFS –58 dB typ Input Amplitude = –6.0 dBFS–67 dB typ Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS 59 dB typ Input Amplitude = –6.0 dBFS 70 dB typINTERMODULATION DISTORTION f IN 1 = 475 kHz, f IN 2 = 525 kHz –93 –91 –91 –83 dBFS typ f IN 1 = 950 kHz, f IN 2 = 1.050 MHz –95 –86 –85 –83 dBFS typDYNAMIC C H ARACTERISTICSFull Power Bandwidth75 75 75 75 MHz typ Small Signal Bandwidth (A IN = –20 dBFS) 75 75 75 75 MHz typ Aperture Jitter2 2 2 2 ps rms typAD9260DIGITAL FILTER CHARACTERISTICSTable 4.Parameter AD9260 Unit 8× DECIMATION (N = 8)Pass-Band Ripple 0.00125 dB maxStop-Band Attenuation 82.5 dB minPass-Band 0 MHz min0.605 × (f CLOCK/20 MHz) MHz maxStop-Band 1.870 × (f CLOCK/20 MHz) MHz min18.130 × (f CLOCK/20 MHz) MHz maxPass-Band/Transition Band Frequency(–0.1 dB Point) 0.807 × (f CLOCK/20 MHz) MHz max(–3.0 dB Point) 1.136 × (f CLOCK/20 MHz) MHz maxAbsolute Group Delay113.55 × (20 MHz/f CLOCK) µs maxGroup Delay Variation 0 µs maxSettling Time (to ± 0.0007%)124.2 × (20 MHz/f CLOCK) µs max4× DECIMATION (N = 4)Pass-Band Ripple 0.001 dB maxStop-Band Attenuation 82.5 dB minPass-Band 0 MHz min1.24 × (f CLOCK/20 MHz) MHz maxStop-Band 3.75 × (f CLOCK/20 MHz) MHz min16.25 × (f CLOCK/20 MHz) MHz maxPass-Band/Transition Band Frequency(–0.1 dB Point) 1.61 × (f CLOCK/20 MHz) MHz max(–3.0 dB Point) 2.272 × (f CLOCK/20 MHz) MHz maxAbsolute Group Delay1 2.90 × (20 MHz/f CLOCK) µs maxGroup Delay Variation 0 µs maxSettling Time (to ± 0.0007%)1 5.05 × (20 MHz/f CLOCK) µs max2× DECIMATION (N = 2)Pass-Band Ripple 0.0005 dB maxStop-Band Attenuation 85.5 dB minPass-Band 0 MHz min2.491 × (f CLOCK/20 MHz) MHz maxStop-Band 7.519 × (f CLOCK/20 MHz) MHz min12.481 × (f CLOCK/20 MHz) MHz maxPass-Band/Transition Band Frequency(–0.1 dB Point) 3.231 × (f CLOCK/20 MHz) MHz max(–3.0 dB Point) 4.535 × (f CLOCK/20 MHz) MHz maxAbsolute Group Delay10.80 × (20 MHz/f CLOCK) µs maxGroup Delay Variation 0 µs maxSettling Time (to ± 0.0007%)1 1.40 × (20 MHz/f CLOCK) µs max1× DECIMATION (N = 1)Propagation Delay: t PROP13 ns maxAbsolute Group Delay (225 × (20 MHz/f CLOCK)) + t PROP ns max1 To determine overall Absolute Group Delay and/or Settling Time inclusive of delay from the sigma-delta modulator, add Absolute Group Delay and/or Settling Time pertaining to specific decimation mode to the Absolute Group Delay specified in 1 ×decimation.Rev. C | Page 6 of 44AD9260Rev. C | Page 7 of 44AD9260Rev. C | Page 8 of 44Table 5. Integer Filter Coefficients for First Stage Decimation Filter (23-Tap Half-Band FIR Filter)Lower CoefficientUpper CoefficientInteger ValueH(1) H(23) –1 H(2) H(22) 0 H(3) H(21) 13 H(4) H(20) 0 H(5) H(19) –66 H(6) H(18) 0 H(7) H(17) 224 H(8) H(16) 0 H(9) H(15) –642 H(10) H(14) 0 H(11) H(13) 2496 H(12)4048Table 6. Integer Filter Coefficients for Second Stage Decimation Filter (43-Tap Half-Band FIR Filter)Lower CoefficientUpper CoefficientInteger ValueH(1) H(43) 3 H(2) H(42) 0 H(3) H(41) –12 H(4) H(40) 0 H(5) H(39) 35 H(6) H(38) 0 H(7) H(37) –83 H(8) H(36) 0 H(9) H(35) 172 H(10) H(34) 0 H(11) H(33) –324 H(12) H(32) 0 H(13) H(31) 572 H(14) H(30) 0 H(15) H(29) –976 H(16) H(28) 0 H(17) H(27) 1680 H(18) H(26) 0H(19) H(25) –3204 H(20) H(24) 0H(21) H(23) 10274 H(22)16274NOTE: The composite filter undecimated coefficients (i.e., impulse response) in the 4× decimation mode can be determined by convolving the first stage filter taps with a “zero stuffed” version of the second stage filter taps (i.e., insert one zero between samples). Similarly, the composite filter coefficients in the 8× decimation mode can be determined by convolving the taps of the composite 4× decimation mode (as previously determined) with a “zero stuffed” version of the third stage filter taps (i.e., insert three zeros between samples).Table 7. Integer Filter Coefficients for Third Stage Decimation Filter (107-Tap Half-Band FIR Filter)Lower CoefficientUpper CoefficientInteger ValueH(1) H(107) –1 H(2) H(106) 0 H(3) H(105) 2 H(4) H(104) 0 H(5) H(103) –2 H(6) H(102) 0 H(7) H(101) 3 H(8) H(100) 0 H(9) H(99) –3 H(10) H(98) 0 H(11) H(97) 1 H(12) H(96) 0 H(13) H(95) 3 H(14) H(94) 0 H(15) H(93) –12 H(16) H(92) 0 H(17) H(91) 27 H(18) H(90) 0 H(19) H(89) –50 H(20) H(88) 0 H(21) H(87) 85 H(22) H(86) 0 H(23) H(85) –135 H(24) H(84) 0 H(25) H(83) 204 H(26) H(82) 0 H(27) H(81) –297 H(28) H(80) 0 H(29) H(79) 420 H(30) H(78) 0 H(31) H(77) –579 H(32) H(76) 0 H(33) H(75) 784 H(34) H(74) 0H(35) H(73) –1044 H(36) H(72) 0 H(37) H(71) 1376 H(38) H(70) 0H(39) H(69) –1797 H(40) H(68) 0 H(41) H(67) 2344 H(42) H(66) 0H(43) H(65) –3072 H(44) H(64) 0 H(45) H(63) 4089 H(46) H(62) 0H(47) H(61) –5624 H(48) H(60) 0 H(49) H(59) 8280 H(50) H(58) 0H(51) H(57) –14268 H(52) H(56) 0H(53) H(55) 43520 H(54)68508AD9260Rev. C | Page 9 of 44DIGITAL SPECIFICATIONSAVDD = +5 V , DVDD = +5 V , T MIN to T MAX unless otherwise noted. Table 8.ParameterAD9260 Unit CLOCK 1 AND LOGIC INPUTS High Level Input Voltage(DVDD = +5 V) +3.5 V min (DVDD = +3 V)+2.1 V max Low Level Input Voltage(DVDD = +5 V) +1.0 V min (DVDD = +3 V)+0.9 V max High Level Input Current (V IN = DVDD) ± 10 µA max Low Level Input Current (V IN = 0 V) ± 10 µA max Input Capacitance5pF typ LOGIC OUTPUTS (with DRVDD = 5 V)High Level Output Voltage (I OH = 50 µA) +4.5 V min High Level Output Voltage (I OH = 0.5 mA) +2.4 V min Low Level Output Voltage 2 (I OL = 0.3 mA) +0.4 V max Low Level Output Voltage (I OL = 50 µA) +0.1 V max Output Capacitance5 pF typ LOGIC OUTPUTS (with DRVDD = 3 V)High Level Output Voltage (I OH = 50 µA) +2.4 V min Low Level Output Voltage (I OL = 50 µA)+0.7V max1 Since CLK is referenced to AVDD, +5 V logic input levels only apply.2The AD9260 is not guaranteed to meet V OL = 0.4 V max for standard TTL load of I OL = 1.6 mA.ANALOG INPUTINPUT CLOCKDATA OUTPUTDAVREAD00581-C -008Figure 8. Timing DiagramAD9260Rev. C | Page 10 of 44INPUT CLOCKRESET DAV00581-C -009Figure 9. RESET Timing DiagramSWITCHING SPECIFICATIONSAVDD = +5 V , DVDD = +5 V , C L = 20 pF, T MIN to T MAX unless otherwise noted.分销商库存信息:ANALOG-DEVICESAD9260ASZ AD9260ASZRL。
ADI General RoHS Compliance Information说明书
1.RoHS compliant definitionADI defines RoHS compliant to mean Pb, Hg, Cd, Cr (+6), PBB, PBDE, DEHP, BBP, DBP and DIBP are not intentionally added during the manufacturing process and have upper concentration limits as defined below. In addition, RoHS compliant indicates the packages can withstand a peak reflow temperature of 255 +5/-0 deg C.RoHS Banned Substance CAS Number Maximum Concentration ValueHg (Mercury) 7439-92-1 1000 ppmPb (Lead) 7439-97-6 1000 ppmCd (Cadmium) 7440-43-9 100 ppmCr(+6) (Hexavalent Chromium) 18540-29-9 1000 ppmPBB (Polybrominated Biphenyl) - 1000 ppmPBDE (Polybrominated Diethyl Ether) - 1000 ppmDEHP (Bis(2-Ethylhexyl) phthalate ) - 1000 ppmBBP (Benzyl butyl phthalate) - 1000 ppmDBP (Dibutyl phthalate) - 1000 ppmDIBP (Diisobutyl phthalate) - 1000 ppm2.RoHS compliant package materials and terminal finishesADI offers RoHS compliant solutions for most of its products. Material sets have been qualified to withstand a +255°C (+5/-0°C) peak reflow temperature. The primary terminal finishes for plastic encapsulated and hermetic products are matte Sn plating with a post plating bake (1 hour at 150°C within 24 hours of plating, implemented between EIA date code 0518-0522), SnAgCu solder spheres, and Au plating. NiPdAu is also available for select products.3.Part naming convention for RoHS complianceThe ADI legacy standard naming convention for RoHS compliant products requires the letter "Z" as a suffix to the existing part number.All Hittite legacy products are RoHS Compliant. However, the Hittite Federal products standard naming convention for RoHS compliant products requires the letter "E" as a suffix to the existing part number.All LTC legacy products bearing the suffix "#PBF OR #TRPBF” after the part number are RoHS compliant.The suffix “Z”, “E” and "#PBF or #TRPBF" generally appears at the end of the part name (i.e. after the character that denotes the package style). For example:Standard Part Name RoHS Compliant Part NameADI Legacy Products ADM1024ARU-REEL ADM1024ARUZ-REELAD648KR AD648KRZHittite Legacy Products HMC6407LP5 HMC6407LP5EHMC199AMS8TR HMC199MS8ETRLTC Legacy Products LTC1517CS5-3.3 LTC1517CS5-3.3#PBFLTC6993MPS6-4#TR LTC6993MPS6-4#TRPBFCertain products introduced to the market as RoHS compliant only (i.e. there is no standard SnPb or SnPbAg finish on these parts) do not carry a "Z" suffix, but the data sheet, web product page, part marking, and labeling clearly indicate these products as RoHS compliant.All models intended to be offered as RoHS compliant are visible to customers through the WWW ordering guide.Customers should contact Local Sales or Distributors with any new product transition requests.4.Part marking convention for RoHS complianceRoHS compliant devices have a "#" symbol marked on the top or bottom of the package. Smaller packages, such as SOT23, SC70 and TSOT, are too small to accommodate an additional character, and as a result, there is no "#" marking on the package. For these smaller packages, a unique brand code is used to denote RoHS compliance.5.China RoHSAnalog Devices products considered as EU RoHS Compliant part, do not contain any China RoHS substance above the indicated levels set forth in the People’s Republic of China Electronic Industry Standard SJ/T 11364-2006 for theRequirements for Concentration Limits for Certain Hazardous Substances in Electronic Information Product.beling for RoHS complianceShipping containers for products compliant with RoHS regulations are labeled with “RoHS Compliant” and Chinaenvironment-friendly logos. The labels also contain the Pb free external finish code (i.e., e3, e1, etc) as specified in JEDEC JESD97 standard and MSL ratings.Shipping LabelLOGOS RoHS China Environment-Friendly Use Period or EFUP *RoHSCompliantRoHS ExemptSOT23 FCOL, , Flip chip CSP BGA and Flip chip BGA_ED labeled as “RoHS with Exemption” use lead contained solder bumps that fall under Exemption 15 Lead in solders to complete a viable electrical connection between semiconductor die and carrier within integrated circuit flip chip packages9.Reflow ProfileADI advises reflow profiles should conform to JEDEC J-STD-020 standard which can be downloaded from the JEDEC website under “Free Standards”./9.Backward and forward compatibilityBackward compatibility for matte Sn, NiPdAu and Au: ADI products with matte Sn, NiPdAu, and Au finishes are backward compatible with optimized SnPb reflow processes.Backward compatibility for SnAgCu: ADI products with SnAgCu solder finishes are not backward compatible with SnPb reflow processes.Forward compatibility for SnPb: ADI products with SnPb finish are not forward compatible with +255°C (+5/-0°C) reflow processes. Concerns include weak solder joints caused by Bi in the solder paste reacting with Pb delamination resulting from package material sets that are not +255°C (+5/-0°C) compatible, and solder ball voiding caused by Pb free solder paste outgassing into the solder ball.10.Matte Sn whisker dataMatte Sn is a widely available industry standard that has been in production for many years with excellent quality and reliability. All matte Sn plated devices undergo a post plating bake for 1 hour at 150 degrees C within 24 hours of plating to mitigate Sn whisker growth. Sn whisker testing is done based on the test methodology outlined in JEDEC JESD22A121 standard (Test Method for Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes) with read-point intervals of 1000 hours or 500 cycles. Test results are in the table below.Criteria Maximum 20 um(Class 1a) Maximum 40 um(Class 2)Maximum 45 um(Class 2)Package Preconditioning Temperature HumidityStorage(30/60%RH, 4000 Hrs)High TemperatureHumidity Storage(55'C/85%RH, 4000 Hrs)Temperature Cycle(-55/+85'C,1500 Cyc)LFCSPNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableLQFPNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableMQFPNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableMINISONo precon See QSOP results See QSOP results See QSOP results Precon @ 215-220'C See QSOP results See QSOP results See QSOP results Precon @ 260'C Acceptable Acceptable AcceptablePDIPNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableCriteria Maximum 20 um(Class 1a) Maximum 40 um(Class 2)Maximum 45 um(Class 2)Package Preconditioning Temperature HumidityStorage(30/60%RH, 4000 Hrs)High TemperatureHumidity Storage(55'C/85%RH, 4000 Hrs)Temperature Cycle(-55/+85'C,1500 Cyc)PLCCNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptablePSOPNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableQSOPNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableSC70/ SOT143/ SOT23-3LdNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableSOIC_NNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableSOIC_WNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableSOT223No precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableSOT23No precon See QSOP results See QSOP results See QSOP results Precon @ 215-220'C See QSOP results See QSOP results See QSOP results Precon @ 260'C Acceptable Acceptable AcceptableSSOPNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableTQFPNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable AcceptableTSSOPNo precon Acceptable Acceptable Acceptable Precon @ 215-220'C Acceptable Acceptable Acceptable Precon @ 260'C Acceptable Acceptable Acceptable11. RoHS Compliance for Evaluation BoardsAnalog Devices evaluation boards are specifically designed for the purpose of research and development and are made available solely on a business-to-business basis and are therefore excluded from the scope of the RoHS 2 Directive.。
全志科技股份有限公司Allwinner A系列SDRAM支持列表说明书
Allwinner Axx SDRAM Support ListGeneral Description:1.The purpose of this document is the guide of DDR seclection for customer using our solution.2.There are some DDRs that not mentioned here. Since DDR is an universal device. So you can test3. Since DDR is high speed device. Please directly copy our PCB DRAM Part Template and followAbbr. and Definition of Status:Abbr.DefinitionX Do Not SupportD/S Datasheet SupportS/T Sample Tested√Sample Tested and Mass ProductionVendor Part Number Type package Density Organization A31(s)A20A23A80A33A83R58R16A64Hynix H5TQ2G83CFR-xxC DDR3FBGA 782Gb256Mx8√√S/T D/S D/S D/S D/S D/SH5TQ2G83DFR-xxC DDR3FBGA 782Gb256Mx8√√D/S D/S D/S D/S D/S D/SH5TQ2G63DFR-xxC DDR3FBGA 962Gb128Mx16D/S D/S X D/S D/S D/S D/S D/SH5TQ2G83EFR-xxC DDR3FBGA 782Gb256Mx8√√√D/S D/S D/S D/S D/SH5TQ2G83FFR-xxC DDR3FBGA 782Gb256Mx8D/S D/S D/S D/S D/S D/S D/S D/SH5TQ2G63FFR-xxC DDR3FBGA 962Gb128Mx16S/T D/S X S/T D/S D/SH5TQ4G83MFR-xxC DDR3FBGA 784Gb512Mx8D/S D/S D/S D/S D/S D/S D/S D/SH5TQ4G63MFR-xxC DDR3FBGA 964Gb256Mx16S/T S/T S/T D/S D/S S/T S/T D/SH5TQ4G83AFR-xxC DDR3FBGA 784Gb512Mx8S/T S/T√D/S D/S D/S D/S D/SH5TQ4G63AFR-xxC DDR3FBGA 964Gb256Mx16√√√S/T S/T S/T S/T S/TH5TQ4G63AFR-RDC DDR3FBGA 964Gb256Mx16S/T S/T S/T S/T H5TC2G83EFR-xxA DDR3L FBGA 782Gb256Mx8D/S D/S S/T D/S D/S D/S D/S D/SH5TC2G83FFR-xxA DDR3L FBGA 782Gb256Mx8D/S D/S D/S D/S D/S D/S D/S D/SH5TC2G63FFR-xxA DDR3L FBGA 962Gb128Mx16S/T S/T X S/T D/S D/SH5TC4G83AFR-xxA DDR3L FBGA 784Gb512Mx8S/T D/S S/T D/S D/S D/S D/S D/SH5TC4G63AFR-xxA DDR3L FBGA 964Gb256Mx16S/T S/T S/T S/T D/S S/T S/T D/S S/T H5TC4G83BFR-PBA DDR3L FBGA 784Gb512Mx8D/S D/S S/T D/S S/T D/S D/S S/TH5TC2G83EFR-xxR DDR3L-RS FBGA 782Gb256Mx8D/S D/S D/S D/S D/S D/S D/S D/SH5TC2G63DFR-xxR DDR3L-RS FBGA 962Gb128Mx16D/S D/S X D/S D/S D/S D/S D/SH5TC2G63FFR-xxR DDR3L-RS FBGA 962Gb128Mx16D/S D/S X D/S D/S D/S D/S D/SH5TC4G83AFR-xxR DDR3L-RS FBGA 784Gb512Mx8D/S D/S D/S D/S D/S D/S D/S D/SH5TC4G63AFR-xxR DDR3L-RS FBGA 964Gb256Mx16D/S D/S D/S D/S D/S D/S D/S D/SH5TC8G63AMR-PBA DDR3L FBGA 968Gb256Mx16x2CS D/S D/S X S/T S/T S/T S/T S/TH5TC8G83AMR-PBA DDR3L FBGA 788Gb512Mx8x2CS D/S D/S X D/S D/S D/S D/S D/SH5TC4G63CFR-PBA DDR3L FBGA 964Gb256Mx16D/S D/S D/S D/S D/S S/T S/T D/S S/T H9TKNNN8JDAPLR-NGN LPDDR28Gb128Mx32x2CS D/S X X D/S X D/S D/S XH9CCNNN8JTALAR-NTD LPDDR3FBGA 1788Gb128Mx32x2CS D/S X X S/T X S/T S/T XH9CCNNNBLTALAR-NTM LPDDR3FBGA 17816Gb256Mx32x2CS S/T S/TH9CKNNN8GTMPLR-NUH LPDDR3POP 1688Gb128Mx32x2CS S/T S/TH9CCNNNBJTMLAR-NUM LPDDR3POP 16816Gb256Mx32x2CSNanya（南亚）NT5CB128M8DN-xx DDR3FBGA 781Gb128Mx8D/S S/T X X X D/S D/S XNT5CB256M8GN-xx DDR3FBGA 782Gb256Mx8S/T S/T S/T D/S S/T D/S D/S S/TNT5CB256M8FN-xx DDR3FBGA 782Gb256Mx8S/T S/T S/T D/S D/S D/S D/S D/SNT5CB128M16HP-xx DDR3FBGA 962Gb128Mx16S/T S/T X S/T D/S D/SNT5CB128M16FP-xx DDR3FBGA 962Gb128Mx16D/S D/S X D/S D/S D/SNT5CB256M16BP-xx DDR3FBGA 964Gb256Mx16S/T S/T S/T S/T S/T D/S D/S S/TNT5CC512M8CN-xx DDR3L FBGA 784Gb512Mx8S/T S/T S/T D/S D/S D/S D/S D/SNT5CC256M16CP-xx DDR3L FBGA 964Gb256Mx16S/T D/S D/S D/S D/S D/S D/S D/SNT5CC256M16CP-DI DDR3L FBGA 964Gb256Mx16S/T S/T S/T S/T S/T S/T NT6CL256T32AQ-H2LPDDR3POP 1688Gb128Mx32x2CS S/T S/TNT6CL128M32AQ-H2LPDDR3POP 1684Gb128Mx32x1CS D/S D/SNT5CC256M16DP-DI DDR3L FBGA 964Gb256Mx16S/T S/T S/T S/T NT5CC128M16IP-DI DDR3L FBGA 962Gb128Mx16NT5CB64M16FP-DH DDR3FBGA 961Gb64Mx16NT6TL256T32AQ-G1LPDDR2POP 1688Gb128Mx32x2CS S/T S/TNT6TL128M32AQ-G0LPDDR2POP 1684Gb128Mx32x1CS S/T S/TNT5CC64M16GP-DI DDR3L FBGA 961Gb64Mx16Elpida EDJ2108BDBG-DJ-F DDR3FBGA 782Gb256Mx8D/S D/S D/S D/S D/S D/S D/S D/SEDJ4216EFBG-GN-F DDR3FBGA 964Gb256Mx16S/T S/T S/T S/T S/T D/S D/S S/TEDJ4208EFBG-GNL-F DDR3L FBGA 784Gb512Mx8S/T S/T D/S D/S D/S D/S D/S D/SEDJ4208EFBG-GN-F DDR3FBGA 784Gb512Mx8S/T S/T D/S D/S D/S D/S D/S D/SEDJ4216EFBG-GNL-F DDR3L FBGA 964Gb256Mx16S/T S/T S/T D/S S/T D/S D/S S/T S/T J2108DEBG-DJ-F DDR3FBGA 782Gb256Mx8D/S D/S D/S D/S D/S D/S D/S D/SAllwinner Technology CO., Ltd.ElpidaEDB8132B3MC-8D-F LPDDR28Gb128Mx32x2CS S/T X X S/T X D/S D/S XEDB8132B2MA-8D-F LPDDR28Gb128Mx32x2CS D/S X X S/T X D/S D/S XEDFA232A1MA-GD-F LPDDR316Gb256Mx32x2CS D/S X X D/S X D/S D/S XMicron MT41K256M8DA-125DDR3L FBGA 782Gb256Mx8D/S D/S S/T D/S D/S D/S D/S D/SMT41K128M16JT-125DDR3L FBGA 962Gb128Mx16S/T D/S X X X D/S D/S XMT41J128M16JT-107DDR3FBGA 962Gb128Mx16S/T S/T X X X D/S D/S XMT41K256M16HA-125DDR3L FBGA 964Gb256Mx16S/T D/S S/T S/T S/T D/S D/S S/T S/T MT41K512M8RH-125DDR3L FBGA 784Gb512Mx8D/S D/S S/T D/S D/S D/S D/S D/SMT41J256M8HX-15DDR3FBGA 782Gb256Mx8D/S D/S S/T D/S S/T D/S D/S S/TSAMSUNG K4B4G1646B-HCK0DDR3FBGA 964Gb256Mx16S/T S/T S/T D/S D/S S/T S/T D/SK4B2G1646E-BCK0DDR3FBGA 962Gb128Mx16S/T D/S X D/S D/S D/SK4B2G0846D-HCK0DDR3FBGA 782Gb256Mx8D/S D/S D/S D/S D/S D/S D/S D/SK4B2G1646Q-BCK0DDR3FBGA 962Gb128Mx16S/T D/S X D/S S/T D/S D/S S/TK4B4G1646Q-HYK0DDR3L FBGA 964Gb256Mx16S/T S/T S/T S/T S/T S/T S/T S/T S/T K4B8G1646Q-MYK0DDR3L FBGA968Gb256Mx16x2CS D/S D/S X D/S D/S S/T S/T D/SK4B4G1646D-BCK0DDR3FBGA964Gb256Mx16S/T K4E8E304ED-EGCF LPDDR3FBGA 1788Gb128Mx32x2CS D/S X X S/T X S/T S/T XK4E8E304ED-EGCE LPDDR3FBGA 1788Gb128Mx32x2CS D/S X X D/S X S/T S/T XK4E8E304ED-EGCC LPDDR3FBGA 1788Gb128Mx32x2CS D/S X X S/T X S/T S/T XK4E4E324ED-EGCF LPDDR3FBGA 1784Gb128Mx32x1CS S/T X X D/S X D/S D/S XK4P8G304EG-AGC2LPDDR2POP 1688Gb128Mx32x2CS S/T X X D/S X D/S D/S XK4E8E304EE-EGCE LPDDR3FBGA 1788Gb128Mx32x2CS D/S X X S/T X S/T S/T X S/T K4E6E304EE-EGCE LPDDR3FBGA 17816Gb256Mx32x2CS S/T S/TK4P8G304EQ-AGC2LPDDR2POP 1688Gb128Mx32x2CS S/T S/T S/T K4E8E304EE-AGCE LPDDR3POP 1688Gb128Mx32x2CS S/T S/TK4E4E164EB-EGCE LPDDR3FBGA 1784Gb128Mx32x1CS S/T S/TKingston（金士顿）D2516EC4BXGGB DDR3FBGA 964Gb256Mx16S/T S/T S/T D/S D/S S/T S/T D/SPSC/Mira (力晶)P3P4GF3BLF-GGN DDR3FBGA 784Gb512Mx8D/S S/T S/T D/S D/S D/S D/S D/S P3P4GF4BLF-GGN DDR3FBGA 964Gb256Mx16S/T S/T S/T D/S S/T D/S D/S S/T P3P4GF4BLF-GDJ DDR3FBGA 964Gb256Mx16D/S S/T S/T D/S D/S D/S D/S D/S P3P2GF3BLF-AGGN DDR3FBGA 782Gb256Mx8S/TAllwinner Technology CO., Ltd.Etron （钰创）EM6GE16EW5B-15H DDR3FBGA 964Gb 256Mx16S/T S/T S/T D/S D/S D/S D/S D/S EM6GD08EWUA-15H DDR3FBGA 782Gb 256Mx8D/S D/S S/T D/S S/T D/S D/S S/T EM6GD08EWUA-12H DDR3FBGA 782Gb 256Mx8D/SD/S S/T D/S D/S D/S D/S D/SEM6GD16EWXC-12HDDR3FBGA 962Gb 128Mx16EM6GE16EWXC-12HDDR3FBGA 964Gb 256Mx16S/T D/S D/S EM6GD08EWUC-12H DDR3FBGA 782Gb 256Mx8S/T D/S D/S EM6GE08EW8C-12H DDR3FBGA 784Gb 512Mx8S/TD/S D/SEM6GE16EWXD-12H DDR3FBGA 964Gb 256Mx16SCSemicon （华芯）HXB15H2G800BF-15H DDR3FBGA 782Gb 256Mx8S/T S/T S/T D/S D/S D/S HXB15H2G160BF-15H DDR3FBGA 962Gb 128Mx16D/S S/T X X X X HXB15H4G160BF-15HDDR3FBGA 964Gb 256Mx16S/T S/T S/T D/S S/T S/T HXB15H4G800BF-15H DDR3FBGA 784Gb 512Mx8D/S D/S S/T D/S D/S D/S HXB15H4G800AF-15HDDR3FBGA 784Gb 512Mx8D/S D/S S/T D/S D/SD/S HXB13H4G160BF(L)-13K DDR3L FBGA 964Gb 256Mx16D/S D/SD/S D/S D/S S/T S/T D/SHXB15H2G800BF-13K DDR3FBGA 782Gb 256Mx8S/THXB15H2G160BF-13KDDR3FBGA 962Gb 128Mx16PI （补丁）PMF511808DBR-KADN DDR3FBGA 782Gb 256Mx8D/S D/S S/T D/S D/S D/S PMF512816BBR-KADN DDR3FBGA 964Gb 256Mx16S/T S/T S/T D/S D/S S/T S/T D/S PMF511808BBRDDR3FBGA 782Gb 256Mx8D/S D/S S/T D/S D/S D/S eorex （森富）EM47DM0888SBA-150DDR3FBGA 781Gb 128Mx8D/S D/S X X X XEM47EM0888SBA-150DDR3FBGA 782Gb 256Mx8D/S D/S S/T D/S D/S D/S EM47CM1688SBB-150DDR3FBGA 961Gb 64Mx16D/S D/S X X X X EM47EM1688SBA-150DDR3FBGA 964Gb 256Mx16D/S S/T S/T D/S D/S D/S EM47EM3288SBA-150DDR38Gb 256Mx32S/T D/S X X XXGT （创芯）GT8UB128M16HP DDR3FBGA 962Gb 128Mx16S/T S/T X D/S D/S D/S GT8UB128M16BP DDR3FBGA 962Gb 128Mx16D/S S/T X D/S D/S D/S GT8UB256M16BP DDR3FBGA 964Gb 256Mx16S/T S/T S/T D/S D/S S/T S/T D/S GT8UB256M8EN-BG DDR3FBGA 782Gb 256Mx8D/S D/S S/T D/S D/S D/S GT8UB512M8EN-BGDDR3FBGA 784Gb512Mx8D/SD/S S/T D/S D/S D/SEG EG1L256M88BA12LH DDR3FBGA 782Gb 256Mx8D/S D/S S/T D/S D/S D/SAllwinner Technology CO., Ltd. EGElixir N2CB2G80GN DDR3FBGA 782Gb256Mx8D/S S/T S/T D/S D/S D/S N2CB4G16CP-DI DDR3FBGA 964Gb256Mx16D/S D/S S/T D/S D/S D/S华聆 xeme H2A402G1666ADBC DDR3FBGA 962Gb128Mx16H2A402G0866CD3C DDR3FBGA 782Gb256Mx8H2A404G0866ED9C DDR3FBGA 784Gb512Mx8H2C402G1666ADBC DDR3FBGA 962Gb128Mx16H2C402G0866CD3C DDR3FBGA 782Gb256Mx8H2C402G0866BD3C DDR3FBGA 782Gb256Mx8H2C404G0866ADEC DDR3FBGA 784Gb512Mx8H2C404G1666ADFC DDR3FBGA 964Gb256Mx16S/T S/T S/T S/T H2C404G0866CD8C DDR3FBGA 784Gb512Mx8H2C402G1666BDBC DDR3FBGA 962Gb128Mx16X X H2A402G0866CD3C DDR3FBGA 782Gb256Mx8XGCAI GDB41A32ED7-D1S LPDDR2POP 1684Gb128Mx32x1CS GDB42A32ED7-D1S(25nm)LPDDR2POP 1688Gb128Mx32x2CS GDB42A32ED7-D1S(30nm)LPDDR2POP 1688Gb128Mx32x2CS。
ADL5565差分放大器与AD9467 ADC接口电路设计说明书
为窄带、高中频、16位、250 MSPS 接收机前端设计带通滤波器的谐振匹配方法评估和设计支持设计和整合文件原理图、布局文件、物料清单电路功能与优势图1所示的电路是一款16位、250 MSPS 、窄带、高中频接收机前端，其中在ADL5565差分放大器与AD9467 ADC 之间提供最佳接口。
AD9467是一款缓冲输入16位、200 MSPS 或250 MSPS ADC ，具有约75.5 dBFS 的SNR 性能和介于95 dBFS 与98 dBFS 之间的SFDR 性能。
由于具有高输入带宽、低失真和高输出线性度，ADL5565差分放大器适合驱动中频采样ADC 。
本电路笔记介绍了如何设计接口电路和抗混叠滤波器才能在保持高性能的同时确保最低信号损耗的系统化过程。
使用谐振匹配方法来设计最平坦的巴特沃兹四阶带通滤波器，中心频率为200 MHz 。
电路描述使用差分放大器来驱动高速ADC 的优势包括信号增益、隔离和ADC 与源阻抗匹配。
ADL5565允许6 dB 、12 dB 或 15.5 dB 的引脚绑定增益调整。
或者，通过对输入应用两个外部电阻，可在0 dB 至15.5 dB 范围内实现更精细的增益步进。
此外，ADL5565具有高输出线性度、低失真、低噪声和宽输入带宽。
3 dB 带宽为6 GHz ，0.1 dB 平坦度为1 GHz 。
ADL5565能实现大于50 dB 的输出三阶交调截点(OIP3)。
10560-001图1. 使用ADL5565差分放大器和AD9467 ADC 完成窄带高中频应用的谐振滤波器设计电路笔记Rev.0Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page)One Technology Way, P .O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 /zh Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.为实现ADL5565和AD9467必须提供的最佳性能水平，必须严格遵循各数据手册中指定的设计原则。
ADX自动静态电机分析器系列说明书
ADXAutomated Static Motor Analyzer■Complete range of essential tests to determine motor health, analyze trends, and find faults.■These include high voltage tests for surge, PD,DC insulation resistance (IR, DA, PI), and DC HiPot (standard, step, or ramp).■Plus, low voltage testing for winding resistance,inductance, and capacitance.■Test voltages from 4 kV to 15 kV (and up to 40 kV coupled with a Megger Baker PPX.■Available with built-in armature hardware in the ADX 15A model.DESCRIPTIONFEATURESThe ADX family includes models designed to perform tests up to 15 kV. The five main options include 4 kV, 6 kV, 12 kV, 15 kV, and 15 kV-A (Armature). These analyzers can be coupled with PPX to increase test voltages to 30 kV or 40 kV for tests on high voltage motors, coils, and generators.The Megger Baker ADX is used for motor winding, coil, assembled motor, and generator testing. It will be used by Original Equipment Manufacturers, Industrial Maintenance Engineers, Motor Repair Shops, and Service Engineers working on equipment in the field for verification, validation, fault finding, and research; or to serve as part of a maintenance program. Tests Performed:■Winding Resistance ■Inductance ■Capacitance ■Insulation Resistance ■Dielectric Absorption (DA)■Polarization Index (PI)■DC HiPot ■DC Step-Voltage ■DC Continuous Ramped ■Surge analysis with EAR+™■Partial Discharge on Surge■Detachable IEC61010-compliant HV / LV Kelvin test leads ■PowerDB Dashboard secure cloud-based analysis software ■10.4-inch daylight viewable touch screen ■Industrial IP68 Waterproof Silicone Keyboard ■Choice of Manual, Automatic, or Sequence testing ■Screen-level context sensitive help ■Adaptable search capability ■Asset management tools ■Configurable Route based testing■Pulse-to-Pulse and Line-to-Line Error Area Ratio analysis ■Import existing databases from AWA and DX ■Android operating system■ 2 x USB ports and ethernet connection ■HDMI port for duplicating screens ■Wi-Fi and Bluetooth enabled ■Foldable viewing standBENEFITS■Asset-centric approach provides opportunities for turnkey testing.■Sequence mode leverages the approach for fully-automatic testing.■Data analysis features identify service needs and reduce down time.■Remote asset configuration via PowerDB Dashboard frees the ADX for testing needs.■Separating Asset from Installation opens opportunities for dataanalysis.DATA STORAGE, ANALYSIS, REPORT GENERATION, AND MANAGEMENTAll test results are saved and stored locally on the ADX, and are automatically synchronized with the cloud-based application PowerDB Dashboard for users with internet connection.Test results can be analyzed through Dashboard. Comparing current and historical data can reveal downward trends and other issues, indicating when action should be taken to service assets and avoid unplanned downtime.The built-in Report Generator provides on-board test result viewing that can be sent directly to a printer. Reports can be printed from the ADX wirelessly to a networked printer, or directly via a USB-connected printer. Data can be accessed securely through PowerDB Dashboard to view and download reports in either MS Word or PDF. Data can also be exported in other formats such as CSV.The ADX can function as an off-line system, utilizing PowerDB Print Engine software to create, edit, and print reports on a local computer. Data is transferred via ADX export to a USB drive, uploaded to a local computer, and edited as anMS Word document.ADX software allows users to easily create, view, and edit assets, test configurations, installations, and routes. The asset-centric approach provides administrators and management with all the tools needed to set up a turnkey environment, simplifying the asset testing process for operators.Asset configuration can be done directly on the ADX or remotely via PowerDB Dashboard. The integrated system allows access through any internet-connected device to create and edit assets, test configurations, installations, and routes. No matter where the changes are made, they are automatically synchronized between the ADX and PowerDB Dashboard via internet connection.EASE OF USEThe ADX has a large, 10.4-inch touch screen. The industrial-grade, daylight-viewable color display was designed to work in all environments. The user interface features large, intuitive icons for easy touch operation—even when an operator is wearing insulated electrical gloves.ADDITIONAL KEY FEATURES■High-definition graphical user interface displays surge test waveforms.■Displays DC HiPot results.■Displays hundreds of coil waveforms for quick analysis.■Stores reference waveforms for comparison coil testing.■Secure cloud-based data storage■Ability to create and edit assets and test configurations remotely through PowerDB Dashboard■Internal battery backup secures data due to unexpected power loss.ACCESSORIESMegger DLRO Connect systemUsed for low-voltage testing along with the RLC adapter.Number Description Part Number1014-0291 ADX modular lead, DLRO Connect accessories. Connects to the ADX RLC adapter andextension lead.1006-4602 Duplex connector extension lead3 m long. Connects to ADX modular lead and anyDLRO Connect termination.3 Duplex connector handspike probe with spring-loaded tips. 1006-4504 Duplex connector concentric handspike. 1006-4485 Duplex connector handspike twist probe with spring-loaded tips. 1006-4496 Duplex connector Kelvin clip 1. Touch-proof clip with adjustable jaws. 1006-4517 Duplex connector Kelvin clip 1. General-purpose heavy-duty clip. 1006-447Remote Test Status Indication Lights and Remote E-StopNumber Description1 Remote Test Status Indication Lights E-Stop (TSIL-ES).2 Remote Test Status Indication Lights (TSIL). A Stop Jumper must be installed on the open connector if a remoteE-Stop (1) is not used.Foot switchYou can connect the footswitch (optional) to the Megger Baker ADX host or auxiliary units; it works in parallel with the Start (PTT) button. The footswitch enables hands-free use of the unit and gives you additional operating position options.Surge Test Probes and ClipsThe Megger Baker ADX features accessories that facilitate surge testing including the Megger ADX Armature Surge Hand-held Probes (ADX-ASP), which are used during armature bar-to-bar testing.ADX Armature Surge ClipsThe ADX Armature Surge Clips (ADX-ASC) are commonly used during coil and DC motor testing. The longer middle section of the clips employs a shielded cable.ADX Armature Surge accessoryFor armature bar-to-bar surge testing, you can use the ADX Armature Surge accessory— (ADX ARM SRG).NOTICE: Armature surge test and other fixtures used with legacy equipment are not compatible with the ADX tester.SPECIFICATIONSPhysical specificationsModel Mass Size (W x D x H)ADX1546.3 lbs. (21 kg)18 x 23 x 8.5 in (457 x 584 x 216 mm) ADX15A50.7 lbs. lbs. (23 kg)18 x 23 x 8.5 in (457 x 584 x 216 mm) System specificationsParameter ValueInternal memory RAM 2GB DDR3Internal storage 8GB MMC and 480GB SSD DriveProcessor speed 1.0 Ghz (Quad core)User interface Capacitive touch screen, mouse, keyboard, stylus Platform AndroidDisplay 10.4-in touch screenResolution XGA 1024 x 768Bluetooth 4.1 / BLE with CSA2 supportWi-Fi 802.11 a/b/g/n Dual Band 2.4 / 5 GHzEthernet Gigabit Ethernet 10/100/1000 MbpsUSB flash drive USB 2.0Battery Backup 4+ hours standby timeLanguages supported—user interface and documentation localizationLanguage Regional TranslationsEnglishFrench EuropeSpanish Europe and Latin AmericaPortuguese Europe and BrazilGermanCzechRussianChinese Traditional and SimplifiedInstrument rating summaryParameter Variant / Option ValueInternal and operating environment Pollution degree 2Operating altitude ≤ 3,000 m (9,842 ft)Operating temperature 5–40° C (41–104° F)Operating humidity ≤ 80% RH for temperature up to 31°C (88° F),decreasing linearly to 50% RH at 40° C (104° F). Storage temperature 0–60° C (32–140° F)Ensure that the unit has sufficient time to warm to ambient temperature beforeoperating after storing the unit in a colder area.Storage humidity Less than 95% non-condensing.IP Rating IP40Mains Power Input 90–264 VAC, 47–63 Hz, 2.5 A,CAT II 300 VMaximum generated voltage Peak voltage for AC or DC test ADX4 Nominal 100 V–4 kV ADX6 Nominal 100 V–6 kV ADX12 Nominal 100 V–12 kV ADX15 Nominal 100 V–15 kV ADX15A Nominal 100 V–15 kVMaximum input voltage rating Must be connected only to isolated, de-energizedcircuits. See Caution below.Standard Kelvin 4-wire test leads voltage rating 16 kV DC peakCAUTIONThe ADX must be connected only to isolated, de-energized circuits. Connection to live circuitry can expose personnel to severe electrical shock risk, permanently damage tester, and void warranty. Refer to chapter 1, “General Operating and Safety Information” for complete information on safely connecting and operating the unit.DC IR and HiPot test specificationsParameter Variant ValueVoltage accuracy ± 2% ± 5 VMaximum output current 1.2 mADisplayed current resolution 1 nACurrent measurement resolution 16 pACurrent accuracy Test voltage 0–2 kV ± 4% ± 5 nATest voltage 2–4 kV ± 4% ± 10 nATest voltage 4–8 kV ± 4% ± 25 nA Overcurrent trip settings Adjustable to 1.2 mA Overcurrent trip settings IR measurement range 100 kΩ–1 TΩ IR measurement range Surge test specificationsParameter Variant ValueNominal surge capacitance 100 nFTypical surge energy 11.25 J at 15 kV Typical short circuit current 700 ARepetition rate 4 Hz nominal Minimum inductance 4 kV 70 µH6 kV 100 µH12 kV 120 µH15 kV 170 µHVoltage accuracy ±10%Surge with Partial Discharge (PD) test specificationsParameter ValueInception and extinction voltages (PDIV, PDEV) Measured per IEC 61934 Repetitive inception and extinction voltages (RPDIV, RPDEV) Measured per IEC 61934 Programmable PD threshold range (Resolution to 0.1 mV) 1.0–999 mVPD time scaling 1.024–26,400 µsResistance test specificationsParameter Value Measurement range 0.001 mΩ–1 MΩ4-wire measurement YesMaximum test current 10 AAccuracy ±2% ±0.25 mΩ Inductance test specificationsParameter Value Measurement range 0.01 µH–10 H (120 Hz)0.01µH–200 mH (1000 Hz)4-wire measurement YesTest frequency 120, 1000 Hz Capacitance test specificationsParameter Value Measurement range 0.01 nF–50 µF4-wire measurement YesTest frequency 4000 HzAccuracy ±5% ±1 nFADX testing and safety standards complianceStandard TopicIEC 61326-1 Ed. 2.0 2012-07 Electrical equipment for measurement, control, and laboratory use - EMC requirements –Table 1.FCC 47CFR: Part 15 Subpart B: 2020 Unintentional RadiatorsICES-003 Issue 7, October 2020 Limits and Methods of Measurement to Information Technology Equipment (includingDigital Apparatus).IEC 61010-031:2015 Safety requirements for electrical equipment for measurement, control, and laboratoryuse. Safety requirements for hand-held probe assemblies for electrical measurement andtest.IEC 61010-2-034:2017 Safety requirements for electrical equipment for measurement, control, and laboratoryuse. Particular requirements for measurement equipment for insulation resistance and testequipment for electric strength.IEC 62133-2:2017 Safety Test Standard of Li-IonCISPR 11:2009 +A1:2010, Class A Radiated Emissions and AC Mains Conducted EmissionsIEC 61000-3-2:2014 HarmonicsIEC 61000-3-3:2013 FlickerIEC 61000-4-2:2009 Electro-Static Discharge Immunity TestIEC 61000-4-3:2010 Radiated, Radio-Frequency, Electromagnetic ImmunityIEC 61000-4-4:2012 Electrical Fast Transient/Burst Immunity TestIEC 61000-4-5:2006 Immunity to SurgesIEC 61000-4-8:2010 Power Frequency Magnetic Field Immunity TestIEC 61000-4-11:2004 Voltage Dips/Interruptions Immunity TestORDERING INFORMATIONItem Description PartNumber Item Description PartNumberADX 44 kV Standard ADX with DC Insulation Resistance (IR, DA, PI), DC HiPot (standard, Step, Ramp), and Surge tests only. 1013-911 ADX 1212 kV Standard ADX with DC InsulationResistance (IR, DA, PI), DC HiPot (standard,Step, Ramp), and Surge tests only.1013-913ADX-4-RLC4 kV Standard ADX with RLC (low voltage Resistance, Inductance, and Capacitance), DC Insulation Resistance (IR, DA, PI), DC HiPot (standard, Step, Ramp), and Surge tests. 1013-916 ADX-12-RLC12 kV Standard ADX with RLC (low voltageResistance, Inductance, and Capacitance), DCInsulation Resistance (IR, DA, PI), DC HiPot(standard, Step, Ramp), and Surge tests.1013-918ADX-4-RLC-PD4 kV Standard ADX with RLC (low voltage Resistance, Inductance, and Capacitance), DC Insulation Resistance (IR, DA, PI), DC HiPot (standard, Step, Ramp), Surge, and Partial Discharge tests. 1013-920 ADX-12-RLC-PD12 kV Standard ADX with RLC (low voltageResistance, Inductance, and Capacitance), DCInsulation Resistance (IR, DA, PI), DC HiPot(standard, Step, Ramp), Surge, and PartialDischarge tests.1013-922ADX-4-RLC-PD-PPI4 kV Standard ADX with RLC (low voltage Resistance, Inductance, and Capacitance), DC Insulation Resistance (IR, DA, PI), DC HiPot (standard, Step, Ramp), Surge, and Partial Discharge tests. Includes Power Pack Interface. 1013-925 ADX-12-RLC-PD-PPI12 kV Standard ADX with RLC (low voltageResistance, Inductance, and Capacitance), DCInsulation Resistance (IR, DA, PI), DC HiPot(standard, Step, Ramp), Surge, and PartialDischarge tests. Includes Power PackInterface.1013-927ADX-66 kV Standard ADX with DC Insulation Resistance (IR, DA, PI), DC HiPot (standard, Step, Ramp), and Surge tests only. 1013-912 ADX-1515 kV Standard ADX with DC InsulationResistance (IR, DA, PI), DC HiPot (standard,Step, Ramp), and Surge tests only.1013-914ADX-6-RLC6 kV Standard ADX with RLC (low voltage Resistance, Inductance, and Capacitance), DC Insulation Resistance (IR, DA, PI), DC HiPot (standard, Step, Ramp), and Surge tests. 1013-917 ADX-15-RLC15 kV Standard ADX with RLC (low voltageResistance, Inductance, and Capacitance), DCInsulation Resistance (IR, DA, PI), DC HiPot(standard, Step, Ramp), and Surge tests.1013-919ADX-6-RLC-PD6 kV Standard ADX with RLC (low voltage Resistance, Inductance, and Capacitance), DC Insulation Resistance (IR, DA, PI), DC HiPot (standard, Step, Ramp), Surge, and Partial Discharge tests. 1013-921 ADX-15-RLC-PD15 kV Standard ADX with RLC (low voltageResistance, Inductance, and Capacitance), DCInsulation Resistance (IR, DA, PI), DC HiPot(standard, Step, Ramp), Surge, and PartialDischarge tests.1013-923ADX-6-RLC-PD-PPI6 kV Standard ADX with RLC (low voltage Resistance, Inductance, and Capacitance), DC Insulation Resistance (IR, DA, PI), DC HiPot (standard, Step, Ramp), Surge, and Partial Discharge tests. Includes Power Pack Interface. 1013-926 ADX-15-RLC-PD-PPI15 kV Standard ADX with RLC (low voltageResistance, Inductance, and Capacitance), DCInsulation Resistance (IR, DA, PI), DC HiPot(standard, Step, Ramp), Surge, and PartialDischarge tests. Includes Power PackInterface.1013-928Item Description PartNumber Item Description PartNumberADX-15A15 kV Standard ADX with DC Insulation Resistance (IR, DA, PI), DC HiPot (standard, Step, Ramp), and Surge tests only. Includes Armature testing hardware and accessories. 1013-915 Megger Baker Test Station Indication Lights(TSIL)Remote accessory box that displays flashingred light when actively testing and greenlight when no testing is in progress.1014-108ADX-15A-RLC-PD6 kV Standard ADX with RLC (low voltage Resistance, Inductance, and Capacitance), DC Insulation Resistance (IR, DA, PI), DC HiPot (standard, Step, Ramp), Surge, and Partial Discharge tests. Includes Armature testing hardware and accessories. 1013-924 Megger Baker Test Status Indication LightEquipment Stop (TSIL-ES)Remote accessory box for ADX equipmentstop with a button press. Also displaysflashing red light when actively testing andgreen light when no testing is in progress1014-109FootswitchAllows operators to initiate a test using thefoot switch rather than the ADX front panelpush-to-test switch during coil testing.1014-110 Pelicase 1014-115ADX Armature Surge Accessory 1014-103 ADX Backpack 1014-114 ADX Armature Surge Probes 1014-104 ADX Test Lead - 15kV Red and labeling kit 1014-116 ADX Armature Surge Clips 1014-105 ADX Test Lead - 15kV Black 1014-117ADX Low Voltage Kelvin Test Leads with Clips 1011-928 2 x ADX Duplex 3-meter test leads withDuplex pistol type probes1014-029ADX Low Voltage Kelvin Test Leads with Probes 1011-929 2 x DLRO Duplex 3-meter test leads - 4mmplugs to Connect system socket1014-072ADX Standard Test Lead Set 1014-106 ADX Keyboard 1014-111 ADX Custom Test Lead Set 1014-107 ADX Front Cover 1014-112For complete Megger Baker Instruments EU declarations of conformity visit https:///company/about-us/legal/eu-dofcCONTACT INFORMATIONSales Office: Megger Baker Instruments 4812 McMurry Avenue, Fort Collins, CO 80525, USATelephone: +1 970-282-1200Email: **********************Web: /baker。
低噪声、低功耗高精度运放的SPICE模型建立
Application Note 1556Building an Accurate SPICE Model for Low Noise, Low Power Precision AmplifiersAbstractIn today's fast moving competitive markets, more and more customers are requesting SPICE models to run comprehensive circuit simulations. System engineers are requiring increasingly accurate models for all types of integrated circuits. Earlier SPICE models (1980) had to minimize the number of nonlinear elements to minimize simulation time, all at the cost of accuracy. T oday's models, thanks to the advancement of computing power, can increase the number of nonlinear elements and improve the accuracy of the models. The focus of this Application Note is to provide a method for developing a multi-stage SPICE model for low noise and low power operational amplifiers. The model presented, started with the work from Mark Alexander and Derek F. Bowers from Analog Devices (Appnote AN-138, 1990) [1]. The final model ended up with several key architectural changes that were required to model today's low noise, and low power precision amplifiers.This application note provides a systematic process that simplifies the understanding of how to build an accurate straightforward SPICE model. This is accomplished by a model architecture that processes the input signal through several stages. The model parameters can easily be calculated using a hand calculator or Excel spreadsheet. The application note does not discuss the process of using SPICE, and assumes the user is familiar with this software.The model presented in this application note is theISL28127 single-pole 10MHz amplifier. The model enables the user to simulate important AC and DC parameters of an amplifier. For higher speed amplifiers, with multiple poles and zeros, reference AN-138 [1]. The AC parameters incorporated into the model are: 1/f and flat-band noise, slew rate, CMRR, gain and phase. The DC parameters are VOS, IOS, total supply current and output voltage swing. The model uses typical(+25°C) parameters given in the “Electrical Specifications” table of the data sheet [2]. IntroductionThe key to an accurate model is the input stage. The closer you model the input stage to the actual amplifier, the better your results. With only a few of the process parameters of the input stage transistors or MOSFETs, you can achieve very accurate AC representation of the amplifiers performance.Another advantage of this model's architecture is the ability to model amplifiers with split supplies. There is no ground reference in any of the signal processing blocks. Instead, after the differential to single-ended conversion, all internally generated node voltages are referenced to the mid point of the supplies, much like the actual operation of an amplifier.Discussed in this application note are the following topics:1.The different cascaded stages of the SPICE Model:-Voltage Noise Stage-Input Stage-1st Gain Stage-2nd Gain Stage-Mid Supply Stage-Supply Isolation Stage-Common Mode Gain Stage-Output Stage2.How the VCCS stages works3.How the VCCS output stage works4.Systematic process for calculating modelparameters5.Simulation results. Actual device vs simulation6.ConclusionsCascaded StagesFigure 1 is the schematic for the SPICE model and Figure2 is the net list. Notice from the schematic, the only circuitry resembling an amplifier is the Input Stage. All other stages process the input signal with Voltage Controlled Current Sources (VCCS) and Voltage Controlled Voltage Sources (VCVS) along with diodes, DC supplies, simple resistors, capacitors and inductors.The circuit schematic is built from eight different functional blocks. Each block is discussed in the following sections, with details of the blocks’ functionality and design considerations.Author: Don LaFontaineFIGURE 1.SPICE SCHEMATICV IN -V OUTV+V-+-+-+-+-+-D12R17377.4IOS1E-9R15E11R25E11DN0.1V V5In+VIN-VCMSUPERBQ1Q2SUPERBCASCODECASCODEQ4Q5R34.45k R44.45k IEE196E-6D1DXMIRRORQ3IEE 200E-6123456V +++-+-V IN +242545V ++Vc VMIDV --VCM+-VOS 10E-6+-+-D2DX D3DX V11.86V V21.86VG1G2R51R6145V ++111210+-+-+-+-D4DX D5DXV31.86V V41.86VG3G4R7572.9E6R8Vg1413C255.55pFC3R91R10155.55pF572.9E6VmidVmid +-+-G5G6R111R121817L13.18E-3L23.18E-31VCMEOS+-+-ISY 2.2mAV ++V-V++-+-G7G8R1590R16222390V --VCMVc+-+-D10DYD11DYD8DX D9DX D6DXD7DXVgV ++V --V --+-+-V5V61.12V1.12VVg +-+-VcG10G9VOUT2021897EnVOLTAGE NOISEINPUT STAGE1ST GAIN STAGE MID SUPPLY REF 2ND GAIN STAGECOMMON MODE GAIN STAGESUPPLY ISOLATION STAGEE2E3OUTPUT STAGEC62pFC42.5pF C52.5pF* source ISL28127_SPICEmodel* Revision C, August 8th 2009 LaFontaine* Model for Noise, supply currents, 150dB f=50Hz CMRR, *128dB f=5Hz AOL*Copyright 2009 by Intersil Corporation*Refer to data sheet “LICENSE STATEMENT” Use of *this model indicates your acceptance with the*terms and provisions in the License Statement. * Connections: +input* |-input* | | +Vsupply* | | | -Vsupply* | | | | output* | | | | |.subckt ISL28127subckt Vin+ Vin-V+ V- VOUT* source ISL28127_SPICEMODEL_0_0**Voltage NoiseE_En IN+ VIN+ 25 0 1R_R17 25 0 377.4D_D12 24 25 DNV_V7 24 0 0.1**Input StageI_IOS IN+ VIN- DC 1e-9C_C6 IN+ VIN- 2E-12R_R1 VCM VIN- 5e11R_R2 IN+ VCM 5e11Q_Q1 2 VIN- 1 SuperBQ_Q2 3 8 1 SuperBQ_Q3 V-- 1 7 MirrorQ_Q4 4 6 2 CascodeQ_Q5 5 6 3 CascodeR_R3 4 V++ 4.45e3R_R4 5 V++ 4.45e3C_C4 VIN- 0 2.5e-12C_C5 8 0 2.5e-12D_D1 6 7 DXI_IEE 1 V-- DC 200e-6I_IEE1 V++ 6 DC 96e-6V_VOS 9 IN+ 10e-6E_EOS 8 9 VC VMID 1**1st Gain StageG_G1 V++ 11 4 5 0.0487707G_G2 V-- 11 4 5 0.0487707R_R5 11 V++ 1R_R6 V-- 11 1D_D2 10 V++ DXD_D3 V-- 12 DXV_V1 10 11 1.86V_V2 11 12 1.86**2nd Gain StageG_G3 V++ VG 11 VMID 4.60767E-3G_G4 V-- VG 11 VMID 4.60767E-3R_R7 VG V++ 572.958E6R_R8 V-- VG 572.958E6C_C2 VG V++ 55.55e-12C_C3 V-- VG 55.55e-12D_D4 13 V++ DXD_D5 V-- 14 DXV_V3 13 VG 1.86V_V4 VG 14 1.86**Mid supply RefR_R9 VMID V++ 1R_R10 V-- VMID 1I_ISY V+ V- DC 2.2E-3E_E2 V++ 0 V+ 0 1E_E3 V-- 0 V- 0 1**Common Mode Gain Stage with ZeroG_G5 V++ VC VCM VMID 31.6228e-9G_G6 V-- VC VCM VMID 31.6228e-9R_R11 VC 17 1R_R12 18 VC 1L_L1 17 V++ 3.183e-3L_L2 18 V-- 3.183e-3**Output Stage with Correction Current Sources G_G7 VOUT V++ V++ VG 1.11e-2G_G8 V-- VOUT VG V-- 1.11e-2G_G9 22 V-- VOUT VG 1.11e-2G_G10 23 V-- VG VOUT 1.11e-2D_D6 VG 20 DXD_D7 21 VG DXD_D8 V++ 22 DXD_D9 V++ 23 DXD_D10 V-- 22 DYD_D11 V-- 23 DYV_V5 20 VOUT 1.12V_V6 VOUT 21 1.12R_R15 VOUT V++ 9E1R_R16 V-- VOUT 9E1*.model SuperB npn+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12+ kf=0 af=0.model Cascode npn+ is=502E-18 bf=150 va=300 ik=17E-3 rb=140+ re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f + kf=0 af=0.model Mirror pnp+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185+ re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12 + kf=0 af=0.model DN D(KF=6.69e-9 AF=1).MODEL DX D(IS=1E-12 Rs=0.1).MODEL DY D(IS=1E-15 BV=50 Rs=1).ends ISL28127subcktFIGURE 2.SPICE NET LISTVoltage Noise StageThe first stage in the model schematic, moving from left to right, is the Voltage Noise Stage. This stage generates the 1/f and flat-band noise. T o generate a flat-bandvoltage noise of a precision amplifier with only 4nV/√Hz, all diodes and transistor model parameters kf (flicker noise coefficient) and af (flicker noise exponent) need to be set to zero. T o lower the noise floor of the model to single digit nanovolts, it may be necessary to reduce the network's Johnson noise [3] by reducing the resistance values where possible. Before reducing the resistor values, the process is to calculate the standard resistor values and complete all simulation tweaks. Once this is done, the last step is to tweak the Voltage Noise Stage by dropping the resistor values to 1Ω while recalculating the g m and time constants of the stages to maintain the same transfer function for that stage. Resistors R 5, R 6, and R 9 thru R 12 are resistors that can easily be set to 1Ω. For amplifiers with noise levels in the flat-band range of 100's of nV , reducing the network's Johnson noise may not be necessary. Initial noise simulations will tell you if this step is necessary. With the model's flat-band noise set below the amplifier's noise floor , the user can now adjust the 1/f and flat-band noise with adjustments to DN, R 17 and V 5.Input StageThe ISL28127 was selected for this application note to illustrate the level of accuracy obtainable by modeling an amplifiers exact input structure. The Input Stage of the ISL28127 consists of five bipolar transistors that model the actual device configuration, as shown in Figure 1. This however will not be the case for most SPICE models. Figure 3 and Figure 4 show typical NMOS and PMOS input stages respectively.The Input Stage can be configured with the same type of input device (NPN, PNP , P and N channel MOSFETs or J-FETS) as the physical op amp being modeled. The Input Stage includes a current supply to model IOS, a voltage supply to model VOS and a VCVS along with R 1 and R 2 to account for CMRR of the device.1st Gain StageThe purpose of the 1st Gain Stage is to set the combined gain of the Input Stage and the 1st Gain Stage to 1.Setting the combined gains to 1 simplifies the calculation to determine the slew-rate limiting components in the 2nd Gain Stage. Diodes D 2 and D 3 along with DCsupplies V 1 and V 2 might be unnecessary, because their function is to clamp the output voltage swing and were going to do that in the next stage. We left them in because they're free. DC supply voltages V 1 and V 2should be slightly larger than V 3 and V 4 in the 2nd Gain Stage. The thought is to limit most of the signalamplitude in the 1st stage and do the final amplitude tweak in the 2nd stage.2nd Gain StageThe 2nd Gain Stage is where the AVOL, bandwidth and slew-rate of the amplifier are set using G 3, G 4, R 7, R 8, C 2 and C 3. Diodes D 4 and D 5 along with DC supplies V 3 and V 4 are used to set the maximum output voltage swing.Mid Supply Reference StageThe Mid Supply Reference Stage is simply two equal resistors R 9 and R 10. These resistors are used togenerate a mid supply reference voltage. The resistor values are set to 1Ω to reduce the Johnson voltage noise of the model. The high current that flows through these resistors is transparent to the model user because of theSupply Isolation Stage, more free stuff.FIGURE 3.TYPICAL NMOS INPUT STAGEFIGURE 4.TYPICAL PMOS INPUT STAGECommon Mode Gain StageThe Common Mode Gain Stage consists of two VCCS's that drive two equal resistors in series with an inductor connected to the supply rails. The inductors simulate the typical fall-off of CMRR that most amplifiers exhibit as the input frequency is increased. The current sources are controlled by the input common mode voltage (generated by resistors R1 and R2 in the Input Stage) relative to the mid supply voltage. Each control source has a g m equal to the reciprocal of the associated resistor value divided by the CMRR of the amplifier at DC (Equation 10). The inductors add a zero to the common-mode gain, which is equivalent to adding a pole to the CMRR. The common-mode voltage, after being scaled and appropriately frequency shaped, is then added back into the Input Stage via the VCVS called EOS. Supply Isolation StageThe Supply Isolation Stage consists of two VCVS's and a current source. This stage enables the user to program the total supply current of the amplifier with just one entry in the node list. It also isolates the internal supply currents from the external supply current seen by the user. This enables the model to provide the correct supply current for low power amplifiers with low voltage noise.Output StageThe operation of the Output Stage is not entirely obvious. The amplifier's output signal, after receiving all the appropriate frequency shaping, appears as a voltage referenced to mid supply at the inputs to G7 and G8. G7 and G8 drive two equal resistors connected to the supply rails and act as active current generators. Both G7 and G8 generate just enough current to provide the desired voltage drop across its parallel resistor. Refer to the section “How the VCCS Output Stage Works” on page6. When there is no load on the output, the model draws no current from either supply rail, thus behaving like an amplifier output. Simulating the right output resistance means the DC open loop gain will be properly reduced as the amplifier is loaded.When a load is applied to the output, equal currents will be pulled from both supply rails. T o make the output behave like a real amplifier, G9 and G10 force the appropriate amount of current to make it appear as if all the current is being sourced or sunk from the correct supply.Output short circuit protection is provided by diodes D6 and D7 along with DC supplies V5 and V6. Under fault conditions, the output voltage is clamped to the previous frequency shaping stage. The output short circuit current limit is determined by adjusting the value of V5 and V6.How the VCCS Stage WorksWhen the voltage at the inputs to G1 and G2 (Figure 5) increases, the resultant voltage at the Midpoint will rise. Likewise, when the voltage at the inputs decrease, the midpoint voltage will decrease. If the g m of the stage is equal to the reciprocal of the parallel resistor, the stage has a positive unity gain.The single-ended equivalent circuit of Figure 5 is shown in Figure 6. The circuit shown in Figure 6 is sometimes easier to help visualize the signal flow through the stages.FIGURE 5.HOW THE VCCS WORKS+-+-G1G2R51ΩR61ΩV++111210+-V--MIDPOINT VOLTAGE+-INPUT VOLTAGE GOES UP•CURRENT GOES UP•NET CURRENT THROUGH R5DROPS•MIDPOINT VOLTAGE GOES UP V+-INPUT VOLTAGE GOES UP•CURRENT GOES UP•NET CURRENT THROUGH R6GOES UP•MIDPOINT VOLTAGE GOES UP FIGURE 6.SINGLE-ENDED EQUIVALENT CIRCUIT TO FIGURE 5 +-R#1Ω12+-V+-MIDPOINT VOLTAGEHow the VCCS Output Stage WorksFigure 7 explains how the Output Stage works for a steady input voltage, an increasing input voltage and a decreasing input voltage.A Systematic Process forCalculating Model ParametersT able 1 is a list of the amplifiers parameters required to calculate the model parameters. The values shown in the table are for the ISL28127 model.Once the values in T able 1 are determined, the model parameters given in Equations 1 through 15 can be calculated and put into the SPICE schematic.The following equations will determine the modelparameters for the SPICE schematic. Putting them into an Excel spreadsheet will enable the user to change critical specs and quickly see the effect on the op amp performance. The calculations are given for each stage of the model.Input Stage and Gain Stage CalculationsThe process to set the Slew Rate and unity gainbandwidth, for a single pole stage, is accomplished in 3steps:•Determine the Capacitor value knowing IEE and the Slew Rate (Equation 1). This effectively sets themaximum frequency for the single pole RC network, and therefore the unity gain bandwidth.•Determine the Resistor value knowing the dominant pole frequency (Equation 2). This effectively sets the break point for the RC network.•Determine the g m of the VCCS knowing the desired AVOL and R value of the RC network. STEP 1IEE is the value of the current source feeding the input differential pair (reference Figure 1). Under Slew Rate conditions, instantaneously all of this current is flowing through one side of the differential pair (until the feedback loop catches up). Equation 1 is used tocalculate the capacitor value to set the Slew Rate of the model. Equation 1 is basically I C = Cdv/dt , with Slew Rate equal to dv/dt and IEE equal to I C .Equation 2 calculates the value of the resistor for a set capacitor value of C 2,3 and dominant pole frequency fp1. STEP 2Where f p1 = dominant pole (reference Figure 8).TABLE 1.DEVICE PARAMETERSPARAMETERVALUE UNITSCOMMENTSQuiescent Supply Current 2.2E-3A VCC 15V VEE -15V IEE 200E-6A Differential input current sourceSlew Rate 3.6E6V/sec Fp15Hz Dominant Pole (Figure 8)AVOL 2640E3V/V 128.43dBVOS 1E-5V IOS1E-9A Temperature 25C Vt0.0257V Differential Input Resistance 5E-11ΩDefault value if unknown CMRR3.16E7V/V150dBFIGURE 7.HOW THE VCCS OUTPUT STAGE WORKSV OUT+-+-G7G8R1590ΩR1690ΩVOUTOUTPUT STAGE+-+-V+-INPUT VOLTAGE CONSTANT •VOLTAGE DROP ACROSS RESISTORS EQUALLY OPPOSE EACH OTHER •OUTPUT VOLTAGE STAYS AT MID SUPPLY INPUT VOLTAGE GOES UP •CURRENT REDUCES IN R15•CURRENT INCREASES IN R16•MIDPOINT VOLTAGE GOES UP INPUT VOLTAGE GOES UP •CURRENT INCREASES IN R15•CURRENT REDUCES IN R16•MIDPOINT VOLTAGE GOES DOWNFcm 50Hz Common mode poleRout 45 ΩIsc 45mA Voh 13.7V Vout max Vol-13.7VVout maxTABLE 1.DEVICE PARAMETERS (Continued)PARAMETER VALUE UNITS COMMENTSC 2C 3IEESlewRate----------------------------==(EQ. 1)C 2C 3200106–×3.6106–×---------------------------- 55.55pF ===R 7R 812πf p1C 23,---------------------------==(EQ. 2)R 7R 812π5()55.55pF ()------------------------------------------- 572.958M Ω===Figure 8 shows the relationship of the unity gainbandwidth to the dominant pole frequency and AVOL.STEP 3Once again, the 1st Gain Stage is used to set thecombined gain of the input stage and the 1st Gain Stage to 1. The voltage required at the input of G 3 and G 4 to cause 200 x 10-6 to flow through R 7 and R 8 is calculated in Equation 4.During Slew Rate limit, the current through either resistor R 3 or R 4 will be clamped by the 200 x 10-6 current sink. Which resistor has the current depends upon the polarity of the input voltage (positive R 4,negative R 3). This current will flow through the 4.45k Ω resistor resulting in a voltage drop of (200 x 10-6) x (4.45k Ω) = 890mV . This voltage drop appears at the input to G 1 and G 2. In order to set the combined gain of the input stage and the 1st stage to one, we need to calculate the g m of G 1 and G 2 so their output voltage equals 43.4mV (Equation 4) when 890mV is at their inputs. If we set the resistor value in parallel with the outputs of G 1 and G 2 to 1Ω, then the voltage will equal the current and we can write Equation 5 to solve for the g m of G 1 and G 2.If the design review document is not available, set R 3 and R 4 to 1Ω for the calculation of the voltage appearing at the inputs to G 1 and G 2.Equations 7 and 8 are used to set V 1 through V 4voltages for the maximum output voltage swing. The output voltage will be clamped at a voltage equal to V ++-(V 1,3+ V D2,D4) for positive input voltage swings and V --+ (V 2,4 + V D3,D5) for negative input voltage swings.Where V T = 0.02585V at T = +25°C.I S = 1 x 10-12 A (for both diodes).You can substitute some data sheet parameters directly into the model. These parameters are:EOS = Input Offset Voltage (DC component only).IOS = Input Offset Current.C diff = Input differential capacitance (not shown in this model).Common-Mode Gain StageWhere fcm is common-mode pole from the CMRR vsFrequency curve (similar to the dominant frequency pole shown in Figure 8).Output StageSetting the g m equal to the reciprocal of 2R OUT results in unity gain through G7-G10. The value of 2R OUT results from the need to have the output currents appear to be coming from one supply rail.Simulation ResultsFigures 9 through 14 compare actual device performanceto simulation results. For a complete set of comparisons, reference the data sheet [2].FIGURE 8.AVOL vs FREQUENCYG 3G 4AVOLR 78,----------------==(EQ. 3)G 3G 426406×10572.9586×10--------------------------------- 4.63–×10===g m I V ---V G 34,Ig m -------2006–×104.63–×10------------------------43.4mV===⇒=(EQ. 4)G 1G 2g m I V---43.4103×890103–×----------------------------48.77103–×===⇒=(EQ. 5)R 3R 4 4.45k Ω==from design review ()(EQ. 6)V 13,V CC V OUTMAX ()–V T Ln 2I EE I S ------------⎝⎠⎜⎟⎛⎞+=(EQ. 7)V 24,V –OUTMAX ()V EE –V T Ln 2I EE I S ------------⎝⎠⎜⎟⎛⎞+=(EQ. 8)R 11R 121M Ω==(EQ. 9)G 7G 81R 1112,CMRR ×-------------------------------------------==(EQ. 10)L 1L 2R 1112,2πfp cm ()--------------------------==(EQ. 11)G 7G 8G 9G 1012R OUT -------------------====(EQ. 12)R 15R 162R OUT×==(EQ. 13)V 3I SC 0.764()R OUT V T Ln 20106×I S ----------------------⎝⎠⎜⎟⎛⎞–=(EQ. 14)V 4I SC 0.764()R OUT V T Ln 20106×I S ----------------------⎝⎠⎜⎟⎛⎞–=(EQ. 15)Characterization vs Simulation ResultsFIGURE 9.CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 10. SIMULATED INPUT NOISE VOLTAGEFIGURE 11.CHARACTERIZED CLOSED LOOP GAIN vsFREQUENCY FIGURE 12.SIMULATED CLOSED LOOP GAIN vsFREQUENCYFIGURE 13.CHARACTERIZED CLOSED LOOP GAIN vsR f /R gFIGURE 14.SIMULATED CLOSED LOOP GAIN vs R f /R gFREQUENCY (Hz)110100I N P U T N O I S E V O L T A G E (n V /√H z )0.11101001k 10k 100k V S = ±19V A V = 1FREQUENCY (Hz)110100I N P U T N O I S E V O L T A G E (n V /√H z )0.11101001k 10k 100kV(INOISE)FREQUENCY (Hz)G A I N (d B )100k 1M10M100M10k1k-10010203040506070100A V = 1A V = 100 A V = 1000V S = ±15V V OUT = 100mV P-PC L = 3.5pF R L = INFR g = 100, R f = 100kR g = 10k, R f = 100k A V = 10R g = 1k, R f = 100kR g = OPEN, R f = 0FREQUENCY (Hz)G A I N (d B )100k 1M10M100M10k1k-10010203040506070100A V = 1A V = 100 A V = 1000R g = 10k, R f = 100k A V = 10R g = OPEN, R f = 0R g = 1k, R f = 100kR g = 100, R f = 100k-5-3-113579111315FREQUENCY (Hz)100k 1M 10M 100M10k1kR f = R g = 100kR f = R g = 100R f = R g = 10kR f = R g = 1kV S = ±15VR L = 10k A V= +2V OUT = 100mV P-P C L = 3.5pF N O R M A L I Z E D G A I N (d B )-5-3-113579111315FREQUENCY (Hz)100k 1M 10M 100M10k1kV S = ±15VR L = 10k A V= +2V OUT = 100mV P-P C L = 3.5pF R f = R g = 100kR f = R g = 100R f = R g = 10k R f = R g = 1kN O R M A L I Z E D G A I N (d B )Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.For information regarding Intersil Corporation and its products, see FIGURE 15.CHARACTERIZED CLOSED LOOP GAIN vs R L FIGURE 16.SIMULATED CLOSED LOOP GAIN vs R LFIGURE 17.CHARACTERIZED CLOSED LOOP GAIN vs C L FIGURE 18.SIMULATED CLOSED LOOP GAIN vs C LFIGURE 19.CHARACTERIZED LARGE SIGNAL 10V STEPRESPONSE FIGURE 20.SIMULATED LARGE SIGNAL 10V STEPRESPONSE-5-4-3-2-1012FREQUENCY (Hz)N O R M A L I Z E D G A I N (d B )100k 1M 10M100M10k1kV S = ±15V A V = +1V OUT = 100mV P-PC L = 3.5pF R L = 499R L = 100R L = 49.9R L = 10kR L = 1k-5-4-3-2-1012FREQUENCY (Hz)N O R M A L I Z E D G A I N (d B )100k 1M 10M100M10k1kV S = ±15V A V = +1V OUT = 100mV P-PC L = 3.5pF R L = 499R L = 100R L = 49.9R L = 10k R L = 1kFREQUENCY (Hz)100k 1M 10M100M10k1k-3-2-101234567V S = ±15V R L = 10k A V = +1V OUT = 100mV P-PC L = 1000pF C L = 220pFC L = 100pF C L = 25.5pFC L = 3.5pFN O R M A L I Z E D G A I N (d B )N O R M A L I Z E D G A I N (d B )FREQUENCY (Hz)100k 1M 10M100M10k1k-3-2-101234567V S = ±15V R L = 10k A V = +1V OUT = 100mV P-PC L = 25.5pFC L = 100pFC L = 220pFC L = 3.5pFC L= 1000pFTIME (µs)L A R G E S I G N A L (V )-6-5-4-3-210123456051015202530TIME (µs)L A R G E S I G N A L (V )V S = ±15V A V = 1C L = 3.5pF V OUT = 10V P-PR f = 0, R g = INF R L = 10kConclusionsThis Application Note has presented a method for building an accurate straightforward SPICE model for today's low noise and low power precision amplifiers. The extremely close simulation to actual part comparison results was achieved by taking advantage of today's improved computing power and modeling 5 bipolartransistors with their specific model parameters for each type of transistor . Improvements to previous models include the ability to model single digit nanovolt noise parameters and very low total system supply currents for micro-powered amplifiers.AcknowledgmentI would like to thank Oscar Mansilla for all his help with the SPICE software, and especially his help withgenerating sub-circuits from a node list and building my own libraries in SPICE.I would also like to thank Bob Pospisil for his technical expertise with op amps and helping me solve various problems along the way.References[1]Mark Alexander and Derek F . Bowers, ApplicationNote AN-138, “SPICE-Compatible Op Amp Macro-Models”, Analog Devices.[2]ISL28127, ISL28227 FN6633 Intersil data sheet/data/fn/fn6633.pdf .[3]Derek F . Bowers, IEEE 1989, “Minimizing Noise inAnalog Bipolar Circuit Design”, Precision Monolithics, Inc.FIGURE 21.SIMULATED OPEN-LOOP GAIN, PHASE vsFREQUENCY FIGURE 22.SIMULATED OPEN-LOOP GAIN, PHASE vsFREQUENCYFIGURE 23.CHARACTERIZED CMRR vs FREQUENCYFIGURE 24. SIMULATED CMRR vs FREQUENCYO P E N L O O P G A I N (d B )/P H A S E (°)FREQUENCY (Hz)-100-80-60-40-200204060801001201401601802000.1m 1m 10m 100m 1101001k 10k 100k 1M 10M 100MR L = 10k SIMULATION C L = 10pF GAIN PHASE 0.1Hz 10Hz 1.0k100k 10M-100-50050100150200FREQUENCY (Hz)O P E N L O O P G A I N (d B )/P H A S E (°)PHASEGAINR L = 10k MODEL V OS SET TO C L = 10pFZERO FOR THIS TEST 0C M R R (d B )1001k10k100k1M10MFREQUENCY (Hz)1020406080100120-101030507090110130R L = INF A V = +1V CM = 1V P-PC L = 5.25pF V S = ±15VV S = ±2.25VV S = ±5V10m1.0Hz100Hz 10k 1.0M 100M10G 1.0T-50050100150FREQUENCY (Hz)C M R R (d B )GENERATED USING FULL MODEL. CMRR DELTA INPUT BASE VOLTAGE/V CM INPUT VOLTAGE。
AD1955并联解码器开发文档
AD1955 并联式音频解码器设计开发介绍引言：现今，数字音频已经是最主要的音频传播途径，如CD、ape、mp3等等。
数字音频的音频源无一例外的都是以数字信号0/1来记录数据，只是通过一系列编码标准进行序列化，构成不同的格式。
这些数据是录音室通过话筒、拾音器等进行录取、放大后再进行A/D模数转换得到的。
而我们播放这些数字音频源的过程就是一个相反的过程，数字源通过播放器进行D/A数模转换，而数模转换的好坏就直接引响到了音频信号的保真度。
数模转换的芯片，世界很多著名的半导体厂家都有在做，如philips（飞利浦）、TI/BB（德州仪器/布尔布朗）、ADI、AKM、Cirrus、Wolfson（欧胜）等等，而且他们开发出一些列不同架构、不同档次的产品，甚至有些是格式标准的制定者。
半导体厂家的下线整机厂商（CD 厂、mp3播放器厂）使用的D/A芯片方案的不同，则基本可以决定产品音频重放的好坏。
我们可以听到有人盛赞某品牌的CD机，功放机，也有人会骂某某品牌的东西是垃圾。
这些除了跟厂家的产品定位有关外，另外最重要的一点是厂家利字当头。
所以价格和档次在商品世界里永远是无法兼得的。
而有相当大的一部分人，偏又着迷于高保真音乐的魅力，古人也说过余音绕梁，三日不绝，这都是说法而已，也可说是这类瘾君子的借口，但是的确可见声音魅力之无穷。
市售的音频类产品，如CD机，高档的很多都是天价，动辄上万。
有钱人当然不会在意，但是对升斗小民来说，这些机器可能永远都是梦，无法企及的。
毛主席教导过，自己动手，丰衣足食。
如果我们有一点电子基础，而且渴望获得高档器材的，何不自己做来？设计目标：设计一款音质较好的独立式解码器，来弥补普通音频设备在音乐重放上的不足。
设计思考：利用手头可利用的资源，音频源可以是普通的桌面电脑、笔记本、普通CD机、DVD 机等等，这些在现代家庭中，基本上都是属于常见的。
这些家用设备，本身都已经可以直接接耳机或者功放来播放音乐了，但是因为成本因素，厂家使用的器件都比较廉价，不能满足高保真重放的要求。
常用ad芯片
常用ad芯片AD芯片是模拟信号（Analog-to-Digital Converter）转换器的简称，是一种将连续的模拟信号转换为数字信号的集成电路。
AD芯片有着广泛的应用领域，在通信、电力、汽车、医疗等领域都得到了广泛应用。
常用的AD芯片包括AD7685、ADS1256、ADS1115、MAX11156等。
以下就这几款常用的AD芯片进行简要介绍。
AD7685是一款高速、16位的AD芯片，它具有低功耗、小型封装等特点。
AD7685采用了SPI接口，具有高采样率和低失调。
它在工业控制、仪器仪表、电力传感和通信等领域广泛应用。
ADS1256是一款带有24位ΔΣADC的AD芯片，采用SPI接口。
它具有低噪声、低功耗、高精度等特点，适用于精密仪器、称重系统和传感器等领域。
ADS1115是一款带有16位ADC的AD芯片，采用I2C接口。
它具有低功耗、高精度、内部参考电压等特点，适用于电源监控、温度测量、压力测量等应用。
MAX11156是一款带有12位ADC的AD芯片，采用SPI接口。
它具有低功耗、高采样率、低失调等特点，适用于医疗仪器、消费电子和通信设备等领域。
除了上述常用的AD芯片，还有许多其他AD芯片，它们根据不同的应用需求有不同的特点。
AD芯片的选择需要根据具体的应用场景和要求来确定，包括采样率、精度、功耗、通信接口等因素。
总的来说，AD芯片在现代电子设备中发挥着重要的作用，它实现了模拟信号向数字信号的转换，为我们提供了准确的数据处理基础。
随着科技的不断发展，AD芯片的性能也在不断提高，未来它将在更多的领域发挥更大的作用。
亚德诺 宽带中频接收机子系统 AD6676 数据手册说明书
ADI 中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI 不对翻译中存在的差异或由此产生的错误负责。
如需确认任何词语的准确性，请参考ADI 提供的最新英文版数据手册。
宽带中频接收机子系统AD6676Rev. BDocument FeedbackInformation furnished by Analog Devices is believed to be accurate and reliable. However , noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved. Technical Support 功能框图L–L+RESETBVDDIO AGC4, AGC3AGC2, AGC1VDD2NVVSSAVDD2VDDD VSSDSPICSB SCLK SDIO SDOSERDOUT0+SERDOUT0–SERDOUT1+SERDOUT1–VDDHSI SYNCINB±SYSREF±AGC SUPPORTCLOCK GENERATION–2.0V REGJ E S D 204B S E R I A L I Z E R T x O U T P U T SMxM = 12,16, 24,32IQQDDC +NCO IQBAND-PASS Σ-� ADCVIN–VIN+27dB ATTENUATOR(1dB STEPS)CLOCKSYNTHESIZER JESD204B SUBCLASS 1CONTROLCLK+CLK–VDDCVDDQ AD667612348-001VDDL VDD1VSS2OUT VSS2IN图1.产品特性高瞬时动态范围噪声系数(NF)低至13 dB噪声频谱密度(NSD)低至−159 dBFS/Hz I I P3高达36.9 dBm ，杂散音低于−99 dBFS 可调谐带通Σ-Δ型模数转换器(ADC) 信号带宽：20 MHz 至160 MHz 中频中心频率：70 MHz 至450 MHz可配置输入满量程电平：−2 dBm 至−14 dBm 易于驱动的阻性中频输入1 dB 增益平坦度，带外峰化低于0.5 dB 混叠抑制大于50 dB2.0 GSPS 至3.2 GSPS ADC 时钟速率 片内PLL 时钟倍频器 16位I/Q 速率高达266 MSPS 片内数字信号处理NCO 和正交数字下变频器(QDDC) 可选抽取系数：12、16、24和32 支持自动增益控制(AGC)片内衰减器范围为27 dB 、步进为1 dB通过可配置AGC 数据端口实现衰减器快速控制 具有可编程阈值的峰值检测标志 单通道或多通道，支持JESD204B低功耗：1.20 W电源电压：1.1 V 和2.5 V TDD 省电高达60% 4.3 mm × 5.0 mm WLCSP应用宽带蜂窝基础设施设备和中继器 点对点微波设备 仪器仪表频谱分析仪和通信分析仪 软件定义无线电概述AD66761是一款高度集成的中频子系统，可数字化高达160 MHz 的射频(RF)频段，并且此频段在70 MHz 至450 MHz 中频(IF)范围内为宽度居中。
ad通道额定值
ad通道额定值什么是AD通道额定值？AD通道额定值是指模拟数字转换器（Analog to Digital Converter）中用来表示模拟量输入范围的数值。
AD通道额定值通常以电压表示，它确定了转换器能够接受的输入电压范围。
为什么AD通道额定值重要？AD通道额定值的重要性在于确定了模拟输入信号的有效范围，超出这个范围的信号可能会导致转换器输出的失真，甚至损坏转换器。
因此，确保将输入信号限制在AD通道额定值范围内是非常重要的。
如何确定AD通道额定值？AD通道额定值一般由以下几个因素决定：1. 功耗：较高的AD通道额定值将导致较高的功耗。
因此，根据设备需要的功耗情况来确定AD通道额定值可以有效平衡功耗与精度之间的关系。
2. 设备精度要求：AD通道额定值与设备的精度要求密切相关。
如果需要较高的精度，通常需要较高的AD通道额定值。
3. 信号范围：根据输入信号的实际范围来确定AD通道额定值非常重要。
例如，如果输入信号的幅值范围为0-5V，则需要选择至少为5V的AD通道额定值，以确保不会超过该范围。
4. 噪声：AD通道额定值还应考虑输入信号中的噪声。
噪声可能会导致精度的下降，因此需要选择一个相对较高的AD通道额定值来抵消噪声带来的影响。
如何配置AD通道额定值？配置AD通道额定值需要了解具体的硬件设备和使用的转换器。
一般来说，AD通道额定值可以通过设备的配置寄存器或软件来进行设置。
在配置AD通道额定值时，可以使用下列步骤：1. 根据设备的需求和规格手册，确定所需的AD通道额定值范围。
2. 找到设备的配置寄存器或软件界面，进入配置模式。
3. 在配置模式下，找到与AD通道相关的设置项，例如AD通道顺序、分辨率和参考电压等。
4. 根据需要，选择合适的AD通道额定值，并将其设置为所需值。
5. 保存配置并退出配置模式。
需要注意的是，在配置AD通道额定值时，应确保参考电压与AD通道匹配，以获得准确的转换结果。
总结：AD通道额定值是模拟数字转换器中用来表示模拟量输入范围的数值。
内含低噪声可编程增益放大器的24位∑-Δ模数转换器
内含低噪声可编程增益放大器的24位∑-Δ模数转换器
1 概述
AD1555 是一种过抽样∑-Δ调整器，它内含一个可编程增益放大器（programmable gain amplifier,PGA）可用于低频、大动态范围的测量领域，该器件在技术上采用模拟输入线性输出方式，它与AD1556 数字滤波器/抽样器结合使用可构成一款高性能的模数转换器。
由于使用了连续时间模拟调制器，因此，它们不需要外部去阶梯滤波器。
此外，采用可编程增益前后简化系统的设
计方法还扩大了动态范围，减小了电路板的面积。
同时低功耗和备用模拟的采
用更使得AD1555 在电池供电数据采集系统中成为理想的应用选择。
AD1555 是一种采用BICMOS 器件。
它是一种高性能的双极CMOS 晶体管组成的模拟器件。
AD1555 和AD1556 分别采用28 脚和44 脚封装。
2 引脚功能
AD1555 和AD1556 的引脚排列如图1 所示。
2.1 AD1555 的引脚定义AD1555 的引脚定义如下：
AGND1（1 脚）：模拟地；
PGAOUT（2 脚）：可编程增益放大器输出；
+VA：（3，26 脚）：模拟电源电压正端，额定值为+5V；
-VA：（4，20，21 脚）：模拟电源电压负端，额定值为-5V；
AIN（+）（5 脚）：多路复合输入，用于输入PGA 多路复合输入的非逆变信号；
AIN（-）（6 脚）：多路复合输入，用于输入PGA 多路复合输入的逆变信号；TIN（+）（7 脚）：多路复合输入，用于输入PGA 多路复合输入的逆变检测。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
116.5 120
116 120
dB
116 119.5
115.5 119.5
dB
114 117.5
114 117.5
dB
104.5 109.5
104.5 109.5
dB
98
98
dB
–120 –111
–120 –107
dB
–116 –108
–116 –107
dB
–116 –106
95
102
91.5 102
dB
PGA Gain of 8.5, 34
95.5 108
94.5 108
dB
PGA Gain of 128
108
108
dB
Power Supply Rejection Ratio7
50
50
dB
AIN to TIN Crosstalk Isolation Differential Input Current
–116 –105
dB
–115 –101
–115 –101
dB
–108
–108
dB
300
300
ps
122
122
dB
DC ACCURACY Absolute Gain Error5
Gain Stability Over Temperature5 Offset5, 6 Offset Drift5, 6
PGA Gain of 1, 2.5 PGA Gain of 8.5 PGA Gain of 34
CLKIN SYNC BW0...BW2 RESET PWRDN GND VL
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
AIN, TIN Inputs
140
140
MΩ
Common-Mode Range
± 2.25
± 2.25 V
Common-Mode Rejection Ratio VCM = ± 2.25 V, fIN = 200 Hz
PGA Gain of 1
93
101
91
101
dB
PGA Gain of 2.5
The continuous-time analog modulator input architecture avoids the need for an external antialias filter. The programmable gain front end simplifies system design, extends the dynamic range, and reduces the system board area. Low operating power and standby modes makes the AD1555 ideal for remote battery-powered data acquisition systems.
0 –20 –40 –60 –80 –100
fIN = 24.4Hz SNR = 116.7dB THD = –120.6dB
AMPLITUDE – dBr
–120 –140 –160
–180
–200 0
50 100 150 200 250 300 350 400 450 500 FREQUENCY – Hz
AD1555/AD1556
AD1555–SPECIFICATIONS (+VA = +5 V; –VA = –5 V; VL = 5 V; AGND = DGND = 0 V; MCLK = 256 kHz; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
STATUS REGISTER
INPUT MUX
DIGITAL FILTER
DATA OUTPUT
MUX
CLOCK DIVIDER
DATA REGISTER
AD1556
DIN SCLK CS R/W
DOUT
DRDY RSEL
AGND1
REV. B
PGAOUT MODIN AGND2 +VA –VA
VL DGND
The AD1555 is fabricated on Analog Devices’ BiCMOS process that has high performance bipolar devices along with CMOS transistors. The AD1555 and AD1556 are packaged, respectively, in 28-lead PLCC and 44-lead MQFP packages and are specified from –55°C to +85°C (AD1556 and AD1555 B Grade) and from 0°C to 85°C (AD1555 A Grade).
V
130
130
µA
DIGITAL INPUTS OUTPUTS
VIL VIH IIL IIH VOL VOH
ISINK = +2 mA ISOURCE = –2 mA
–0.3
+0.8 –0.3
+0.8
V
2.0
VL + 0.3 2.0
VL + 0.3 V
–10
+10
–10
+10
µA
–10
+10
–10
+10
fIN = 200 Hz
130
130
dB
1PERATURE RANGE8 Specified Performance
REFERENCE INPUT9 Input Voltage Range Input Current
TMIN to TMAX
–55
+85
0
85
°C
2.990 3.0 3.010 2.990 3.0 3.010
high dynamic range measurement applications. The AD1555 outputs a ones-density bitstream proportional to the analog input. When used in conjunction with the AD1556 digital filter/ decimator, a high performance ADC is realized.
APPLICATIONS Seismic Data Acquisition Systems Chromatography Automatic Test Equipment
GENERAL DESCRIPTION The AD1555 is a complete sigma-delta modulator, combined with a programmable gain amplifier intended for low frequency,
Notes
AD1555BP Min Typ Max
AD1555AP Min Typ Max
Unit
PGA Gain Settings
1, 2.5, 8.5, 34, 128
AC ACCURACY Dynamic Range1
Total Harmonic Distortion2
Jitter Tolerance3 Intermodulation Distortion4
Figure 1. FFT Plot, Full-Scale AIN Input, Gain of 1
FUNCTIONAL BLOCK DIAGRAM
AIN (+) AIN (–)
TIN (+) TIN (–)
REFIN REFCAP2 REFCAP1 AGND3
REF DIVIDER DAC
MODE CONTROL LOGIC
Input Impedance
MODIN
20
20
k⍀
Full-Scale Differential Input
PGA Gain of 1
± 2.25
± 2.25 V
Other PGA Gain Settings
See Table I
See Table I
Differential Input Impedance
OVERVOLTAGE DETECTION
PGA MUX
LOOP FILTER
AD1555
CLOCK GENERATION
CB0...CB4
MFLG CSEL
TDATA MDATA
MCLK
PGA0...PGA4 H/S
ERROR
PGA CONTROL
CONFIGURATION REGISTER